BD9775FV

TECHNICAL NOTE Large Current External FET Controller Type Switching Regulator Step-down, High-efficiency Switching Regulators (Controller type) BD9011EKN , BD9011KV , BD9775FV ■ BD9011EKN, BD9011KV ●Overview The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It supports a wide input range, enabling low power consumption ecodesign for an array of electronics. ●Features 1) Wide input voltage range: 3.9V to 30V 2) Precision voltage references: 0.8V±1% 3) FET direct drive 4) Rectification switching for increased efficiency 5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz) 6) Built-in selected OFF latch and auto remove over current protection 7) Built-in independent power up/power down sequencing control 8) Make various application , step-down , step-up and step-up-down 9) Small footprint packages: HQFN36V, VQFP48C ●Applications Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players, etc. ●Absolute Maximum Ratings (Ta=25℃) Parameter EXTVCC Voltage VCCCL1,2 Voltage CL1,2 Voltage SW1,2 Voltage BOOT1,2 Voltage BOOT1,2-SW1,2 Voltage STB, EN1,2 Voltage VREG5,5A VREG33 SS1,2､FB1,2 Symbol EXTVCC VCCCL1,2 CL1,2 SW1,2 BOOT1,2 BOOT1,2-SW1,2 STB, EN1,2 VREG5,5A VREG33 SS1,2､FB1,2 Rating 34 34 *1 *1 Unit V V V V V V V V V V Parameter COMP1,2 Voltage DET1,2 Voltage RT､SYNC Voltage Symbol COMP1,2 DET1,2 RT､SYNC Rating VREG5 Unit V 34 34 40 7 *1 *1 0.875 （HQFN36V） Power Dissipation Pd 1.1 （VQFP48C） *2 *2 W *1 W VCC 7 VREG5 VREG5 Operating temperature Storage temperature Junction temperature Topr Tstg Tj -40 to +105 -55 to +150 +150 ℃ ℃ ℃ *1 Regardless of the listed rating, do not exceed Pd in any circumstances. *2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/℃（HQFN36V） or 8.8mW/℃（VQFP48C） above 25℃. Sep. 2008 ●Operating conditions (Ta=25℃) Parameter Input voltage 1 Input voltage 2 BOOT－SW voltage Carrier frequency Synchronous frequency Synchronous pulse duty Min OFF pulse *1 After more than 4.5V, voltage range. *2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5. Symbol EXTVCC VCC BOOT－SW OSC SYNC Duty TMIN Min. 3.9 *1 *2 Typ. 12 12 5 300 50 100 Max. 30 30 VREG5 550 550 60 - Unit V V V kHz kHz ％ nsec 3.9 *1 *2 4.5 250 OSC 40 - ★This product is not designed to provide resistance against radiation. ●Electrical characteristics (Unless otherwise specified, Ta=25℃ VCC=12V STB=5V EN1,2=5V) Parameter VIN bias current Shutdown mode current ［Error Amp Block］ Feedback reference voltage Feedback reference voltage (Ta=-40 to 105℃) Open circuit voltage gain VO input bias current ［FET Driver Block］ HG high side ON resistance HG low side ON resistance LG high side ON resistance LG low side ON resistance ［Oscillator］ Carrier frequency Synchronous frequency ［Over Current Protection Block］ CL threshold voltage CL threshold voltage （Ta=-40 to 105℃） ［VREG Block］ VREG5 output voltage VREG33 reference voltage VREG5 threshold voltage VREG5 hysteresis voltage ［Soft start block］ Charge current ISS 6.5 10 13.5 14 μA μA VSS=1V VSS=1V,Ta=-40 to 105℃ ※ Charge current ISS+ 6 10 (Ta=-40 to 105℃) Note: Not all shipped products are subject to outgoing inspection. 2/29 VREG5 VREG33 VREG_UVLO DVREG_UVLO 4.8 3.0 2.6 50 5 3.3 2.8 100 5.2 3.6 3.0 200 V V V mV IREF=6mA IREG=6mA VREG:Sweep down VREG:Sweep up Vswth Vswth+ 70 67 90 90 110 113 ｍV ｍV Ta=-40 to 105℃ ※ FOSC Fsync 270 300 500 330 kHz kHz RT=100 kΩ RT=100 kΩ,SYNC=500kHz HGhon HGlon LGhon LGlon 1.5 1.0 1.5 0.5 Ω Ω Ω Ω VOB VOB+ Averr IVo+ 0.792 0.784 0.800 0.800 46 0.808 0.816 1 V V dB μA Ta=-40 to 105℃ ※ Symbol IIN IST Limit Min. Typ. 5 0 Max. 10 10 Unit mA μA VSTB=0V Conditions ●Reference data (Unless otherwise specified, Ta=25℃) 100 90 80 EFFICIENCY[%] 70 60 50 40 30 20 10 0 0 2.6V 3.3V 5.0V 100 90 3.3V CIRCUIT　CURRENT[mA] 80 EFFICIENCY[%] 6 5 1.8V 1.2V 70 60 50 40 30 20 5.0V 4 3 2 1 0 105℃ 25℃ -40℃ VIN=12V 1 2 OUTPUT CURRENT：Io[A] 3 10 0 6 9 Io=2A 12 15 18 21 INPUT VOLTAGE ： VIN[V] 24 0 10 20 INPUT VOLTAGE：VIN[V] 30 Fig.1 Efficiency 1 Fig.2 Efficiency 2 Fig.3 Circuit current 0.816 REFERENCE VOLTAGE ： VOB[V] 過電流検出電圧 ： Vswth[mV] 0.812 0.808 0.804 0.800 0.796 0.792 0.788 0.784 -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE ： Ta[℃] 110 OSILATING FREQUENCY ： F [kHz] OSC 330 320 310 300 290 280 270 RT=100kΩ 100 90 80 70 60 -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE ： Ta[℃] -40 -15 10 35 60 85 110 AMBIENT TEMPERATURE ： Ta[℃] Fig.4 Reference voltage vs. temperature characteristics 5.25 5.00 OUT PUT VOLTAGE ： Vo[V] Fig.5 Over current detection vs. temperature characteristics 6 5 OUT PUT VOLTAGE ： Vo[V] 3.0 2.5 Fig.6 Frequency vs. temperature characteristics 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 -40 -15 10 OUT PUT VOLTAGE ： Vo[V] VREG5 5.0V 4 3 RCL=15mΩ 2.0 1.5 3.3V 2 1 0 0 5 10 15 20 INPUT VOLTAGE ： VIN[V] 25 LOFF=H 1.0 VREG33 LOFF=L 0.5 0.0 0 1 2 3 4 5 6 OUTPUT CURRENT: Io[A] 35 60 85 110 AMBIENT TEMPERATURE ： Ta[℃] Fig.7 Internal Reg vs. temperature characteristics 6 Fig.8 Line regulation Fig.9 Load regulation OUTPU T　VOLTAGE ： Vo[V] 5 50mV/div VOUT VOUT 50mV/div 4 105℃ 3 25℃ 2 1 0 0 2 4 INPUT VOLTAGE：V EN[V] 6 -40℃ IOUT 1A/div IOUT 1A/div Fig.10 EN threshold voltage Fig.11 Load transient response 1 Fig.12 Load transient response 2 3/29 ●Block diagram (Parentheses indicate VQFP48C pin numbers) EXTVCC 22 (41) 5V Reg STB VCC 10 (25) 32 (7) RT 15 (33) SYNC 16 (34) 3.3V Reg VREG5 24(44) B.G SYNC 5(19) 17(35) UVLO TSD 2.7V VREG33 LLM VCCCL1 CL1 BOOT1 OUTH1 SW1 VREG5A OUTL1 DGND1 FB1 SS1 COMP1 TSD OSC 33(8) 34(10) VCCCL2 CL2 BOOT2 OUTH2 SW2 OUTL2 DGND2 FB2 SS2 COMP2 31(5) 30(3) 29(2) 28(1) 27(48) OCP Set DRV Reset Set Reset DRV OCP 35(11) 36(12) SW VREG5 SW TSD UVLO Q Reset Set PW M COMP TSD UVLO 1(13) 4(17) 3(15) 2(14) LOGIC LOGIC 25(46) 26(47) 21(39) 19(37) 20(38) － ＋ ＋ 0.8V Slope Slope PW M COMP Q Set Reset Err Amp Err Amp 6(21) 8(23) 0.8V UVLO Ｏ 7(22) Q Q Reset Sequence DET Set Set Reset Sequence DET 0.56V 0.56V 18 (36) 14 (31) 12 (27) 11 (26) (30) 13 (29) 9 (24) DET2 LOFF EN2 EN1 (GNDS) GND DET1 Fig-13 ●Pin configuration BD9011EKN（HQFN36V） EXTVCC ●PIN function table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name SW1 DGND1 OUTL1 VREG5A VREG33 FB1 COMP1 SS1 DET1 STB EN1 EN2 GND LOFF RT SYNC LLM DET2 SS2 COMP2 FB2 EXTVCC － VREG5 OUTL2 DGND2 SW2 OUTH2 BOOT2 CL2 VCCCL2 VCC VCCCL1 CL1 BOOT1 OUTH1 Function High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 FET drive REG input Reference input REG output Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1ON/OFF pin Output 2ON/OFFpin Ground Over current protection OFF latch function ON/OFF pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 External power input pin N.C. FET drive REG output Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 Hi side FET gate drive pin 2 OUTH2 driver power pin Over current detector setting pin 2 Over current detection VCC2 Input power pin Over current detection VCC1 Over current detector setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 COMP2 20 DGND2 VREG5 OUTL2 SW2 27 26 25 24 23 22 21 OUTH2 28 BOOT2 29 CL2 30 VCCCL2 31 VCC 32 VCCCL1 33 CL1 34 BOOT1 35 OUTH1 36 1 2 3 4 5 6 7 8 9 SS2 19 18 DET2 17 LMM 16 SYNC 15 RT 14 LOFF 13 GND 12 EN2 11 EN1 10 STB SW1 VREG33 FB1 FB2 COMP1 DGND1 OUTL1 SS1 VREG5A Fig-14 DET1 4/29 ●Pin configuration BD9011KV（VQFP48C） GNDS SYNC ●Pin function table Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name OUTH2 BOOT2 CL2 N.C VCCCL2 N.C VCC VCCCL1 N.C CL1 BOOT1 OUTH1 SW1 DGND1 OUTL1 N.C VREG5A N.C VREG33 N.C FB1 COMP1 SS1 DET1 STB EN1 EN2 N.C GND GNDS LOFF N.C RT SYNC LLM DET2 SS2 COMP2 FB2 N.C EXTVCC N.C N.C VREG5 N.C OUTL2 DGND2 SW2 Function High side FET gate drive pin 2 OUTH2 driver power pin Over current detection pin 2 Non-connect (unused) pin Over current detection VCC2 Non-connect (unused) pin Input power pin Over current detection CC1 Non-connect (unused) pin Over current detection setting pin 1 OUTH1 driver power pin High side FET gate drive pin 1 High side FET source pin 1 Low side FET source pin 1 Low side FET gate drive pin 1 Non-connect (unused) pin FET drive REG input Non-connect (unused) pin Reference input REG output Non-connect (unused) pin Error amp input 1 Error amp output 1 Soft start setting pin 1 FB detector output 1 Standby ON/OFF pin Output 1 ON/OFF pin Output 2 ON/OFF pin Non-connect (unused) pin Ground Sense ground Over current protection OFF latch function ON/OFF pin Non-connect (unused) pin Switching frequency setting pin External synchronous pulse input pin Built-in pull-down resistor pin FB detector output 2 Soft start setting pin 2 Error amp output 2 Error amp input 2 Non-connect (unused) pin External power input pin Non-connect (unused) pin Non-connect (unused) pin FET drive REG output Non-connect (unused) pin Low side FET gate drive pin 2 Low side FET source pin 2 High side FET source pin 2 LOFF DET2 GND 36 35 34 33 32 31 30 29 28 27 EN1 26 STB 25 24 DET1 23 SS1 22 COMP1 21 FB1 20 N.C 19 VREG33 18 N.C 17 VREG5A 16 N.C 15 OUTL1 14 DGND1 13 SW1 12 LLM SS2 37 COMP2 38 FB2 39 N.C 40 EXTVCC 41 N.C 42 N.C 43 VREG5 44 N.C 45 OUTL2 46 DGND2 47 SW2 48 1 2 3 4 5 6 7 8 9 10 11 EN2 N.C N.C RT BOOT2 BOOT1 N.C N.C VCC N.C OUTH2 VCCCL2 Fig-15 ●Block functional descriptions ・Error amp The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage. ・Oscillator (OSC) Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz. ・ SLOPE The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator. ・PWM COMP The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum. ・Reference voltage (5Vreg，33Vreg) This block generates the internal reference voltages: 5V and 3.3V. ・External synchronization (SYNC) Determines the switching frequency, based on the external pulse applied. ・Over current protection (OCP) Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low, and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch mode ends when the latch is set to STB, EN. ・Sequence control (Sequence DET) Compares FB voltage with reference voltage (0.56V) and outputs the result as DET. ・Protection circuits (UVLO/TSD) The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or exceeds 150℃. Output is restored when temperature falls back below the threshold value. VCCCL1 OUTH1 CL2 CL1 5/29 ●Application circuit example (Parentheses indicate VQFP48C pin numbers) VIN(12V) 100uF 15mΩ 100Ω 1nF 0.33 15mΩ 10 Ω 1nF 32 (7) SP8K2 RB160 VA-40 uF 100Ω SP8K2 RB160 VA-40 36 (12) 35 (11) 34 (10) 33 (8) 31 (5) 30 (3) 29 (2) 28 (1) (SLF12565：TDK) Vo(5V/3A) 10uH RB051 L-40 (SLF12565：TDK) 0.1 uF 10uH RB051 L-40 BOOT1 VCCCL1 VCCCL2 BOOT2 VCC 0.1 uF CL1 CL2 OUTH1 1(13) 2(14) 3(15) 4(17) 5(19) 6(21) OUTH2 SW2 DGND2 OUTL2 VREG5 27(48) 26(47) 25(46) 24(44) 23 Vo(3.3V/3A) SW1 DGND1 OUTL1 68kΩ 220uF (OS ｺﾝ) 220uF (OS ｺﾝ) 1uF 1uF 13kΩ 15000pF 39kΩ 0.1uF VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB 10 (25) 47kΩ 1uF EXTVCC FB2 COMP2 SS2 DET2 18 (36) 22(41) 21(39) 20(38) 19(37) 0.33uF 15kΩ 39kΩ 0.1uF 15000pF 7(22) 8(23) 9(24) GND EN1 EN2 11 (26) 12 (27) 13 (29) 14 (31) 15 (33) 16 (34) 100kΩ Fig-16A（Step-Down：Cout=OS Capacitor） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. VIN(12V) 100uF 23mΩ 100Ω 1nF 0.33 23mΩ 10 Ω 1nF 32 (7) SP8K2 RB160 VA-40 uF 100Ω LLM 17 (35) RT SP8K2 RB160 VA-40 36 (12) 35 (11) 34 (10) 33 (8) 31 (5) 30 (3) 29 (2) 28 (1) (SLF10145：TDK) Vo(1.8V/2A) 10uH RB051 L-40 (SLF10145：TDK) 0.1 uF 10uH RB051 L-40 VCCCL1 VCCCL2 BOOT1 0.1 uF OUTH1 1(13) 2(14) 3(15) BOOT2 CL1 VCC CL2 OUTH2 SW2 DGND2 OUTL2 VREG5 27(48) 26(47) 25(46) 24(44) 23 Vo(2.5V/2A) SW1 DGND1 OUTL1 3300pF 150Ω 15kΩ 30uF (C2012JB 0J106K ：TDK) 30uF 1uF (C2012JB 0J106K ：TDK) 43 kΩ 1000pF 510Ω 1uF 1uF 330pF 4(17) 5(19) 6(21) VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB 10 (25) EXTVCC FB2 COMP2 SS2 DET2 18 (36) 22(41) 21(39) 12kΩ 10000pF 0.33uF 330pF 20kΩ 3.3kΩ 3300pF 0.1uF 7(22) 1k Ω 0.1uF 8(23) 9(24) 20(38) 19(37) GND EN1 EN2 11 (26) 12 (27) 13 (29) 14 (31) 15 (33) 16 (34) 100kΩ Fig-16B（Step-Down：Cout=Ceramic Capacitor） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. 6/29 LLM 17 (35) RT VIN(12V) 100uF 10mΩ 100Ω 1nF 0.33 10mΩ 10 Ω 1nF 32 (7) Vo(24V/1A) RB051L-40 L1 (SLF12565：TDK) 27uH ＊REGSPIC 100Ω TM uF SP8K2 RB160 VA-40 27(48) 26(47) Co1 1000pF 680 kΩ 5.1kΩ RSS 065N03 220uF 1uF 1(13) 2(14) 3(15) 4(17) 5(19) 6(21) 7(22) 36 (12) 35 (11) 34 (10) 33 (8) 31 (5) 30 (3) 29 (2) 28 (1) BOOT1 VCCCL1 VCCCL2 BOOT2 VCC OUTH1 SW1 DGND1 OUTL1 OUTH2 SW2 DGND2 OUTL2 VREG5 0.1 uF CL1 CL2 (SLF12565：TDK) L2 27uH Do3 Vo(12V/1A) Co2 25(46) 24(44) 23 1uF 1uF 23.5kΩ 22000pF 1000pF 10kΩ 0.1uF VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB 10 (25) 1uF RB051 L-40 220 uF 91 kΩ 3300pF 10kΩ EXTVCC FB2 COMP2 SS2 DET2 18 (36) 22(41) 21(39) 0.33uF 1000pF 6.2kΩ 4.7kΩ 0.1uF 22000pF 8(23) 9(24) 20(38) 19(37) GND EN1 EN2 11 (26) 12 (27) 13 (29) 14 (31) 15 (33) 16 (34) LLM 17 (35) RT 100kΩ ＊ REGSPICTM is Trade Mark of RHOM Fig-16C（Step-Down：Low Input Voltage） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. VIN(5V) 100uF 23mΩ 100Ω 1nF 0.33 23mΩ 10 Ω 1nF 32 (7) SP8K2 RB160 VA-40 uF 100Ω SP8K2 RB160 VA-40 36 (12) 35 (11) 34 (10) 33 (8) 31 (5) 30 (3) 29 (2) 28 (1) (SLF10145：TDK) Vo(1.8V/2A) 6.8uH RB051 L-40 0.1uF VCCCL1 VCCCL2 BOOT1 OUTH1 1(13) 2(14) 3(15) 4(17) 5(19) 6(21) 7(22) BOOT2 CL1 VCC CL2 0.1uF OUTH2 SW2 DGND2 OUTL2 VREG5 27(48) 26(47) 25(46) 24(44) 23 (SLF10145：TDK) 6.8uH Vo(2.5V/2A) RB051 L-40 SW1 DGND1 OUTL1 3300pF 100Ω 15kΩ 30uF (ｾﾗｺﾝ) 30uF (ｾﾗｺﾝ) 43 kΩ 1000pF 300Ω 1uF 1uF 12kΩ 4700pF 100pF 3.3kΩ 0.1uF VREG5A VREG33 FB1 COMP1 SS1 SYNC LOFF DET1 STB 10 (25) 1uF EXTVCC FB2 COMP2 SS2 DET2 18 (36) 22(41) 21(39) 0.33uF 33pF 20kΩ 10kΩ 0.1uF 2200pF 8(23) 9(24) 20(38) 19(37) GND EN1 EN2 11 (26) 12 (27) 13 (29) 14 (31) 15 (33) 16 (34) 100kΩ Fig-16D（Step-Up：and Step-Up-Down） There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics. Please verify and confirm using practical applications. 7/29 LLM 17 (35) RT ●Application component selection (1) Setting the output L value The coil value significantly influences the output ripple current. Thus, as seen in equation (5), the larger the coil, and the higher the switching frequency, the lower the drop in ripple current. ΔIL = （VCC-VOUT）×VOUT L×VCC×f [A]・・・ 5） （ Δ IL Fig-17 VCC IL L Co VOUT The optimal output ripple current setting is 30% of maximum current. ΔIL = 0.3×IOUTmax.[A]・・・ 6） （ L= （VCC-VOUT）×VOUT ΔIL×VCC×f [H]・・・ 7） （ Fig-18 Output ripple current （ΔIL：output ripple current f：switching frequency） ※Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency. Please establish sufficient margin to ensure that peak current does not exceed the coil current rating. ※Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency. (2) Setting the output capacitor Co value Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage (at rapid load change). The following equation is used to determine the output ripple voltage. Step down ΔVPP = ΔIL × RESR + ΔI L × Co Vcc Vo × f 1 [V] Note: f：switching frequency Be sure to keep the output Co setting within the allowable ripple voltage range. ※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable lower output ripple voltage. Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in the conditions described in the capacitance equation (9) for output capacitors, below. Co ≦ TSS × (Limit – IOUT) VOUT ・・・ （9） Tss： soft start time ILimit：over current detection value（2/16）reference Note: less than optimal capacitance values may cause problems at startup. (3) Input capacitor selection VIN Cin VOUT L Co The input capacitor serves to lower the output impedance of the power source connected to the input pin (VCC). Increased power supply output impedance can cause input voltage (VCC) instability, and may negatively impact oscillation and ripple rejection characteristics. Therefore, be certain to establish an input capacitor in close proximity to the VCC and GND pins. Select a low-ESR capacitor with the required ripple current capacity and the capability to withstand temperature changes without wide tolerance fluctuations. The ripple current IRMSS is determined using equation (10). IRMS = IOUT × VOUT（VCC - VOUT） [A]・・・ 10） （ VCC Also, be certain to ascertain the operating temperature, load range and MOSFET conditions for the application in which the capacitor will be used, since capacitor performance is heavily dependent on the application’s input power characteristics, substrate wiring and MOSFET gate drain capacity. 8/29 Fig-19 Input capacitor (4) Feedback resistor design Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Vo Internal ref. 0.8V R8 FB R9 Fig-20 Vo = R8 +R9 R9 × 0.8 [V] ・・・ 11） （ (5) Setting switching frequency The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when unsupported resistance values are used. 550 500 周波数 [ kHz ] 450 400 350 300 250 50 60 70 80 90 RT [ kΩ] 100 110 120 130 Fig-21 RT vs. switching frequency (6) Setting the soft start delay The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right. 10 DELAY TIME[ms] 1 0.8V(typ.)×CSS TSS = ISS(10μA Typ.) [sec]・・・(12) 0.1 0.01 0.001 0.01 SS CAPACITANCE[uF] 0.1 Fig-22 SS capacitance vs. delay time Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input voltage, output voltage and capacitance, coils and other characteristics. 9/29 (7) Setting over current detection values The current limit value（ILimit）is determined by the resistance of the RCL established between CL and VCCCL. VCCCL CL VIN RCL IL L Vo IL Over current detection point ILimit = 90m RCL [A]・・・(13) Fig-23 Fig-24 There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin. ・LOFF=L (0