BD9850FVM

TECHNICAL NOTE Large Current External FET Controller Type Switching Regulators Single-output High-frequency Step-down Switching Regulator(Controller type) BD9850FVM High temperature operating ESD Resistance Now available Now available Dual-output Step-up, Negative, Step-down Switching Regulator(Controller type) BD9851EFV Description The BD9850FVM is a 1-channel DC/DC step-down switching regulator controller, while the BD9851EFV is a 2-channel DC/DC step-down switching regulator controller. The BD9850FVM is adaptable for a maximum switching frequency of 2 MHz and the BD9851EFV for that of 3 MHz. Both provide space saving in all applications. Features 1) Adaptable for 2-MHz switching frequency (externally variable) (BD9850FVM) Adaptable for 3-MHz switching frequency (externally variable) (BD9851EFV) 2) FET direct drive 3) High-accuracy reference voltage (Accuracy: ±1%) 4) Built-in Under Voltage Lock Out circuit (UVLO) 5) Built-in Thermal Shutdown circuit (TSD) 6) The BD9851EFV provides two channels: Channel 1 available for selection of step-down/step-up switching Channel 2 available for selection of step-down/inverting switching. 7) Compact MSOP8 package (BD9850FVM) / HTSSOP-B20 package (BD9851EFV) Applications TFT panel, TA / Router, digital consumer electronics, PC, and portable CD/DVD/DVC Product lineup Input range Oscillation frequency range External synchronization Standby function Operating temperature Package BD9850FVM 4V to 9V 100kHz to 2MHz Not provided Not provided – 40˚C to 85˚C MSOP8 BD9851EFV 4V to 18V 10kHz to 3MHz Not provided Provided –40˚C to 85˚C HTSSOP-B20 Sep. 2008 ROHM CO., LTD . Absolute maximum ratings ( Ta=25˚C) BD9850FVM Item Power supply voltage Storage temperature Operating temperature Power dissipation Maximum junction temperature Symbol Vcc Tstg Topr Pd Tjmax Rating 10 –55 to +150 –40 to +85 587 * +150 Unit V ºC ºC mW ºC *Reduce by 4.7 mW/ºC over 25ºC (When mounted on PCB of 70mm ×70mm ×1.6mm) BD9851EFV Item Power supply voltage (Between Vcc and GND) Between VREF and GND Between OUT1 and PVcc1 Between OUT2 and PVcc2 Between OUT1, OUT2 and PGND Power dissipation Operating temperature Maximum junction temperature Storage temperature Symbol Vcc VREF Vouth Voutl Pd Topr Tjmax Tstg Rating 20 7 20 20 1000 (*) Unit V V V V mW ºC ºC ºC –40 to +85 +150 –55 to +150 (*)Reduce by 8.0 mW/ ºC over 25ºC (When mounted on PCB of 70mm ×70mm ×1.6mm) Recommended operating range BD9850FVM Item Power supply voltage Oscillation frequency Operating temperature Symbol Vcc fosc Topr min. 4 100 –40 Limits Typ. 7 – – max. 9 2000 + 85 Unit V kHz ºC BD9851EFV Item Power supply voltage Oscillation frequency Timing resistor Timing capacitor Symbol Vcc fosc RRT CCT min. 4 10 3.3 33 Limits Typ. 12 300 – – max. 18 3000 47 10000 Unit V kHz kΩ pF 2/16 BD9850FVM Electrical characteristics (Unless otherwise specified, Ta=25˚C, Vcc=7V, fosc=600kHz) Limits Item Symbol min. Typ. max. [Oscillator block] Oscillation frequency Frequency regulation Oscillator amplitude voltage [Soft start / SW block] CTL/SS pin sink current CTL / SS pin clamp voltage CTL threshold voltage [PWM comparator block] 0% threshold voltage 100% threshold voltage [Error Amp block] Threshold voltage Frequency bandwidth Voltage gain Input bias current Maximum output voltage Minimum output voltage Output source current Output sink current [VREF block] VREF output voltage FREF load regulation VREF current capacitance [Total device] Standby current Average supply current [Output block] ON resistance Output transient time [Under voltage lockout block] Threshold voltage Hysteresis width VUT VUThy 3.7 0.05 3.8 0.10 3.9 0.15 V V Vcc sweep down RON Tr/ Tf 0.9 – 2.5 20 8.0 – Ω nsec Cout = 1000pF ICCS ICCA 420 3.4 610 5.0 960 7.8 μA mA At no load VREF ΔVREFl0 IVREF 2.475 – –45 2.500 – –16 2.525 10 –1 V mV mA IVREF = 0mA IVREF = 0mA to –1mA VIN BW Av IIB VCH VCL IOl IOO 0.98 1.5 – –150 2.3 – –3.1 12 1.00 3.0 70 –70 2.4 0.03 –1.6 50 1.02 – – – 2.6 0.20 –1.0 125 V MHz dB hA V V mA mA VFB = 1.0V VFB = 1.0V AV = 0dB D0 D100 1.5 2.0 1.6 2.1 1.7 2.2 V V fosc = 600kHz fosc = 600kHz ISS VSS VCTLTH –1.90 2.2 1.2 –1.00 2.4 1.3 1.00 2.6 1.4 μA V V VCTL/SS = 1.5V fosc FDV Vpptr 510 –5 – 600 0 0.5 690 5 – kHz % V RRT = 24kΩ Vcc = 4V to 9V Unit Conditions * * * * *Design guarantee *Not designed to be radiation-resistant. 3/16 BD9851EFV Electrical characteristics (Unless otherwise specified, Ta=25˚C, Vcc=12V, fosc=300kHz, STB=3V) Limits Item Symbol Unit min. Typ. max. [Total device] Standby mode circuit current Operation mode circuit current [Reference voltage block] Output voltage Input stability Load stability Short circuit mode output current [Oscillator block] Oscillation frequency Oscillation frequency regulation [Error Amp block] Threshold voltage Input offset voltage Common-mode input voltage range Input bias current Voltage gain Frequency bandwidth Maximum output voltage Minimum output voltage Output sink current Output source current [PWM comparator block] 0% threshold voltage 100% threshold voltage DTC bias current [FET driver block] RONN ON resistance RONP Vselh Vsell [Control block] Threshold voltage Sink current Vstb Istb 0.6 6 1.5 15 1.5 15 V μA STB = 3V 1.5 1 Vcc – 0.2 0 3 2 – – 3 2 – – Ω Ω V V When OUT= Lo When OUT=Hi In step-down switching In step-down switching Vth0 Vth100 Idtc 1.21 1.74 –1 1.31 1.84 – 1.41 1.94 1 V V μA FB voltage FB voltage Vthea Vofst Vcm Ibias Av Bw Vfbh Vfbl Isink Isource 0.98 –10 0.3 –150 60 3 VREF –0.1 – 1.6 –260 1.00 0 – –70 75 6 – – 6 –160 1.02 10 2.0 – 90 13 VREF 0.1 16 –90 V mV V nA dB MHz V V mA μA FB pin FB pin DC * Design guarantee MHz * Design guarantee Ch1 Ch2 Ch2 fosc Dfosc 270 –2 300 0 330 2 kHz % RRT=24kΩ, CCT=220pF Vcc=4Vto18V VREF DVli DVlo Ios 2.475 – – – 45 2.500 – – –12 2.525 10 10 –3 V mV mV mA Io=–0.1mA Vcc=4Vto18V, Io=–0.1mA Io=–0.1mA to –1mA Iccst Icc – 1.5 – 2.5 5 4.1 μA mA STB=0V FB1, FB2=0V Conditions SEL1 input voltage range [Short circuit protection circuit (SCP) block] Timer start voltage Threshold voltage Standby mode voltage Source current Vtime Vthscp Vstscp Vsoscp 2.2 1.4 – –3.2 2.3 1.5 10 –2.0 2.3 1.5 10 –2.0 V V mV μA FB voltage SCP voltage SCP voltage SCP=0.75V [Under voltage lockout block (UVLO)] Threshold voltage Hysteresis width Vuvlo DVuvlo 3.58 0.05 3.7 0.11 4/16 3.7 0.11 V V Vcc sweep down *Design guarantee Characteristic data (BD9850FVM) 1.02 1.015 100 90 87 ERROR-AMP. THRESHOLD VOLTAGE : VINV(V) 1.01 70 1.005 1 0.995 0.99 0.985 10 0.98 –40 –20 0 20 40 60 80 0 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 ON DUTY : DON(%) AMBIENT TEMPERATURE : Ta(˚C) 60 50 40 30 20 FB VOLTAGE : VFB(V) Fig.1 Error Amp threshold voltage vs. Ambient temperature Fig.2 FB voltage vs. ON Duty 1000 900 1000 900 800 OUT SOURCE CURRENT : IOUT [mA] 800 700 600 500 400 300 200 100 0 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Vcc=10V Vcc=10V Vcc=7V OUT SINK CURRENT : IOUT [mA] 700 600 500 400 300 200 100 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Vcc=7V Vcc=4V Vcc=4V (VCC-OUT)VOLTAGE : VO(V) OUT VOLTAGE : VO(V) Fig.3 (Vcc-OUT) Voltage vs. Output source current Fig.4 Output voltage vs. Output sink current 2.53 650 640 OSCILLATING FREQUENCY : FOSC [kHz] 2.52 630 620 610 RT=24kΩ 600 590 580 570 560 550 –40 –20 0 20 40 60 80 VREF VOLTAGE:VREF [ V] 2.51 2.5 2.49 2.48 2.47 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE : Ta [˚C] AMBIENT TEMPERATURE : Ta [˚C] Fig.5 VREF vs. Ambient temperature Fig.6 Oscillation frequency vs. Ambient temperature 5/16 (BD9851EFV) 1.02 100 90 80 ERROR-AMP. THRESHOLD VOLTAGE : VEATH (V) 1.015 1.01 1.005 1 0.995 0.99 0.985 0.98 –40 –20 0 20 40 60 80 ON DUTY : DON (%) 70 60 50 40 30 fosc=1MHz 20 10 0 1.2 1.3 1.4 1.5 1.6 1.7 1.8 19 fosc=300kHz AMBIENT TEMPERATURE : Ta(˚C) DTC VOLTAGE : VDTC (V) Fig.7 Error Amp threshold voltage vs. Ambient temperature Fig.8 FB voltage vs. ON Duty 1000 1000 Vcc=20V 900 900 OUT SOURCE CURRENT : IOUT (mA) OUT SINK CURRENT : IOUT (mA) 800 800 700 600 Vcc=12V 700 600 500 400 300 200 100 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Vcc=20V Vcc=12V 500 400 300 200 100 0 0 0.5 0 1.5 2 2.5 3 3.5 4 Vcc=4V Vcc=4V (Vcc-OUT) VOLTAGE : VO(V) OUT VOLTAGE : VO (V) Fig.9 (Vcc-OUT) Voltage vs. Output source current Fig.10 Output voltage vs. Output sink current 2.55 2.54 2.53 320 315 RRT=24kΩ CCT=220pF OSCILLATING FREQUENCY : FOSC (kHz) –20 0 20 40 60 80 REFERENCE VOLTAGE : VREF ( V) 310 305 300 295 290 285 280 –40 –20 0 20 40 60 80 2.52 2.51 2.5 2.49 2.48 2.47 2.46 2.45 –40 AMBIENT TEMPERATURE : Ta(˚C) AMBIENT TEMPERATURE : Ta(˚C) Fig.11 VREF vs. Ambient temperature Fig.12 Oscillation frequency vs. Ambient temperature 6/16 Block diagram / Pin assignment (BD9850FVM) Vcc Vcc 1 VREF 4 RT 8 Vcc TRI Vcc U.V.L.O VREF INV 5 Error Amp 1.0V 6 T.S.D 2 Clamper VREF PWM COMP OUT Vo FB 7 CTL/SS GND 3 CTL/ SS Fig.13 BD9850FVM Block diagram INV FB RT Pin No. 1 2 3 4 5 6 Pin name Vcc OUT GND VREF INV FB CTL /SS RT Power supply FET driver drive output Ground Function Reference voltage (2.5V±1%) output Error Amp inverting input Error Amp output Control/Soft start common Oscillation frequency setting resistor connection GND OUT VREF Vcc 7 8 (BD9851EFV) Vcc Vcc 18 VREF 17 VREF (2.5V) Both channels ON/OFF 19 STB Pin No. 1 Vcc Pin name SEL1 RT CT NON2 INV2 FB2 DTC2 PVCC2 OUT2 PGND OUT1 PVCC1 DTC1 SCP FB1 INV1 VREF VCC STB GND FIN on reverse Function CH1 drive FET setting (Vcc short: P-ch drive, GND short: N-ch drive) Oscillation frequency setting resistor connection Oscillation frequency setting capacitor connection Error Amp non-inverting input (CH2) Error Amp inverting input (CH2) Error Amp output (CH2) Maximum duty/soft start setting (CH2) FET driver block power supply input (CH2) FET driver block output (CH2) FET driver block ground FET driver block output (CH1) FET driver block power supply input (CH1) Maximum duty/soft start setting (CH1) Short circuit protection timer setting capacitor connection Error Amp output (CH1) Error Amp inverting input (CH1) Reference voltage (2.5V±1%) output Power supply input ON/OFF control Ground Make FIN on the reverse open or ground to GND (pin 20) (However, open FIN on the reverse will degrade radiation performance.) FB1 Vo1 2 3 Vcc 15 1 SEL1 PVcc1 12 INV1 16 4 5 – + – – + OUT1 11 6 Vo1 VREF DTC1 1V 7 8 13 + + – PGND 10 9 10 Vcc FB2 Vo2 6 2.3V 11 PVcc2 8 VREF INV1 NON2 VREF DTC2 7 5 4 – + – – + OUT2 9 12 13 14 Vo2 15 RT CT 2 OSC 3 GND 20 16 17 18 19 SCP 14 Tmer Latch Fig.14 BD9851EFV Block diagram PVcc1 OUT1 DTC1 GND INV1 SCP VREF FB1 STB Vcc 20 – NON2 PGND PVcc2 OUT2 DTC2 SEL1 INV2 FB2 RT CT 7/16 Description of operations 1) Reference voltage block The reference voltage block generates a constant voltage with temperature compensated through inputting the power supplied from the Vcc pin. The output voltage is 2.5 V, with a ±1% accuracy. To cancel noises, insert a capacitor with a low ESR (several tens of mΩ) between the VREF and GND pins. It is recommended to use a ceramic capacitor of 1μF for this purpose. 2) Triangular wave oscillator block By connecting the resistor and capacitor of frequency settings to the RT and CT pins (only to RT pin on the BD9850FVM), a triangular wave will be generated and then input to the PWM comparators of Channels 1 and 2. 3) Error Amp block The Error Amp block detects the output voltage of the INV pin, amplifies an error with the set output voltage, and then outputs the error from the FB pin. The comparison voltage is 1 V, with a ±2% accuracy. (The Channel 2 of the BD9851EFV uses the NON pin input voltage as a reference.) Inserting a resistor and capacitor between the INV and FB pins will conduct phase compensation. 4) PWM comparator block The PWM comparator block converts the output voltage (FB voltage) into a PWM waveform and outputs it to the FET driver. (Only available on the BD9851EFV) Inputting a voltage, divided by resistance of the VREF pin in the DTC pin, will allow maximum ON duty setting. Inserting a capacitor between the CTL/SS and GND pins will allow the soft start function to control the rising output voltage. Inserting a capacitor between the DTC and GND pins will allow the soft start function to control the rising output voltage. Furthermore, the overshoot of output voltage at startup can be derated. Adding a Schottky diode between the FB and DTC pins will make it possible to suppress the overshoot rate (only available with step-down application). 5) FET driver block This block is a push-pull type driver enabling direct drive of external MOS FET. For the Channel 1, SEL1 pin setting will determine the application function. Set the SEL1 pin to step-down (P-ch drive) mode for short-circuiting Vcc or to step-up (N-ch drive) mode for short-circuiting GND. Furthermore, be sure to short-circuit the SEL1 pin to Vcc or GND pin. 6) Standby function (BD9850FVM) The CTL/SS pin allows for output ON/OFF control. Set the CTL/SS pin voltage to “H” to activate the output ON control. (BD9851EFV) The STB pin allows for output ON/OFF control. Set the STB pin voltage to “H” to activate the output ON control. The standby mode circuit current should be set to less than 5 μA. 7) Short circuit protection circuit (SCP) (Only available on BD9851EFV) The SCP is a timer-latch type short circuit protection circuit. If the output voltage of either channel drops below the set voltage, the Error Amp will be activated to increase the FB voltage and initiate charging the capacitor connected to the SCP pin with a 2 μA current. When the SCP pin voltage exceeds 1.5 V, the latch circuit will be activated to fix the output of both channels at OFF and, at the same time, the DTC pin at “L” level. In order to rest the latch circuit, set the STB pin to “L” level once, and then to “H” level. Or, turn ON the power supply again. Furthermore, if the short circuit protection circuit is not used, short-circuit the SCP pin to the GND pin. 8) Under Voltage Lock Out (UVLO) circuit The UVLO is a protection circuit to prevent the IC from malfunctioning when the power supply turns ON or if an instantaneous power interruption occurs. When the Vcc voltage falls below 3.8 V (or 3.7 V on the BD9851EFV), the output of both channels will be fixed at “OFF” and, at the same time, the DTC pin at “L” level. Hysteresis width of 0.1 V (or 0.11 V on the BD9851EFV) is provided for the detection voltage and release voltage of the UVLO in order to prevent malfunctions of the IC which may result from variations in the input voltage due to threshold online. Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this UVLO. 9) Thermal shutdown circuit (TSD) The TSD is a protection circuit to prevent the destruction of the IC due to abnormal heat generation. If the TSD detects an abnormal heat generation (175˚C) on the chip, the output of both channels will be fixed at “OFF” and, at the same time, the DTC pin at “L” level. Hysteresis width (15˚C) is provided for the superheat detection and release temperatures in order to prevent malfunctions of the IC which may result from variations in the input voltage due to threshold online. Furthermore, if the latch circuit is activated through the short circuit protection circuit, the circuit will be reset by this TSD. 8/16 Timing chart • In startup/normal operation (BD9850FVM) Soft start set voltage Oscillator output FB pin voltage Control threshold OUT pin waveform Vcc waveform Output voltage waveform Fig.15 BD9850FVM Timing chart (BD9851EFV) Vcc pin voltage waveform 3.8V 1.5V Output short circuit SCP pin voltage waveform FB CT DTC 2.3V OUT pin voltage waveform Output voltage waveform Fig.16 BD9851EFV Timing chart 9/16 Description of external components • Setting of output voltage (BD9850FVM) Setting of output voltage for the step-down application can be calculated by the formula below : Setting procedure Vo = Vthea × (R1 + R2) / R2 [V] (Vthea: Error Amp threshold voltage Typ. 1.0 [V]) Vo Application R1 INV (5) R2 Setting of output voltage (BD9851EFV) Setting procedure • Step-down (CH1), Step-up (CH1) Vo1 = Vthea × (R1 + R2) / R2 [V] (Vthea: Error Amp threshold voltage Typ. 1.0 [V]) Vo1 Application R1 INV1 (16) R2 • Step-down (CH2) Vo2 = VNON2 × (R1 + R2) / R2 [V] VNON2 = 2.5 × R4 / (R3 + R4) [V] However, set the NON2 pin voltage to 0.3 to 2.0 V. VREF (17) Vo2 R1 R2 R3 NON2 (4) R4 INV2 (5) • Inverting (CH2) Vo2 = 2.5 – {(2.5 - VINV2) X (R1 + R2) / R1} [V] VINV2 = 2.5 × R4 / (R3 + R4) [V] However, set the INV2 pin voltage to 0.3 to 2.0 V VREF (17) R3 INV2 (5) R1 R2 Vo2 R4 NON2 (4) Setting of oscillation frequency (BD9850FVM) Connecting a resistor to the RT pin (pin 2) allows for the setting of oscillation frequency. 10000 RT (2) Oscillating frequency [kHz] RRT 1000 Fig.17 Setting procedure for BD9850FVM oscillation frequency 100 1 10 100 1000 Timing resistance(RT) [kΩ] Fig.18 RT vs. Oscillation frequency 10/16 • Setting of oscillation frequency (BD9851EFV) Connecting a resistor to the RT pin (pin 2) and a capacitor to the CT pin allows for the setting of oscillation frequency. RRT RT (2) CT (3) CCT Fig. 19 Setting procedure for BD9851EFV oscillation frequency 1000 CCT=33pF 1000 Oscillating Frequency (kHz) 1000 CCT=220pF Oscillating Frequency (kHz) 1000 RRT=4.7kΩ CCT=1200pF 100 100 RRT=24kΩ 10 1 10 Timing Resistance (kΩ) 100 10 10 10 100 1000 Timing Capacitance(pF) Fig. 20 RT vs. Oscillation frequency Fig. 20 CT vs. Oscillation frequency • Setting of timer of short circuit protection circuit (BD9851EFV) Setting procedure TSCP = 7.45 × 105 × CSCP TSCP : Time from output short circuit to latch stop [sec] OSCP : Capacitance of capacitor between the SCP and GND pins [F] SCP (14) CSCP Application • Setting of maximum duty (BD9851EFV) Setting procedure DUTY(max.) = 100 × ( VDTC – Vth0) / (Vth100 – Vth0) VDTC = 2.5 × R2 / (R1 + R2) DUTY(max.) VDTC Vth0 Vth100 : : : : Maximum duty [%] DTC pin voltage [V] 0% duty threshold voltage [V] 100% duty threshold voltage [V] R1 DTC (13)(7) R2 Application VREF (17) • Pin treatment of unused channels (BD9851EFV) (18) Vcc (17) VREF (18) Vcc SEL1 (1) NON2 (4) INV (16) (5) FB (15) (6) DTC (13) (7) PVcc (12) (8) OUT (11) (9) Upper : Pin No. to be treated when the CH1 is not used Lower : Pin No. to be treated when the CH2 is not used Fig. 22 Pin treatment procedure for unused channel on BD9851EFV In order to use one channel, treat the pins of unused channel as shown above. 11/16 5 Application circuit / Directions for pattern layout (BD9850FVM) Vo Vcc Vcc RT R1 RT OUT C1 OUT CT/SS GND FB Vcc * R1 C1 * C2 1µF * Vcc OUT GND VREF RT CTL/SS FB INV ON/OFF OFF [ H ::ON ] L GND C1 VREF INV VREF C1: In order to reduce ripple noises, set the shortest distance between the VCC pin and the capacitor pin, and the GND pin and the capacitor pin. Furthermore, the OUT line may pass under the C1. C2: In order to reduce ripple noises, set the shortest pattern between the VREF pin and the capacitor pin, and the GND pin and the capacitor pin. R1: In order to stabilize the switching frequency, set the smallest pattern area so that PCB parasitic capacitance for the RT pin will be minimized. Fig.23 BD9850FVM Reference application 1 SEL1 2 RT 3 CT 4 NON2 5 INV2 6 FB2 7 DTC2 8 PVCC2 9 OUT2 Step-down GND 20 STB 19 VCC 18 VREF 17 INV1 16 FB1 15 SCP 14 DTC1 13 PVcc1 12 OUT1 11 Step-down 1 SEL1 GND 20 STB 19 Vcc 18 VREF 17 INV1 16 FB1 15 SCP 14 DTC1 13 PVcc1 12 OUT1 11 Step-up STB Vcc GND 2 RT 3 CT 4 NON2 5 INV2 6 FB2 7 DTC2 8 PVcc2 9 OUT2 STB Vcc GND Vo2 10 PGND Vo2 Vo1 Inverting 10 PGND VO1 Fig.24 Step-down/Step-up application Equivalent circuit (BD9850FVM) 2PIN(OUT) Vcc 1.67k 50k 250k Fig.25 Step-up/Inverting application 4PIN(VREF) Vcc 5PIN(INV) Vcc OUT VREF INV 200k 193k GND GND GND 6PIN(FB) Vcc 7PIN(CTL/SS) Vcc 20k 5k 8PIN( R T ) VREF 100k FB 20p CTL/SS 500k RT 1k 200k GND GND GND Fig.26 Equivalent circuit (BD9850FVM) 12/16 BD9851EFV 1PIN (SEL1) Vcc Vcc 2PIN (RT) Vcc VREF VREF 7,13PIN (DTC2,DTC1) Vcc Vcc SEL1 RT DTC 9PIN (OUT2) Vcc Vcc PVcc2 3PIN (CT) VREF VCC VREF VREF VREF VREF VREF 4PIN (NON2) VREF Vcc Vcc OUT2 CT NON2 PGND 11PIN (OUT1 ) Vcc Vcc PVcc1 14PIN (SCP) VREF Vcc VREF Vcc 5,16PIN (INV2,INV1) VREF Vcc Vcc OUT1 SCP INV 6,15PIN (FB2,FB1) VREF Vcc VREF VREF Vcc 17PIN (VREF) Vcc Vcc 19PIN (STB) Vcc STB FB VREF Fig.27 Equivalent circuit (BD9851EFV) Cautions on use 1) Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2) GND potential Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals should be lower than the GND potential voltage including an electric transients. 3) Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other circuitís power lines. 5) Operation in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 6) Thermal shutdown circuit (TSD circuit) The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. 7) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or removing it from a jig or fixture, during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting and storing the IC. 13/16 8) IC pin input This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. Pin junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the Pin junction operates as a parasitic diode. When Pin B > GND > Pin A, the PñN junction operates as a parasitic transistor. Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Resistor (Pin A) (Pin B) C Transistor (NPN) B E GND N P+ N N N N P P+ P+ N N P P+ Player Parasitic element GND Parasitic element GND Player (Pin B) (Pin A) B Parasitic element E GND Other proximity element Parasitic element C GND Fig. 28 Typical simple construction of monolithic IC 9) Common impedance The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage line may damage the device. on the power ground 10) On the application shown below, Vcc is short-circuited to the Ground with external diode charged, internal circuits may be damaged. recommended to insert a backflow prevention diode in series with the Vcc or a bypass diode between each pin and Vcc. Bypass diode Backflow prevention diode Vcc Output pin Fig. 29 14/16 11) Although ROHM is confident that the example application circuit reflects the best possible recommendations, be sure to verify circuit characteristics for your particular application. Modification of constants for other externally connected circuits may cause variations in both static and transient characteristics for external components as well as this Rohm IC. Allow for sufficient margins when determining circuit constants. Oscillation frequency setting resistor 12) For the oscillation frequency setting resistor to be inserted between the RT pin and the GND pin, mount this resistor close to the RT pin and provide the shortest pattern routing. Thermal derating characteristics PD(W) 0.8 MSOP 8 PD(W) 5 HTSSOP-B20 POWER DISSIPATION : Pd [W] POWER DISSIPATION : Pd [W] 0.6 (2) 0.59 W 4 (4) 3.20W 3 (3) 2.30W 2 (2) 1.45W 1 (1) 1.00W (1) 0.30 W 0.4 Wiring width 0.4mm Pd = 0.50 W qjc = 200˚C/W 0.2 0 0 25 50 75 100 125 150 0 0 25 50 75 100 125 150 AMBIENT TEMPERATURE : Ta [˚C] (1) : Single piece of IC (2) : With ROHM standard PCB mounted (Glass epoxy PCB of 70mm X70mm X1.6mm) AMBIENT TEMPERATURE : Ta [˚C] (1) : Single piece of IC PCB size: 70mm X70mm X1.6 mm2 (PCB incorporates thermal via) Copper foil area on the reverse side of PCB: 10.5 X10.5mm2 (2) : 2-layer PCB (Copper foil area on the reverse side of PCB: 15mm X15mm (3) : 2-layer PCB (Copper foil area on the reverse side of PCB: 70mm X70mm (4) : 4-layer PCB (Copper foil area on the reverse side of PCB: 70mm X70mm Fig.30 Fig.31 Selection of order type B D 9 8 5 0 F V M T R ROHM model name Product No. 9850=10V 9851=20V Package type FVM=MSOP8 EFV=HTSSOP-B20 Taping type TR=Reel-type embossed carrier tape (MSOP8) E2=Reel-type embossed carrier tape (HTSSOP-B20) MSOP8 Package style Quantity 2.9 ± 0.1 8 5 Embossed carrier tape 3000 pieces /reel TR (When holding a reel in left hand and pulling out the tape with right hand, No. 1 pin appears in the upper right of the reel.) 0.29 ± 0.15 0.6 ± 0.2 4.0 ± 0.2 2.8 ± 0.1 Packaging direction +0.05 –0.03 1 4 0.475 0.9max. 0.75 ± 0.05 0.08 ± 0.05 0.22 0.65 +0.05 –0.04 0.145 0.08 M 0.08 S No. 1 pin Pulling-out side (unit : mm) HTSSOP-B20 Reel Package style Quantity 6.5 ± 0.1 20 11 Embossed carrier tape (Moisture-proof specificatin) 2500 pieces /reel E2 (When holding a reel in left hand and pulling out the tape with right hand, No. 1 pin appears in the upper left of the reel.) 0.325 1.0max. 0.85 ± 0.05 0.08 ± 0.05 1 10 0.17 S 0.08 S 0.65 0.2 +0.05 +0.04 0.5 ± 0.15 1.0 ± 0.2 6.4 ± 0.2 4.4 ± 0.1 Packaging direction +0.05 +0.03 12.34 12.34 12.34 No. 1 pin 12.34 12.34 12.34 (unit : mm) Pulling-out side 12.34 12.34 Reel 15/16 Catalog No.08T679A '08.9 ROHM © Appendix Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright © 2009 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster @ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix-Rev4.0