BD9997FVT

1/4 Structure Product Name Model Name Function Silicon monolithic integrated circuits Boost DC/DC converter LSI for Blu-ray BD9997FVT (1) (2) (3) (4) (5) The output voltage can be set by external resistance. Internal Power MOS transistor with Backgate Control function Inrush current reduction Integrated Soft start Built-in Protection function NMOS overcurrent limit, overvoltage mute, thermal shutdown, output ground short protection UVLO operation at low power-supply voltage Easy assembly small sized package TSSOP-B8 Built-in Discharge function function of output interception(at shutdown, at overvoltage) (6) (7) (8) (9) ○Absolute maximum ratings (Ta=25℃) Item Supply voltage Power dissipation （※1） Operating temperature range Storage temperature range Input voltage range on SW Input voltage range on VOUT Input voltage range on FB AMPOUT terminal maximum input voltage XSHDN terminal maximum input voltage Junction temperature Symbol Vcc Pd Topt Tstg VINSW VINOUT VINFB VINAMPOUT VINSHDN Tjmax Limit -0.3～7 0.625 -25～+85 -55～+150 -0.3～15 -0.3～15 -0.3～VCC+ 0.3 -0.3～VCC+ 0.3 -0.3～VCC+ 0.3 +150 Unit V W ℃ ℃ V V V V V ℃ （※1） While mounted on Glass-expoxy board（ROHM standard board：70×70×1.6[mm3]） ○Operating conditions (Ta＝25℃) Item Supply voltage Output current1 （※2）（※5） Output current2 （※3）（※5） Output current3 （※4）（※5） （※2） VIN=4.5[V] → VOUT=7.5[V] (L=22[uH]) Symbol Vcc Iout1 Iout2 Iout3 Min. 4.5 - Typ. 5.0 - Max. 5.5 0.15 0.10 0.20 Unit V A A A （※3） VIN=4.5[V] → VOUT=11.0[V] (L=22［uH］) （※4） VIN=4.5[V] → VOUT=8.1[V] (L=10［uH］) （※5） Do not, however exceed Pd. REV. B 2/4 ○Electric Characteristics （Unless otherwise specified, Vcc=5.0[V], VOUT=5.0[V], Ta=25[℃]） Limit Min. 4.0 2.3 － Vcc 3.5 0.582 400 65 2.00 － 0.36 0.30 3.35 3.45 0.92 7.0 Typ. 6.3 3.7 1 － 6.0 0.600 650 80 2.30 0.03 0.60 0.50 3.55 3.65 1.53 10.0 Max. 9.5 5.2 10 12.0 8.5 0.618 900 90 2.60 0.20 0.84 0.70 3.75 3.85 2.14 13.0 Parameter Current consumption Current consumption Current consumption (Shutdown mode) Output voltage range Soft start beginning time ERRVREF voltage Oscillator frequency Maximum duty cycle AMPOUT maximum output voltage AMPOUT minimum output voltage PMOS ON resistance NMOS ON resistance UVLO detection voltage UVLO return voltage XSHDN Input threshold voltage XSHDN pull down resister Symbol ICC1 ICC2 ICC3 VOUTR TSOFT ERRVREF SAWO DMAX VAMPOUTH VAMPOUTL RONP RONN VUVLO1 VUVLO2 VthXSHDN RXSHDN Unit mA mA μA V ms V kHz % V V Ω Ω V V V kΩ Condition VCC=5.0[V], FB=2.5[V], No load VCC=5.0[V], FB=0[V], No load VCC=5.0[V], XSHDN=GND or Open VCC=5.0[V], FB=0[V] VOUT=9.0[V] VOUT=9.0[V] VCC Falling VCC Rising REV. B 3/4 ○Package outline 3.0±0.1 Max 3.35 (include. BURR) 8 7 6 5 4°±4° 9997 6.4±0.2 4.4±0.1 1 0.525 2 3 4 +0.05 1Pin MARK 0.145 -0.03 1.0±0.05 1.2MAX LOT NO. 0.1±0.05 0.08 0.65 0.245 -0.04 +0.05 0.08 (UNIT: mm) ○Block Diagram ○Terminal No./Terminal name Terminal No 1 2 3 4 5 6 7 8 Terminal name VOUT FB AMPOUT GND XSHDN VCC PGND SW VOUT SW 1 BACKGATE CONTROL FB OUTPUT CONTROL CURRENT LIMIT 8 PGND 2 7 AMPOUT VCC DTC 3 ERRVREF 6 GND XSHDN SOFT START 4 5 SAW REV. B 0.5±0.15 1.0±1.2 4/4 ○Operation Notes 1．About grand potential Set PGND and GND to equal potential.The ground line is where the lowest potential and transient voltages are connected to the IC. 2．About starting Keep light Load at VOUT output while start-up. 3．About board pattern Use separates ground lines for small control signals and high current outputs. Because these high current outputs that flows to the wire impedance changes the GND voltage for control signal. Therefore each ground of IC must be connected at one point on the set circuit board. As for GND of external parts, it’s similar to the above-mentioned. The characteristics of DC/DC converter might influenced by surrounding components and board pattern. Consider the effects from surroundings while design. Make VCC,PGND and GND impedance sufficiently low Solder RESERVE to GND on set circuit board. 4．About peripheral circuit Bypass capacitor between power supply and ground should be use low ESR ceramic capacitor and placed close to the IC pin as possible. External components such as L and C is necessary to be placed as near to the IC as possible with shortest distance. Monitor the output voltage at both end of capacitor connected to VOUT.PMOS over current limit must not be built into, and the over current must not flow to PMOS. please have safe countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing. 5．About absolute maximum rating Exceeding supply voltage and operating Temp. over Absolute Maximum Ratings may cause degradation of IC and even may destroy the IC. If special mode such that exceeding Absolute Maximum Ratings is expected, please have safe countermeasure such as adding POLY SWITCH and fuse to avoid from over stressing. 6．About heat design Do not exceed the power dissipation (PD) of the package specification rating under actual operation. 7．About Short between terminals and the mis-installation While mounting IC on the board, check direction and position of the IC. If inadequately mounted, the IC may destroy. Moreover this IC might be destroyed when dust short the terminals between pins or pin and ground. 8．About operation in strong electromagnetic field Strong electromagnetic radiation can cause operation failures. 9．About heat interception circuit (TSD) The TSD is activated when the junction temperature (Tj) reaches 175℃ and the output terminal is switched to Hi-Z. The TSD circuit aims to intercept IC from high temperature. The guarantee and protection of IC are not purpose. Therefore, please do not use this IC after TSD circuit operates, nor use it for assumption that operates the TSD circuit. 10．About inspection by set substrate The stress might hang to IC by connecting the capacitor to the terminal with low impedance. Then, please discharge electricity in each and all process. Moreover, in the inspection process, please turn off the power before mounting the IC, and turn on after mounting the IC. In addition, please take into consideration the countermeasures for electrostatic damage, such as giving the earth in assembly process, transportation or preservation. 11．About each input terminal This IC is a monolithic IC, and has P+ isolation and P substrate for the element separation. Therefore, a parasitic PN junction is firmed in this P-layer and N-layer of each element. When the GND voltage potential is greater than the voltage potential at Terminals A or B, the PN junction operates as a parasitic diode. In addition, the parasitic NPN transistor is formed in said parasitic diode and the N layer of surrounding elements close to said parasitic diode. These parasitic elements are formed in the IC because of the voltage relation. The parasitic element operating causes the wrong operation and destruction. Therefore, please be careful so as not to operate the parasitic elements by impressing to input terminals lower voltage than GND (P substrate). Please do not apply the voltage to the input terminal when the power –supply voltage is not impressed. Moreover, please impress each input terminal lower than the power-supply voltage or equal to the specified range in the guaranteed voltage when the power-supply voltage is impressing.. REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 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