BH6948GU

1/4 ● Structure ● Product ● Type ● Figure 1. 2. 3. 4. 5. 6. Silicon Monolithic Integrated Circuit 7 x 7 Matrix LED DRIVER for Mobile Phone BH6948GU Highly effective Charge Pump circuit that can be switched 1 time, 1.5 times, and 2 times pressure automatically. (190mA / MAX) 7-channel LED DRIVER that can contorol PWM (IoMAX = 31mA/ch, Current step = 1mA) 7-channel PMOS-SW controlled with 1/8TDMA It is possible to make 49(7X7) LED shine by PMOS-SW and the LED driver SPI Interface Wafer Level CSP pacage for space constrained applications 62pin (4.1mm×4.1 mm height = 1.0mm-max) ● Absolute Maximum Ratings (Ta = 25℃) Parameter Maximum Supply Voltage Power Dissipation ※ Operating Temperature Range Storage Temperature Range ※ Symbol VMAX Pd Topr Tstg Rating 5.5 1.47 -30～+85 -55～+125 Unit V W ℃ ℃ When using more than at Ta=25℃, it is reduced 14.7mW per 1℃. When RHOM specification board 50mm X 58mm mounting. Cautions : A device may be destroyed when it is used on the conditions beyond this value. Moreover, the usual operation is not guaranteed. ● Operating Conditions Parameter VBAT1 Voltage ※1 VBATCP Voltage ※1 DVDD1 Voltage ※2 DVDD2 Voltage ※2 ※1 49LED lighting ※2 DVDD1 ≦ DVDD2 ◎This product is not especially designed to be protected from radioactivity. Status of this document. The Japanese version of this document is the formal specification. A customer may use this translation version only for reference to help reading the formal version. If there are any differences in translation version of this document, formal version takes priority. Symbol VBAT1 VBATCP VDVDD1 VDVDD2 Range 3.15～4.5 1.7～3.1 2.7～3.1 Unit V V V V Block VREF/BGR DCDC I/O Logic REV. B 2/4 ● Electrical Characteristics (Unless otherwise specified, Ta=25℃,VBAT1=VBATCP=VBATCP1-3=3.6V,DVDD1=1.8V,DVDD2=2.85V) Parameter Stand-by Circuit Current Circuit Current DC-DC Converter Current1 DC-DC Converter Current2 DC-DC Converter Current3 CPOUT Voltage1 CPOUT Output Current1 CPOUT Voltage2 CPOUT Output Current2 DCDC Converter CPOUT Voltage3 CPOUT Output Current3 CPOUT Voltage4 CPOUT Output Current4 Oscillator Frequency PMOS Switch Leak Current when OFF (SW1～7 total) Output Current1 Output Current2、3 Current Driver (Lo-Mode, LED1~7) Output Current4～31 Output Current matching1 Output Current matching2 Leak Current when OFF (SW1～7 total) Current Driver (RGB with PWM ：LED1~7) Under Voltage Lockout Soft-Start Short Circuit Protector Over Current Protector Over Voltage Protector LED Dropout Detector PWM on duty1 PWM on duty2 PWM on duty3 UVLO Threshold UVLO Hysteresis SS Mode Time SCP Threshold Delay Time Reset Time OCP Threshold OVP Threshold Detect Voltage Input “H” Level SPI I/F Input “L” Level “H” Level Input Current “L” Level Input Current Input ”H” Level RSTB Input “L” Level ”H” Level Input Current “L” Level Input Current Symbol IST IQCP1 IQCP2 IQCP3 VCP1 ICP1 VCP2 ICP2 VCP3 ICP3 VCP4 ICP4 fosc ILEAKP IO１ IO2 IO4 Mat1 Mat2 ILEAK PWMD1 PWMD2 PWMD3 VUVLO VUVLO TSS VSCP TDLY TRST IOCP Vovp VDR VIH VIL IIH IIH VIH VIL IIH IIL MIN 4.55 4.55 5.1 5.1 0.96 -8.5 -8.0 -7.0 1.54 43.7 84.6 2.0 50 1.6 1.0 8 80 5.50 0.36 1.4 -0.3 1.4 -0.3 - Spec TYP 0 0.93 6.4 4.8 4.75 4.75 5.3 5.3 1.20 5.04 47.2 88.1 2.25 100 2.0 1.2 10 100 790 5.62 0.40 0 0 0 0 MAX 8.8 1.4 9.6 7.2 4.95 190 4.95 190 5.5 190 5.5 190 1.44 7.0 +8.5 +8.0 +7.0 11.5 10 7.0 8.54 40.7 91.6 2.6 150 2.4 1.4 12 120 5.74 0.44 DVDD1 +0.3 0.4 1 1 DVDD1 +0.3 0.4 1 1 Units uA mA mA mA V mA V mA V mA V mA MHz μA % % % % % uA % % % V mV ms V mS mS mA V V V V uA uA V V uA uA Condition Stand-by mode (RSTB=”H”) 1times mode 1.5times mode (CPOUT=4.75V) 2times mode (CPOUT=4.75V) 1.5times mode No Load 1.5times mode, VCPOUT>4V 49 LED lighting 2.0times mode No Load 2.0times mode, VCPOUT>4V 49 LED lighting 1.5times mode No Load 1.5times mode, VCPOUT>4V 49 LED lighting 2.0times mode No Load 2.0times mode, VCPOUT>4V 49 LED lighting When 35H(MATRIXCNT)bit0(START)=0 I=1mA Setting I=2～3mA Setting I=4～31mA Setting I=1～3mA Setting, Mat1=(IoMax-IoMin)/IoMinx100 I=4～31mA Setting Mat2=(IoMax-IoMin)/IoMinx100 When 35H(MATRIXCNT)bit0(START)=0 PWM1～7SET=5digit PWM1～7SET=32digit PWM1～7SET=58digit VBAT falling CPOUT falling REV. B 3/4 ● Block Diagram VBAT VBATCP VBATCP1 VBATCP2 VBATCP3 C1P C2M C1M C2P VBAT D2 ● GNDCP CPIN2 Terminal List CPIN1 F8 F1 E2 F2 G1 H6 H7 H4 H5 H2 G8 VBAT1 FBGA62R1 FBGA62R1 BALL Name BALL No. TEST1 H3 G3 FUNCTION Test terminal 1 (※ Please be sure connect to GND) Power supply for SW1～7 P-MOS SW3 output P-MOS SW1 output P-MOS SW7 output LED1 driver output GND for LED1～3 Test terminal 2 (※ Please be sure connect to GND) P-MOS SW5 output P-MOS SW4 output Power supply for SW1～7 P-MOS SW2 output LED7 driver output LED6 driver output LED2 driver output LED3 driver output GND for VREF, IREF P-MOS SW6 output LED Constant Current Driver Current setting Terminal Test terminal 3 (※ Please be sure connect to GND) GND for LED4～7 LED5 driver output LED4 driver output Stabilization Power Supply for IREF, VSATDET, OSC Power supply for BGR, VREF, SCP Standard for OSC, VSATDET, IREF Reset terminal GND terminal 4 line serial interface CLK 4 line serial interfac DATAIN GND for internal logic Device version Power supply for charge pump GND terminal GND terminal 4 line serial interface CE 4 line serial interface DATAOUT Power supply for interface Power supply for internal logic Power Supply for Charge Pump Section Power Supply for Charge Pump Section TEST terminal 4 (※ Please be sure connect to GND) Test output terminal (※ Please should be left open when used) GND terminal GND terminal Power Supply for Charge Pump section Power Supply for Charge Pump section Step-up Voltage Circuit TEST terminal 5 (※ Please be sure to connect to VBAT) Charge Pump section Constant Voltage Output GND terminal GND terminal GND terminal GND terminal GND for Charge pump section GND terminal Charge Pump section Flying Capacitor2 on Side of Plus Charge Pump section Constant Voltage Output Charge Pump section Flying Capacitor1 on Side of Plus Charge Pump section Flying Capacitor2 on Side of Minus Power Supply for Charge Pump section Step-up Voltage Circuit Charge Pump section Flying Capacitor1 on Side of Minus GND terminal CPOUT 1 A1 A2 A3 A4 A5 A6 A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2 C4 C5 C6 C7 C8 D1 D2 D3 D4 D5 D6 D7 D8 E1 E2 E3 E4 E5 E6 E7 E8 F1 F2 F3 F4 F6 F7 F8 G1 G2 G3 G4 G5 G6 G7 G8 H1 H2 H3 H4 H5 H6 H7 H8 Charge pump x1, x1.5, x2 CPOUT 2 CPOUTSW SW3 VREF12 D3 D1 BGR / VREF VREF OSC CPOUTSW CPOUTSW1 T06 A2 B3 SW1 SW7 LED1 GNDLE2 IREF C4 C1 SW7 SW 6 SW5 SW4 SW3 SW2 SW1 A5 C2 IREF T05 T04 Logic TDMA T03 T02 T01 T00 TEST2 B1 GNDA D5,E3,E4, F6,F7,G4, GND G5,G6,G7, H1,H8 SW5 B2 SW4 A3 B4 A4 DVDD1 E7 CPOUTSW １ SW2 LED7 LED6 LED2 LED3 GNDA SW6 IREF TEST3 GNDLE3 LED5 RSTB D4 CE E5 CLK D6 DI D7 DO E6 SPI/IF TDMA PWM SLOPE 31mA /ch 1 mA step TDMA TDMA TDMA GNDLE 2 A7 LED7 LED6 B5 B6 LED5 LED4 LED3 C7 C8 B8 B7 A6 DGND D8 TDMA TDMA TDMA DVER LED2 LED1 E1 TDMA PWM DVDD2 E8 G2 A1 A8 C5 F3 TEST1 TEST2 TEST3 TEST4 TEST5 VBAT F4 GNDLE3 C6 LED4 VREF TEST0 VBAT1 VREF12 ● Package Outline RSTB GND CLK DI DGND BH6948 DVER VBATCP2 GND GND Lot No. CE DO DVDD1 DVDD2 VBATCP１ VBATCP3 TEST4 TESTO GND GND VBATCP CPIN1 TEST5 CPOUT2 GND GND GND GND GNDCP GND C2P CPOUT1 C1P C2M CPIN2 C1M REV. B GND 4/4 ● Use-related Cautions (1) Absolute maximum ratings If applied voltage (VMAX), operating temperature range (Topr), or other absolute maximum ratings are exceeded, there is a risk of damage. Since it is not possible to identify short, open, or other damage modes, if special modes in which absolute maximum ratings are exceeded are assumed, consider applying fuses or other physical safety measures. (2) Power supply lines In the design of the board pattern, make power supply and GND line wiring low impedance. When doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns. Similarly take pattern design into account for GND lines as well. When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND pattern and small signal GND pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the pattern wiring and large currents do not cause the small signal GND voltage to change. Take care that the GND wiring pattern of externally attached components also does not change. Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND pins, when using electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for various characteristics of the capacitors used. (3) GND voltage Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm that there are no pins for which the potential becomes less than a GND by actually including transition phenomena. (4) Shorts between pins and misinstallation When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is installed erroneously, there is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a power supply or GND. (5) Operation in strong magnetic fields Be careful when using the LSI in a strong magnetic field, since it may malfunction. (6) Input pins Parasitic elements inevitably are formed on an LSI structure due to potential relationships. Because parasitic elements operate, they give rise to interference with circuit operation and may be the cause of malfunctions as well as damage. Accordingly, take care not to apply a lower voltage than GND to an input pin or use the LSI in other ways such that parasitic elements operate. Moreover, do not apply a voltage to an input pin when the power supply voltage is not being applied to the LSI. Furthermore, when the power supply voltage is being applied, make each input pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics. (7) Externally attached capacitors When using ceramic capacitors for externally attached capacitors, determine constants upon taking into account a lowering of the rated capacitance due to DC bias and capacitance change due to factors such as temperature. (8) Thermal shutdown circuit (TSD) When the junction temperature becomes higher, the thermal shutdown circuit operates and turns the switch OFF. The thermal shutdown circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI. Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation. (9) Thermal design Perform thermal design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use. （10）Test terminal and unused terminal processing Please process a test terminal and unused terminal according to explanations of the function manual and the application note, etc. to be unquestionable while real used. Moreover, please inquire of the person in charge of our company about the terminal without the explanation especially. （11）Rush current For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wring, width of GND wiring, and routing of wiring. REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. 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