BR24C16F

Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV I2C BUS compatible serial EEPROM BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16 / BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV / The BR24C08, BR24C16 and BR24E16 series are 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗I2C BUS is a registered trademark of Philips. Features 1) 1k x 8 bits serial EEPROM. (BR24C08 / F / FJ / FV) 2k x 8 bits serial EEPROM. (BR24C16 / F / FJ / FV, BR24E16 / F / FJ / FV) 2) Two wire serial interface. (2Byte Address : BR24E16) 3) Operating voltage range : 2.7V∼5.5V 4) Low current consumption Active (at 5V) : 2.0mA (Typ.) Standby (at 5V) : 1.0µA (Typ.) 5) Auto erase and auto complete functions can be used during write operations. 6) Page write function : 16byte 7) DATA security Write protect feature Inhibit to WRITE at low Vcc 8) Noise filters at SCL and SDA pins. 9) Address can be incremented automatically during read operations. 10) Compact packages. 11) Rewriting possible up to 100,000 times. 12) Data can be stored for ten years without corruption. Absolute maximum ratings (Ta=25°C) Parameter Supply voltage Symbol VCC Limits −0.3~+6.5 300(SSOP−B8) Power dissipation Pd ∗1 Unit V 450(SOP8, SOP−J8) ∗2 800(DIP8) ∗3 mW Storage temperature range Operating temperature range Terminal voltage Tstg Topr − −65~+125 −40~+85 −0.3~VCC+0.3 °C °C V ∗1 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. Recommended operating conditions (Ta=25°C) Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7~5.5 0~VCC Unit V V Memory Ics Block diagram BR24C08 / F / FJ / FV A0 1 10bits BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV 8kbits EEPROM ARRAY 8bits 8 VCC Pin name VCC GND I/O − − − I I I/O I Power supply Ground (0V) Function A1 2 ADDRESS DECODER 10bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER 7 WP A0, A1 A2 Out of use. Please connect to GND. Slave address set Serial clock input Slave and word address, serial data input, serial data output Wite protect pin ∗ START STOP A2 3 CONTROL LOGIC ACK 6 SCL SCL SDA GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA WP ∗An open drain output requires a pull-up resistor. BR24C16 / F / FJ / FV A0 1 11bits 16kbits EEPROM ARRAY 8bits 8 VCC Pin name VCC I/O − − I I I/O I Power supply Ground (0V) Function A1 2 ADDRESS DECODER 11bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER 7 WP GND A0, A1, A2 SCL Out of use. Please connect to GND. Serial clock input Slave and word address, serial data input, serial data output Wite protect pin ∗ START STOP A2 3 CONTROL LOGIC ACK 6 SCL SDA WP GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA ∗An open drain output requires a pull-up resistor. BR24E16 / F / FJ / FV A0 1 11bits 16kbits EEPROM ARRAY 8bits 8 VCC Pin name 7 WP I/O − − I I I/O I Power supply Ground (0V) Function A1 2 ADDRESS DECODER 11bits SLAVE · WORD ADDRESS REGISTER DATA REGISTER VCC GND START STOP A0, A1, A2 6 ACK Slave address set Serial clock input Slave and word address, serial data input, serial data output Wite protect pin ∗ A2 3 CONTROL LOGIC SCL SCL SDA GND 4 HIGH VOLTAGE GEN. VCC LEVEL DETECT 5 SDA WP ∗An open drain output requires a pull-up resistor. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV Electrical characteristics DC characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Parameter "HIGH" input voltage "LOW" input voltage "LOW" output voltage Input leakage current Output leakage current operating current Standby current Symbol VIH VIL VOL ILI ILO ICC ISB Min. 0.7VCC − − −1 −1 − − Typ. − − − − − − − Max. − 0.3VCC 0.4 1 1 3.0 3.0 Unit V V V µA µA mA µA IOL=3.0mA(SDA) VIN=0V~VCC VOUT=0V~VCC VCC=5.5V, fSCL=400kHz VCC=5.5V, SDA SCL=VCC A0, A1, A2=GND, WP=GND Conditions − − This product is not designed for protection against radioactive rays. Operating timing characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Parameter SCL frequency Dataclock "HIGH" time Dataclock "LOW" time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus open time before start or transfer Internal write cycle time Noise erase valid time (SDA/SCL pins) Symbol fSCL tHIGH tLOW tR tF tHD : STA tSU : STA tHD : DAT tSU : DAT tPD tDH tSU : STO tBUF tWR tI Vcc=5V±10% Min. − 0.6 1.2 − − 0.6 0.6 0 100 0.1 0.1 0.6 1.2 − − Typ. − − − − − − − − − − − − − − − Max. 400 − − 0.3 0.3 − − − − 0.9 − − − 10 0.05 − 4.0 4.7 − − 4.0 4.7 0 250 0.2 0.2 4.7 4.7 − − Vcc=3V±10% Min. Typ. − − − − − − − − − − − − − − − Max. 100 − − 1.0 0.3 − − − − 3.5 − − − 10 0.1 Unit kHz µs µs µs µs µs µs ns ns µs µs µs µs ms µs Memory Ics Timing charts BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV tR SCL tHD SDA (IN) tBUF SDA (OUT) tF tHIGH : STA tSU : DAT tLOW tHD : DAT tPD tDH SCL tSU SDA : STA tHD : STA tSU : STO START BIT STOP BIT Data is read on the rising edge of SCL. Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing SCL SDA D0 Write data (n) ACK tWR STOP CONDITION START CONDITION Fig.2 Write cycle timing Circuit operation (1) Start condition (recognition of start bit) Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be executed unless this condition is satisfied. (See Fig.1 for the synchronized data input / output timing.) (2) Stop condition (recognition of stop bit) To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed. (See Fig.1 for the synchronized data input / output timing.) (3) Precautions concerning write commands In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (4) Device addressing BR24C08 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 1bit of the slave address (A2 … device address) are used to select the device. This IC can address up to two devices on the same bus. 4) The next 2bits (P1, P0 … page select) are used by the master to select four 256 word page of memory. P1, P0 set to ‘0’ ‘0’ $ $ $ $ $ $ $ 1 page (000 ~0FF) P1, P0 set to ‘0’ ‘1’ $ $ $ $ $ $ $ 2 page (100 ~1FF) P1, P0 set to ‘1’ ‘0’ $ $ $ $ $ $ $ 3 page (200 ~2FF) P1, P0 set to ‘1’ ‘1’ $ $ $ $ $ $ $ 4 page (300 ~3FF) 5) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 P1 P0 R/W BR24C16 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 3bits (P2, P1, P0 … page select) are used by the master to select four 256 word page of memory. P2, P1, P0 set to ‘0’ ‘0’ ‘0’$ $ $ $ $ $ $ 1 page (000 ~0FF) P2, P1, P0 set to ‘0’ ‘0’ ‘1’$ $ $ $ $ $ $ 2 page (100 ~1FF) : : P2, P1, P0 set to ‘1’ ‘1’ ‘1’$ $ $ $ $ $ $ 8 page (700 ~7FF) 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 P2 P1 P0 R/W BR24E16 / F / FJ / FV 1) Make sure the slave address is output from the master in continuation with the start condition. 2) The upper 4bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 3bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC can address up to eight devices on the same bus. 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 A1 A0 R/W Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (5) Write protect (WP) When WP pin set to VCC (High level), write protect is set by all address. When WP pin set to GND (Low level), enable to write to all address. Either control this pin or connect to GND (or VCC). It is inhibited from being left unconnected. (6) ACK signal The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output (µ-COM when a write or read command of the slave address input ; this IC when reading data). For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address input, µ-COM when a read command data output). The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8 bits). When data is being write to the ICs, a LOW acknowledge signal (ACK signal) is output after the receipt of each 8 bits of data (word address and write data). When data is being read from the IC, 8bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Fig.3 for acknowledge signal (ACK signal) response.) Start condition (start bit) SCL (from µ-COM) SDA (µ−COM output data) SDA (IC output data) Acknowledge signal (ACK signal) 1 8 9 Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (7) Byte write BR24C08 / F / FJ / FV S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 A2 P1 P0 WA 7 WA 0 D7 D0 RA /C WK WP A C K A C K Fig.4 BR24C16 / F / FJ / FV S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 P2 P1 P0 WA 7 WA 0 D7 D0 RA /C WK WP A C K A C K Fig.5 BR24E16 / F / FJ / FV S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS 1st WORD ADDRESS ∗∗∗∗∗ WA 10 2nd WORD ADDRESS WA 0 DATA 1 0 1 0 A2 A1 A0 D7 D0 RA /C WK A C K A C K A C K WP Fig.6 $ Data is written to the address designated by the word address (n address). $ After 8 bits of data are input, the data is written to the memory cell by issuing the stop bit. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (8) Page write BR24C08 / F / FJ / FV S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS WORD ADDRESS DATA 1 0 1 0 P2 P1 P0 WA 7 WA 0 D7 D0 RA /C WK WP A C K A C K Fig.7 BR24C16 / F / FJ / FV S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 DATA(n) DATA(n+15) S T O P 1 0 1 0 P2 P1 P0 D7 D0 D0 RA /C WK A C K A C K A C K WP Fig.8 BR24E16 / F / FJ / FV S T A R T SDA LINE W R I T E S T O P SLAVE ADDRESS 1st WORD ADDRESS(n) ∗∗∗∗∗ WA 10 2nd WORD ADDRESS(n) WA 0 DATA(n) DATA(n+15) 1 0 1 0 A2 A1 A0 D7 D0 D0 RA /C WK A C K A C K A C K A C K WP Fig.9 $ A 16 byte write is possible using this command. $ The page write command arbitrarily sets the upper 4 bits (WA7 to WA4) of the word address. The lower 4 bits (WA3 and WA0) can write up to 16 bytes of data with the address being incremented internally. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (9) Current read BR24C08 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 A2 P1 P0 D7 D0 RA /C WK Fig.10 A C K BR24C16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 P2 P1 P0 D7 D0 RA /C WK Fig.11 A C K BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA S T O P 1 0 1 0 A2 A1 A0 D7 D0 RA /C WK Fig.12 A C K $ In case the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the next word address (n+1). If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current read outputs the data of the word address (n). If the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides s single byte of data. At this point, this IC discontinues transmission. $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) $ This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (10) Random read BR24C08 / F / FJ / FV S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 S T A R T SLAVE ADDRESS R E A D DATA(n) S T O P 1 0 1 0 A2 P1 P0 1 0 1 0 A2 P1P0 D7 D0 RA /C WK A C K Fig.13 RA /C WK A C K BR24C16 / F / FJ / FV S T A R T SDA LINE W R I T E WA 7 SLAVE ADDRESS WORD ADDRESS(n) WA 0 S T A R T SLAVE ADDRESS R E A D DATA(n) S T O P 1 0 1 0 P2 P1 P0 1 0 1 0 P2 P1P0 D7 D0 RA /C WK A C K Fig.14 RA /C WK A C K BR24E16 / F / FJ / FV S T A R T SDA LINE W R I T E S T A R T WA 0 SLAVE ADDRESS 1st WORD ADDRESS(n) ∗∗∗∗∗ WA 10 2nd WORD ADDRESS(n) SLAVE ADDRESS R E A D DATA(n) S T O P 1 0 1 0 A2 A1 A0 1 0 1 0 A2 A1A0 D7 D0 RA /C WK A C K Fig.15 A C K RA /C WK A C K $ This command can read the designated word address data. $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled] (See Fig.16 to 18 for the sequential read cycles.) $ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV (11) Sequential read BR24C08 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 A2 P1 P0 D7 D0 D7 D0 RA /C WK A C K Fig.16 A C K A C K BR24C16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 P2 P1 P0 D7 D0 D7 D0 RA /C WK A C K Fig.17 A C K A C K BR24E16 / F / FJ / FV S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) DATA(n+x) S T O P 1 0 1 0 A2 A1 A0 D7 D0 D7 D0 RA /C WK A C K Fig.18 A C K A C K $ When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words can be read] $ This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH. $ Sequential reading can also be done with a random read. Memory Ics BR24C08 / BR24C08F / BR24C08FJ / BR24C08FV / BR24C16/ BR24C16F / BR24C16FJ / BR24C16FV / BR24E16 / BR24E16F / BR24E16FJ / BR24E16FV External dimensions (Units : mm) BR24C08 BR24C16 BR24E16 BR24C08F BR24C16F BR24E16F 9.3 ± 0.3 8 5 6.5 ± 0.3 5.0 ± 0.2 8 5 6.2 ± 0.3 0.51Min. 7.62 1.5 ± 0.1 0.11 1 4 3.2 ± 0.2 3.4 ± 0.3 1.27 0.4 ± 0.1 0.3Min. 0.15 0.3 ± 0.1 2.54 0.5 ± 0.1 0°~15° DIP8 BR24C08FJ BR24C16FJ BR24E16FJ BR24C08FV BR24C16FV BR24E16FV SOP8 4.9 ± 0.2 8765 3.0 ± 0.2 8 5 6.0 ± 0.3 3.9 ± 0.2 6.4 ± 0.3 4.4 ± 0.2 0.2 ± 0.1 1.375 ± 0.1 1234 0.22 ± 0.1 (0.52) 0.65 0.1 1.15 ± 0.1 1 4 0.175 0.45Min. 1.27 0.42 ± 0.1 0.1 0.3Min. 0.1 SOP-J8 SSOP-B8 0.15 ± 0.1 0.15 ± 0.1 1 4 4.4 ± 0.2