600V High Voltage
3 Phase Bridge Driver
BS2130F-G
Key Specifications
General Description
High-side floating supply voltage:
600V
Output voltage range:
11.5 ~ 20V
Min Output Current Io+/Io-:
200mA/350mA(Typ)
OCP detect voltage
0.46V(Typ)
OCP blanking time
150ns(Typ)
Turn On/Turn Off:
630/580ns(Typ)
Offset supply leakage current:
50µA (Max)
Operating temperature range:
-40°C ~+125°C
The BS2130F is a monolithic bridge driver IC, which can
drive N-channel power MOSFET and IGBT driver in 3
phase systems with bootstrap operations.
The floating channel can be used to driven an N-channel
power MOSFET or IGBT in the high side configuration
which operates up to 600V.
The logic inputs can be used 3.3V and 5.0V.
To provide a protection circuit, the device Includes an
Under Voltage Lockout (UVLO) circuit and an Over
Current Protection (OCP) circuit.
The UVLO circuit prevents malfunction when VCC and
VBS are lower than the specified threshold voltage.
Package
W(Typ) x D(Typ) x H(Max)
18.50mm x 9.90mm x 2.41mm
SOP-28
Features
Floating Channels for Bootstrap Operation to +600V
Gate drive supply range from 11.5V to 20V
Built-in Under Voltage Lockout for Both Channels
The device includes an Over Current Protection circuit
Built-in Enable Channel (EN) which enable I/O
functionality
Built-in FAULT Channel (/FAULT) which indicates over
current and under voltage
RCIN Channel can determine the OCP holding time
by external resistance and capacitance
3.3V and 5.0V input logic compatible
Output in phase with input
Applications
MOSFET and IGBT high side driver applications
Typical Application Circuit
Up to 6V
CC
HN123
N123
FA
EN
RCN
RP
SS
B123
H 123
S123
TO LOD
123
C
Figure 1. Typical Application Circuit
Product structures>Silicon monolithic integrated circuit This product is not designed for protection against radioactive rays
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BS2130F-G
Pin Configuration
(TOP VIEW)
VCC
VB1
HIN1
HO1
HIN2
VS1
HIN3
N.C
LIN1
VB2
LIN2
HO2
LIN3
VS2
FAUL
N.C
I RIP
VB3
EN
HO3
RCIN
VS3
VSS
N.C
CO
LO1
LO3
LO2
Figure 2. Pin Configuration
Pin Description
Pin No.
Symbol
Function
1
VCC
2,3,4
HIN1,2,3
Logic input for high side gate driver outputs (HO1,2,3), in phase
5,6,7
LIN1,2,3
Logic input for low side gate driver outputs (LO1,2,3), in phase
8
/FAULT
Indicates over current or low side undervoltage (negative logic, open-drain output)
9
ITRIP
10
EN
11
RCIN
External RC-network to define FAULT clear delay after the tHOLD
12
VSS
Logic Ground
13
COM
Power Ground
14,15,16
LO1,2,3
Low side gate drive outputs
18,22,26
VS1,2,3,
High side floating supply return
19,23,27
HO1,2,3
High side gate drive outputs
20,24,28
VB1,2,3
High side floating supply
17,21,25
N.C
Low side supply voltage
Analog input for over-current shutdown, activates FAULT and RCIN to VSS
Logic input to enable I/O functionality (positive logic)
Non-Connection
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BS2130F-G
Block Diagram
B1
UT
E
LTE
HIN1
DED TE &
T
T UG
EVET
UT
E
LTE
IN1
UL E
GEE T
V /C
LEVEL
TE
V /C
LEVEL
TE
V
LEVEL
TE
UV
DETECT
E ET
ET
UL E
LTE
HO1
S1
B2
UT
E
LTE
HIN2
DED TE &
T
T UG
EVET
UT
E
LTE
IN2
UL E
GEE T
V /C
LEVEL
TE
V /C
LEVEL
TE
V
LEVEL
TE
UV
DETECT
E ET
ET
UL E
LTE
HO2
S2
B3
UT
E
LTE
HIN3
DED TE &
T
T UG
EVET
UT
E
LTE
IN3
UL E
GEE T
V /C
LEVEL
TE
V /C
LEVEL
TE
V
LEVEL
TE
UV
DETECT
E ET
ET
UL E
LTE
HO3
S3
UV
DETECT
UT
E
LTE
N
I RIP
+
-
UT
E
LTE
04V
Q
L tc
DELY
O1
DELY
O2
DELY
O3
RIN
FA
O
SS
Figure 3. Functional Block Diagram
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BS2130F-G
Absolute Maximum Ratings
(Unless otherwise specified: All voltages are absolute voltages referenced to VSS. VSS=0V, Ta=25 C)
Parameter
Symbol
Min
Max
Unit
High side offset voltage
VS
VB-25
VB+0.3
V
High side floating supply voltage
VB
VCOM-0.3
VCOM+625
V
High side floating output voltage HO
VHO
VS-0.3
VB+0.3
V
Low side and logic fixed supply voltage (VCC vs. VSS)
VCC
-0.3
+25
V
Low side and logic fixed supply voltage (VCC vs. COM)
VCCCOM
-0.3
+25
V
Low side output voltage LO (LO vs. COM)
VLO
-0.3
VCCCOM+0.3
V
Logic input voltage HIN, LIN, EN
VIN
-0.3
VCC+0.3
V
FAULT output voltage
VFLT
-0.3
VCC+0.3
V
RCIN input voltage
VRCIN
-0.3
VCC+0.3
V
ITRIP input voltage
VITRIP
-0.3
VCC+0.3
V
Power ground
VCOM
-5.5
+5.5
V
Allowable offset voltage SLEW RATE
dVS/dt
-
50
V/ns
Junction temperature
Tjmax
-
150
°C
Storage temperature
Tstg
-55
+150
°C
Thermal Resistance(Note 1)
Parameter
Symbol
Thermal Resistance (Typ)
1s
(Note 4)
(Note 3)
2s2p
Unit
SOP28
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
JA
136.9
88.6
°C/W
JT
19
15
°C/W
(Note 1)Based on JESD51-2A(Still-Air)
(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)Using a PCB board based on JESD51-3.
Layer Number of
Measurement Board
Single
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.57mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70m
(Note 4)Using a PCB board based on JESD51-7.
Layer Number of
Measurement Board
4 Layers
Material
Board Size
FR-4
114.3mm x 76.2mm x 1.6mmt
Top
2 Internal Layers
Bottom
Copper Pattern
Thickness
Copper Pattern
Thickness
Copper Pattern
Thickness
Footprints and Traces
70m
74.2mm x 74.2mm
35m
74.2mm x 74.2mm
70m
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BS2130F-G
Recommended Operating Ratings
(Unless otherwise specified: All voltages are absolute voltages referenced to VSS. VSS=0V)
Parameter
Symbol
Min
Max
Unit
High side floating supply offset voltage (VS vs. COM)
VS
-
600
V
High side floating supply voltage (VB vs. VS)
VB
11.5
20
V
High side floating output voltage (HO vs. VS)
VHO
0
VB
V
Low side supply voltage (VCC vs. VSS)
VCC
11.5
20
V
Low side supply voltage (VCC vs. COM)
VCCCOM
11.5
20
V
Low side output voltage LO (LO vs. COM)
VLO
0
VCCCOM
V
Logic input voltage HIN, LIN, EN
VIN
0
VCC
V
FAULT output voltage
VFLT
0
VCC
V
RCIN input voltage
VRCIN
0
VCC
V
ITRIP input voltage
VITRIP
0
VCC
V
Power ground
VCOM
-2.5
+2.5
V
TA
-40
+125
°C
Ambient temperature
Static Logic Function Table
VCC
VBS
RCIN
ITRIP
EN
FAULT
HO1,2,3
LO1,2,3
VRCIN+
0V
0V
High-Z
0
0
(Note 1)
0
(Note 1)
0
(Note 1)
(Note 1) State after the OCP. Because the latch circuit is not reset, the OCP state is maintained.
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BS2130F-G
DC Operation Electrical Characteristics
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VSS=VCOM, CL=1000pF)
Parameter
Symbol
Limits
Min
Typ
Max
VCC and VBS supply undervoltage
positive going threshold
VCCUV+
VBSUV+
9.6
10.4
11.2
VCC and VBS supply undervoltage
negative going threshold
VCCUVVBSUV-
8.6
9.4
10.2
VCC supply undervoltage lockout
hysteresis
VCCUVH
VBSUVH
-
1.0
-
ILK
-
-
50
Offset supply leakage current
Unit
Conditions
V
VB = VS = 600V
µA
Quiescent VBS supply current
IQBS
-
60
120
VIN = 0V or 5V
Quiescent VCC supply current
IQCC
-
0.7
1.3
Logic
VIH
2.6
-
-
VIL
-
-
0.8
EN positive going threshold
VEN+
-
-
2.6
EN negative going threshold
VEN-
0.8
-
-
VRCIN+
-
8
-
VRCIN,HYS
-
3
-
ITRIP positive going threshold
VIT,TH+
0.437
0.46
0.483
ITRIP hysteresis
VIT,HYS
-
0.07
-
High level output voltage, VCC (VBS) - VO
VOH
-
-
1.4
Low level output voltage, VO
VOL
-
-
0.6
IIN+
-
100
150
L
IIN-
-
-
1.0
IITRIP
-
1
2
VITRIP = 0V or 3.3V
IO+
120
200
-
VO = 0V
Pulse Width
10µs
VO = 15V
Pulse Width
10µs
mA
VIN = 0V or 5V
V
RCIN positive going threshold
V
RCIN hysteresis
V
V
ITRIP input bias current
Output high short circuit pulse current
VIN = 3.3V
µA
mA
Output low short circuit pulsed current
IO-
250
350
-
RCIN input bias current
IRCIN
-
-
1
RCIN low on resistance
RON_RCIN
-
50
100
IO = 20mA
VIN = 0V
µA
VRCIN = 0.5V
FAULT low on resistance
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100
VFAULT = 0.5V
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02.Feb.2017 Rev.003
BS2130F-G
AC Operation Electrical Characteristics
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VSS=VCOM, CL=1000pF)
Parameter
Symbol
Limits
Min
Typ
Max
Unit
Conditions
Turn-on propagation delay
ton
480
630
780
VS = 0V, VIN = 0V & 5V
Turn-off propagation delay
toff
430
580
730
VS = 0V or 600V, VIN =0V&5V
Turn-on rise time
tr
-
125
190
VIN = 0V & 5V
Turn-off fall time
tf
-
50
75
VIN = 0V & 5V
tEN
430
580
730
VIN ,VIN = 0V & 5V
tITRIP
500
750
1000
EN low to output shutdown propagation
delay
ITRIP to output shutdown propagation
delay
ITRIP blanking time
VITRIP = 5V
ns
tbl
100
150
-
VITRIP = 5V
ITRIP to FAULT propagation delay
tFLT
400
600
800
VITRIP = 5V
Input filter time (HIN,LIN)
tFILIN
100
200
-
VIN = 0V & 5V
Enable input filter time
tFLTEN
100
200
-
VIN = 0V & 5V
Dead time
DT
250
300
450
VIN = 0V & 5V
Delay matching, HS & LS turn-on/off
MT
-
-
150
tFLTCLR
1.3
1.65
2.0
FAULT clear time
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ms
RCIN : R = 2M, C = 1nF
TSZ02201-0Q3Q0BZ00520-1-2
02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
15.0
15.0
VCCUV+
12.0
VBSUV+
12.0
9.0
VB-VS[V]
VCC[V]
9.0
VCCUV-
VBSUV-
6.0
6.0
3.0
3.0
0.0
0.0
-50
-25
0
25
50
75
100
125
-50
-25
0
Ambient Temperature[ºC]
25
50
75
100
125
Ambient Temperature[ºC]
Figure 5. VBS UVLO - Ta
Figure 4. VCC UVLO - Ta
1.0
1.0
Ta=150
0.8
0.6
0.6
IVS[uA]
IVS[uA]
0.8
0.4
0.4
0.2
0.2
0.0
0.0
0
100
200
300
400
500
600
700
VS[V]
0
40
80
120
160
Ambient Temperature[ºC]
Figure 7. Offset supply leakage current
(VB=VS=600V)
Figure 6. Offset supply leakage current - VS
(VB=VS)
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02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
0.8
0.8
0.6
0.6
IQCC [mA]
1.0
IQCC [mA]
1.0
0.4
0.4
0.2
0.2
0.0
0.0
0
2
4
6
8
10
12
14
16
18
20
-50
-25
0
VCC[V]
25
50
75
100
125
Ambient Temperature[ºC]
Figure 8. Quiescent VCC supply current - VCC
Figure 9. Quiescent VCC supply current
(VCC=15V)
Ta
125
125
100
100
75
IQBS[uA]
IQBS[uA]
75
50
50
25
25
0
0
0
2
4
6
8
10
12
14
16
18
20
VBS[V]
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Figure 10. Quiescent VBS supply current - VBS
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Figure 11. Quiescent VBS supply current
(VBS=15V)
9/27
Ta
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02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
2.5
2.5
VIH
VIH
2.0
1.5
1.5
HIN[V]
LIN[V]
2.0
1.0
1.0
VIL
VIL
0.5
0.5
0.0
0.0
-50
-25
0
25
50
75
100
125
-50
-25
0
Ambient Temperature[ºC]
25
50
75
100
125
Ambient Temperature[ºC]
Figure 13. Logic 1/0 Input Voltage LIN - Ta
Figure 12. Logic 1/0 Input Voltage HIN - Ta
1000
0.8
800
0.6
VIT,TH+
VIT[V]
IIN [uA]
600
0.4
400
VIT,TH-
0.2
200
0
0
0
2
4
6
8
10
12
14
16
18
20
VIN [V]
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Figure 14. Logic 1 Input bias current - VIN
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Figure 15. ITRIP threshold Voltage - Ta
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02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
2.0
2.0
Io=20mA
Io=20mA
1.5
VLO(VHO)-COM(VS)[V]
VCC(VB)-VLO(VHO)[V]
1.5
1.0
0.5
1.0
0.5
0.0
0.0
-50
-25
0
25
50
75
100
125
-50
-25
0
Ambient Temperature[ºC]
25
50
75
100
125
Ambient Temperature[ºC]
Figure 16. High Level Output Voltage - Ta
Figure 17. Low Level Output Voltage - Ta
100
100
VRCIN=0.5V
VFAULT=0.5V
60
60
Ron[ ]
80
Ron[ ]
80
40
40
20
20
0
0
-50
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Figure 18. RCIN low on Resistance - Ta
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Figure 19. FAULT low on Resistance - Ta
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02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
1000
2
1.6
Turn-on
600
1.2
Tr/Tf[us]
Propagation Delay[ns]
800
Turn-off
400
Rise
0.8
Fall
200
0.4
0
0
-50
-25
0
25
50
75
100
125
0
2500
Ambient Temperature[ºC]
Figure 20. HO Turn on/off Propagation Delay - Ta
Figure 21. HO Rise/Fall Time
1000
7500
10000
Load Capacitance
2
800
1.6
Turn-on
600
1.2
Tr/Tf[us]
Propagation Delay[ns]
5000
CL[pF]
Turn-off
400
Rise
0.8
Fall
200
0.4
0
0
-50
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
2500
5000
7500
10000
CL[pF]
Figure 22. LO Turn on/off Propagation Delay - Ta
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0
Figure 23. LO Rise/Fall Time
12/27
Load Capacitance
TSZ02201-0Q3Q0BZ00520-1-2
02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
500
400
400
[ns]
Dead Time LO HO[ns]
500
Dead Time HO
300
200
300
200
100
100
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Ambient Temperature[ºC]
Figure 25. Dead time Ta (LO off HO on)
Figure 24. Dead time Ta (HO off LO on)
1000
80
800
Propagation Delay[ns]
100
MT[ns]
60
40
20
600
400
200
0
-50
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
-50
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Figure 26. Delay matching Turn on/off - Ta
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Figure 27. ITRIP to Output Shutdown
Propagation Delay - Ta
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02.Feb.2017 Rev.003
BS2130F-G
Typical Performance Curves
(Unless otherwise specified: Ta=25°C, VCC=15V, VBS=15V, VS=VPGND=VGND, CL=1000pF)
1000
5
800
4
600
3
Time[ns]
Propagation Delay[ns]
RCIN>R=2M ,C=1nF
400
2
200
1
0
0
-50
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
-25
0
25
50
75
100
125
Ambient Temperature[ºC]
Figure 28. ITRIP to FAULT Propagation Delay - Ta
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Figure 29. FAULT clear time - Ta
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02.Feb.2017 Rev.003
BS2130F-G
Timing Chart
5
HIN
LIN
ton
5
toff
tr
9
9
HO
LO
tf
1
1
(a) Propagation Delay
DT
DT
(b) Dead time
Figure 30. Timing Chart
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BS2130F-G
Timing Chart
HN
LN
EN
Shu dwn
HO
LO
In enl Ded ime
Sh -huh Sh -huh
Sh -huh
Peven in
Peven in
Peven in
Figure 31. Timing Chart
VG
VCC
VCC
+
VCC
FAU
Figure 32. VCCUVLO Timing Chart
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BS2130F-G
Over Current Protection
As soon as ITRIP voltage is exceeded the threshold voltage 0.46V (typ), impedance of the /FAULT pin is lowered and
the RCIN pin turns off.
ITRIP blanking time 150ns (typ) prevents the driver to detect false over-current events which caused by noise. However, it is
recommended to add a ceramic capacitor near the ITRIP pin.
FAULT clear time is determined by external resistance and capacitance. As soon as RCIN voltage exceeds the rising
threshold voltage 8V (typ), the FAULT condition releases. Also, RCIN voltage operates in the voltage less than VRCIN+.
However, it is not returned with stopping when ITRIP voltage goes over threshold voltage V IT,TH+ once. RCIN voltage to
recommend at the normal operation is more than VRCIN+.
+
-
P
"#$+
# "
ig !
%&'(
ig !
")
*,(*
,(
Figure 33. OCP Detection Timing Chart
The over current detection value is determined by R1, R2, and RS, which are connected to ITRIP pin as Figure 34.
The over current detection value is determined by the following equation.
Iocp =
R1+R2
VIT,TH+
R2
RS
Iocp>over current detection value
VIT,TH+>OCP threshold voltage 0.46V(typ)
Rs>Shunt resistor
The reset time of FAULT is determined by the following equation.
tFLTCLR = -(RRCINCRCIN)ln(1-
VRCIN,TH+
VCC
)
VRCIN+>RCIN threshold voltage 8V(typ)
Up to
V
CC
R
C
HN123
B123
N123
H123
FA
I
S123
TO LOD
EN
RCN
IR
SS
123
C
R1
R2
RS
Figure 34. OCP Detection Schematic
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BS2130F-G
Application Components Selection Method
(1) Gate Resistor
The gate resistor RG(on/off) is selected to control the
switching speed of the output transistor. The
switching time (tSW) is defined as the time spent to
reach the end of the plateau voltage, so the turn on
gate resistor RG(on) can be calculated using the
following formulas.
Ig
Qgs Qgd
t sw
R (on)
HO
Rnoff
Cgs
R (off)
R pon RG ( on)
Qgs
Qgd
Cg
Rpon
(1)
t SW
RTOTAL ( on)
B
Ig
VBS
Vgs(th )
Ig
(2)
Figure 35. Gate Driver Equivalent Circuit
(Qgs
Qgd )( R pon
RG ( on) )
(VBS
B2130F
Vgs(th ) )
(3)
VD
Turn on gate resistor value can be changed to
control output slope (dVs/dt). While the output
voltage is non-linear, the maximum output slope
should have a value near that of the following
formula:
dVs
dt
ID
VG
Ig
dV/d
(4)
C rss
where:
Crss is the feedback capacitance.
S
Substituting the value of Ig from equation (2) into
equation (4) yields the following formulas.
RTOTAL ( on)
RG ( on)
VBS
R pon RG ( on)
V gs(th )
dVs
C rss
dt
VBS
V gs(th )
dVs
C rss
dt
Figure 36. Gate Charge Transfer Characteristics
R pon
(5)
(6)
When the gate driver output is in off state, other dVs/dt may induce a drop in the gate voltage of the MOSFET, causing
self-turn-on. To prevent this, please set up the turn off resistor (RG(off)) that satisfies the following formulas.
Vgs( th )
R G ( off )
(R noff
R G ( off ) ) I g
Vgs( th )
dVs
C gd
dt
(R noff
R G ( off ) ) Cgd
R noff
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dVs
dt
(7)
(8)
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BS2130F-G
(2) Bootstrap Capacitor CBS
To reduce ripple voltage, ceramic capacitors with low ESR value are recommended for use in the bootstrap circuit.
The maximum voltage drop (VBS) that we have to guarantee when the high-side switch is in on state must be:
VBS VCC VF VGSMIN
(9)
where:
VCC is the gate driver supply voltage,
VF is the bootstrap diode forward voltage drop, and
VGSMIN is the minimum gate-source voltage.
The total charge supplied (QTotal) by the bootstrap capacitor should have a value near the following formulas.
QTotal QG ( I LKGS I LK I LKDIO I QBS ) THON
(10)
where:
QG is the total gate charge,
ILKGS is the switch gate-source leakage current,
ILKDIO is the bootstrap diode leakage current,
ILK is the level shifter circuit leakage current,
IQBS is the quiescent current, and
THON is the high-side switch on time.
The bootstrap capacitor value should satisfy the following formula.
C BS
QTotal
VBS
(11)
However, BS2130F has a BSTUVLO function to prevent malfunction at low voltage between VB and VS.
Please ensure sufficient capacitor margin to prevent BSTUVLO malfunction.
It is not able to keep turning-on the same way as the high side switch driver because of the specifications of the
bootstrap circuits.
In addition, it is recommended to insert a 1
F ceramic capacitor between VB and VS. This capacitor should be placed as
close as possible to these pins for noise reduction.
F
CC
HI123
I123
FA
E
RCI
IRIP
SS
B123
H123
S123
Up to V
C
GS
TO LO D
123
C
Figure 37. Bootstrap Power Supply Circuit
(3) Input Capacitor
Mount a low-ESR ceramic input capacitor near the VCC pin to reduce input ripple.
For BS2130F, it is recommended to use a capacitor value two times larger than that of the bootstrap capacitor or more.
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BS2130F-G
(4) Input Signals Differential IN
The minimum differential
IN(min)) to
prevent shoot-through of the MOSFETs can be
calculated using the following formula.
tdead
(ton tIN ) (toff
tf )
LIN(HIN)
5
(12)
HIN(LIN)
tf
(ln 0.1 ln 0.9)
( Rnon RG ) CL
Ct
5
(13)
(14)
LO(HO)
tf
9
toff
ton : Turn-on propagation delay
toff : Turn-off propagation delay
tf : Turn-off fall time
Rnon : On-resistance of Nch MOSFET
constituting the final stage inverter
RG : Gate resistor
CL : Load capacitor
HO(LO)
0
tdd
t
* IN '
t
(toff
/ IN (min) .
Figure 38. Shoot-Through Prevention Timing Chart
(15)
(ton " $tIN ) # (toff
"
tf ) ! 0
t ) %tf
& ON
(16)
(17)
(toff (max) + ton(min) ) + ( Rnon(max) - RG ) , CL , (ln 0.1 + ln 0.9)
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TSZ2211115001
ton
1
Please set up tIN that satisfies the following formulas.
tdead
1
20/27
(18)
TSZ02201-0Q3Q0BZ00520-1-2
02.Feb.2017 Rev.003
BS2130F-G
Overshoot / Undershoot of Output Terminal
The occurrence of overshoot / undershoot may be detected by the parasitic inductance of the bonding wire and the PCB. The
mechanism of overshoot in the switching off is Figure 40.
(1) After PchFET is turn-off, current flows from HO to VB through capacitance between G-D and G-S.
(2) The current flows from HO to VB through parasitic diode of PchFET. Forward voltage Vf of the parasitic diode is increased,
and HO voltage becomes VB+Vf. NchFET is turn-on and it is discharged to VS.
The undershoot of the switching on may be caused by the same mechanism, too.
In addition, it may be caused in low side output LO because the circuit structure is the same. The overshoot / undershoot
voltage changes by the current of the parasitic diode.
When the overshoot / undershoot voltage is large, please adjust the gate resistance to slow in order to the switching speed
and connect to reduce the parasitic inductance.
Parastc nuctanc of t bonn wr an PC
!"!# d!$d% &d # ' !" &#% (%")%%& G-* &d G-D
Figure 39. Schematic with Parasitic Inductance
(1)
(2)
VB
Vg
p
Vi
HO
Vg
FF
VS
Figure 40. Mechanism of Overshoot
Overshoot
Figure 41. Overshoot Wave
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BS2130F-G
Power Dissipation
It is shown below reducing characteristics of power dissipation to mount 114.3mm
Junction temperature must be designed not to exceed 150°C.
76.2mm.
SOP28Pacage
4lnaglyers(114.
3mmx76.2mmx1.6mmtt))
e (114.3mmx76.2mmx1.57mm
DSi
D
C
Figure 42. Power Dissipation
PCB Layout
1.
Power GND and Logic GND
Surge voltage is caused by current of Power GND and parasitic inductance of the wire. It may cause malfunction by GND
fluctuation. It is recommended to connect Power GND and Logic GND at only a point.
2.
Shunt Resistor
It is recommended to locate a shunt resistor near the external power MOSFET of low side. If the wiring is long, surge
voltage is caused by parasitic inductance. The wiring to the ITRIP should be divided near the shunt resistor.
3.
ITRIP Filter Capacitor
To prevent a malfunction, it is recommended to locate a ceramic capacitor near ITRIP pin. GND of the capacitor should be
connected to Logic GND.
4.
Input Capacitor and Zener Diode
An input capaciter and a zener diode, a bootstrap capacitor should be located near the pin. It is recommended to select a
low ESR capacitor such as a ceramic-type.
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BS2130F-G
I/O Equivalence Circuits
Pin.No
Pin
Name
Pin Equivalent Circuit
Pin.No
Pin
Name
Pin Equivalent Circuit
VCC
1
VCC
12
VSS
13
COM
VSS
2,3,4
HIN1,2,3
5,6,7
LIN1,2,3
10
EN
LIN
HIN
EN
C
8
/FAULT
11
RCIN
R
FAU
9
T
P
ITRIP
B
14,15,16 LO1,2,3
O
18,22,26
VS1,2,3
19,23,27
HO1,2,3
20,24,28
VB1,2,3
O
M
Figure 43. I/O Equivalent Circuits
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BS2130F-G
Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC s power
supply pins.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded the rise in temperature of the chip may result in
deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the board size
and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately
obtained. The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may
flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,
and routing of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always disc
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
10.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)
and unintentional solder bridge deposited in between pins during assembly to name a few.
11.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
13.
Area of Safe Operation (ASO)
Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all
within the Area of Safe Operation (ASO).
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BS2130F-G
Ordering Information
B
S
2
1
3
Part Number
0
F
-
Package
F: SOP-28
GE 2
Package Material
G: Halogen Free type
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
SOP28 (TOP VIEW)
Part Number Marking
BS2130F
LOT Number
1PIN MARK
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BS2130F-G
Physical Dimension, Tape and Reel Information
Package Name
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SOP28
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02.Feb.2017 Rev.003
BS2130F-G
Revision History
Date
Revision
Changes
26.Feb.2016
001
New Release
31.May.2016
002
Addition P.21 Overshoot / Undershoot of Output Terminal
Correction of errors P.4, P23
02.Feb.2017
003
Change of Absolute Maximum Ratings notation
(Notation only. There is no change in rating)
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Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property ( Specific Applications), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASS
CLASSb
CLASS
CLASS
CLASS
CLASS
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or
Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.003
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
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Rev.003
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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