BU1852GUW-E2

GPIO ICs Keyencoder IC BU1852GUW No.11098EAT04 ●Description Keyencoder IC BU1852GUW can monitor up to 8x12 matrix (96 keys), which means to be adaptable to Qwerty keyboard. We adopt the architecture that the information of the only key which status is changed, like push or release, is encoded into the 8 bits data. This can greatly reduce the CPU load which tends to become heavier as the number of keys increase. (Previously, all key's status is stored in the registers.) When the number of keys is small, the extra ports can be used as GPIO. Furthermore, auto sleep function contributes to low power consumption, when no keys are pressed. It is also equipped with the various functions such as ghost key rejection, N-key Rollover, Built-in power on reset and oscillator. ●Features 1) Monitor up to 96 matrix keys. 2) Under 3µA Stand-by Current 3) Built-in Power on Reset. 4) Ghost key rejection. 5) Keyscan / GPIO selectable 6) 3 volt tolerant Input ●Absolute maximum ratings (Ta=25℃) Parameter Symbol VDD Supply Voltage VDDIO VI1 Input voltage VI2 VIT Storage temperature range Package power ※ ※1 ※2 Ratings -0.3 ~ +2.5 -0.3 ~ +4.5 -0.3 ~ VDD +0.3※ 1 Unit V V V V V ℃ mW Conditions VDD≦VDDIO XRST, XI, TW, PORENB ADR XINT, SCL, SDA, COL[11:0], ROW[7:0] -0.3 ~ VDDIO +0.3※1 -0.3 ~ +4.5 -55 ~ +125 272※2 Tstg PD This IC is not designed to be X-ray proof. It is prohibited to exceed the absolute maximum ratings even including +0.3 V. Package dissipation will be reduced each 2.72mW/℃ when the ambient temperature increases beyond 25℃. ●Operating conditions Parameter Supply voltage range (VDD) Supply voltage range (VDDIO) Symbol VDD VDDIO VI1 Input voltage range VI2 VIT Operating temperature range Topr Ratings Min. 1.65 1.65 -0.2 -0.2 -0.2 -30 Typ. 1.80 1.80 25 Max. 1.95 3.60 VDD+0.2 VDDIO+0.2 3.60 +85 Unit V V V V V ℃ XRST, XI, TW, PORENB ADR XINT, SCL, SDA, COL[11:0], ROW[7:0] Conditions www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 1/24 2011.01 - Rev.A BU1852GUW ●Electrical characteristics 1. DC characteristics (VDD=1.8V, VDDIO=1.8V, Ta=25℃) Parameter Input H Voltage1 Input H Voltage2 Input H Voltage3 Input H Voltage4 Input L Voltage1 Input L Voltage2 Input H Current1 Input H Current2 Input L Current Output H Voltage1 Output H Voltage2 Output L Voltage1 Output L Voltage2 ※1 ※2 ※3 ※4 ※5 ※6 Technical Note Symbol VIH1 VIH2 VIH3 VIH4 VIL1 VIL2 IIH1 IIH2 IIL VOH1 VOH2 VOL1 VOL2 Limits Min. 0.8xVDD 0.8xVDD 0.8xVDDIO 0.8xVDDIO -0.2 -0.2 -1.0 -1.0 -1.0 0.75xVDD 0.75xVDDIO Typ. - Max. 3.6 VDD+0.2 3.6 VDDIO+0.2 Unit V V V V V V µA µA µA V V V V ※1 Conditions ※2 COL[11:0] ADR ※3 0.2xVDD 0.2xVDDIO 1.0 1.0 1.0 0.25xVDD 0.25xVDDIO ADR, COL[11:0] VIN=3.60V※ Pull-down/up OFF VIN=1.80V※5 VIN=0V Pull-down/up OFF IOH=-2mA, ROW[7:0] IOH=-2mA, COL[11:0] IOL=2mA, ※6 IOL=2mA, COL[11:0] 4 - XINT,SCL,SDA,ROW[7:0] XRST,XI,TW,PORENB XINT,SCL,SDA,ROW[7:0],XRST,XI,TW,PORENB XINT,SCL,SDA,ROW[7:0],COL[11:0] XRST,XI,TW,PORENB,ADR XINT,SDA,ROW[7:0] 2. Circuit Current (VDD=1.8V, VDDIO=1.8V, Ta=25℃) Parameter Symbol IPD IPDIO ISTBY1 ISTBYIO1 ISTBY2 ISTBYIO2 IOP Limits Min. Typ. 50 Max. 1.0 1.0 3.0 1.0 1.0 1.0 110 Unit µA XRST=VSS µA µA µA µA µA µA XRST=VDD, PORENB=VSS, SCL=VDD, SDA=VDD Conditions Power Down Current (VDD) Power Down Current (VDDIO) Standby Current1 (VDD) Standby Current1 (VDDIO) Standby Current2 (VDD) Standby Current2 (VDDIO) Operating Current (VDD) XRST=VDD, PORENB=VDD, SCL=VDD, SDA=VDD Internal oscillator is used. one key is pressed. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 2/24 2011.01 - Rev.A BU1852GUW 3. 2 I C AC Characteristics Technical Note Condition (Repeated) START tSU;STA BIT7 BIT6 1/fSCLK Ack STOP tLOW SCL tHIGH SDA tSU;DAT tSU;STO tBUF tHD;STA tHD;DAT Fig.1 I2C AC timing VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS Parameter SCL Clock Frequency Bus free time (Repeated) START Condition Setup Time (Repeated) START Condition Hold Time SCL Low Time SCL High Time Data Setup Time Data Hold Time STOP Condition Setup Time Symbol fSCL tBUF tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tSU;STO Limits Min. 1.3 0.6 0.6 1.3 0.6 100 0 0.6 Typ. Max. 400 Unit kHz µs µs µs µs µs ns ns µs Conditions www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 3/24 2011.01 - Rev.A BU1852GUW 4. GPIO AC Characteristics State BIT1 BIT0 A NA Technical Note SCL tDV GPIO[7:0](Output) GPIO[7:0](Input) tIV XINT tIR Fig.2 VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS Parameter Output Data Valid Time Interrupt Valid Time Interrupt Reset Time Symbol tDV tIV tIR GPIO AC timing Limits Min. Typ. Max. 0.8 5 5 Unit µs µs µs Conditions www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 4/24 2011.01 - Rev.A BU1852GUW 5. Startup sequence tVDD VDD VDDIO XRST tVDD tI2CWAIT SCL SDA tI2CWAIT Technical Note tVDD tVDD tRWAIT tRV tRWAIT Fig.3 Start Sequence timing VDD=1.8V, VDDIO=1.8V, Topr=25℃, TW=VSS Parameter VDD Stable Time Reset Wait Time Reset Valid Time I2C Wait Time Symbol tVDD tRWAIT tRV tI2CWAIT Limits Min. 0 10 10 Typ. Max. 5 Unit ms µs µs µs Conditions VDD and VDDIO are ON at the same time. XRST controlling※1 ※1 Even if XRST port is not used, it operates because Power On Reset is built in. In this case, connect XRST port with VDD on the set PCB. Note) At VDD=0V, when SCL port is changed from 0V to 0.5V or more, SCL port pulls the current. It is same in SDA, XINT, and ROW[7:0] ports of 3V tolerant I/O. (VDDIO=0V in case of COL[11:0] ports) VDD 0V Port 3V (~2kΩ Pull-up) 0V Port Pull Current 0.1～1mA 2～3ms Fig.4 Port operating at VDD=0V www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 5/24 2011.01 - Rev.A BU1852GUW ●Package Specification Technical Note U 1852 Lot No. Fig.5 Package Specification (VBGA035W040) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 6/24 2011.01 - Rev.A BU1852GUW ●Pin Assignment Technical Note 1 A TESTM0 2 XI 3 ROW 0 4 ROW 2 5 ROW4 6 TW B XRST ROW 1 ROW 3 ROW 6 ROW 5 C XINT VDD PORENB VSS ROW7 COL0 D SDA VDD VDDIO VSS COL2 COL1 E SCL COL10 COL8 COL6 COL4 COL3 F TESTM1 COL11 COL9 COL7 COL5 ADR Fig.6 Pin Diagram (Top View) ●Block diagram XI VDD TESTM[1:0] ADR TW SCL SDA 2 VDDIO Oscillator Input Filter I C / 3 wire Control Key Encoder + FIFO COL[11:0]/ GPIO[19:8] Key Scan / GPIO Control ROW[7:0]/ GPIO[7:0] XINT Interrupt Filter Interrupt Logic XRST PORENB VSS Power on Reset Reset Gen Fig.7 Functional Block Diagram www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 7/24 2011.01 - Rev.A BU1852GUW ●Pin Functional Descriptions PIN name VDD VDDIO VSS XRST XI TW I/O I I I Function Power supply (Core, I/O except for COL[11:0], ADR) Power supply (I/O for COL[11:0], ADR) GND Reset(Low Active) External clock input (32kHz) Select protocol H: original 3 wire 2 L: IC 2 (TW=L) Select Device Address for I C (TW=H) H : Key scan rate 1/2 L : Key scan rate original Technical Note Init I I I Cell Type A I B ADR XINT SCL SDA ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 PORENB TESTM0 TESTM1 I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I H(TW=H) Hi-z(TW=L) I I B E D F Key/GPIO Interrupt Clock for serial interface Serial data inout for serial interface ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 / GPIO0 / GPIO1 / GPIO2 / GPIO3 / GPIO4 / GPIO5 / GPIO6 / GPIO7 / GPIO8 / GPIO9 / GPIO10 / GPIO11 / GPIO12 / GPIO13 / GPIO14 / GPIO15 / GPIO16 / GPIO17 / GPIO18 / GPIO19 I [100kΩ Pull-up] G L(TW=H) I [150kΩ Pull-down] (TW=L) H Power on reset enable (Low Active) Test Pins※1 I I B C ※1 Note: All these pins must be tied down to GND in normal operation. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 8/24 2011.01 - Rev.A BU1852GUW ●I/O equivalence circuit Technical Note A B C D E F G H I Fig.8 Equivalent I/O circuit diagram www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 9/24 2011.01 - Rev.A BU1852GUW Technical Note ●Functional Description 1. Power mode The device enters the state of Power Down when XRST=”0”. When XRST becomes High after powered, the device enters the standby state. Power On Reset A Power On Reset logic is implemented in this device. Therefore, it will operate correctly even if the XRST port is not used. In this case, the XRST port must be connected to “1” (VDD), and the PORENB port must be connected to “0” (VSS). If you don’t want to use Power On reset, you must connect PORENB port to “1” (VDD). Power Down State 2 The device enters Power Down state by XRST=”0”. An internal circuit is initialized, and key encoding and 3wire/I C interface are invalid. Power On Reset becomes inactive during this state. Stand-by State The device enters the stand-by state by setting XRST to "1". In this state, the device is waiting for keys pressed or 2 2 I C communication (TW=”0”). When a key is pressed or I C start condition, the state will change to operation. Power On Reset is active in this state if PORENB = “0”. Operating State The device enters the operating state by pressing keys. The device will scan the key matrix and encode the key code, and then the 3wire/I2C interface tries to start communication by driving XINT “0”. See next section for the details. After communicating with host device, when no keys are pressed, the device returns to the stand-by state. Power On Reset is active in this state if PORENB=”0”. 2. Protocol of serial interface 2 IC When set to TW=”0”, SCL and SDA are used for I2C communication. Any register shown in section 4 can be 2 accessed through I C. Initially, all GPIO ports are set to GPI and pull-up/down ON. When the application requires GPO or key scan, proper register setting should be done through I2C. 3 wire (Original) When set to TW=”1”, SCL and SDA are used for original 3wire communication, which is not the standard interface. Any register shown in section 4 cannot be accessed through 3wire. With TW=”1”, only keyscan and key encoding are supposed to be performed. GPIO function is inactive. When the application needs kind of complex system (for instance, GPO+keyscan or GPIO+keyscan…), I2C mode is recommended. See appendix for the details. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 10/24 2011.01 - Rev.A BU1852GUW 3. 2 Technical Note I C Bus Interface (TW=”0”) Each function of GPIO is controlled by internal registers. The I2C Slave interface is used to write or read those internal registers. The device supports 400kHz Fast-mode data transfer rate. Slave address Two device addresses (Slave address) can be selected by ADR port. A7 ADR=0 ADR=1 0 0 A6 0 0 A5 0 0 A4 1 1 A3 0 1 A2 1 0 A1 0 1 R/W 1/0 Data transfer One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep the value. If SDA changes during SCL = “1”, START condition or STOP condition occur and it is interpreted as a control signal. SDA SCL Data is valid SDA is when SDA is stable variable Fig.9 Data transfer START・STOP・Repeated START conditions When SDA and SCL are “1”, the data isn’t transferred on the I2C bus. If SCL remains “1” and SDA transfers from “1” to “0”, it means “Start condition” is occurred and access is started. If SCL remains “1” and SDA transfers from “0” to “1”, it means “Stop condition” is occurred and access is stopped. It becomes repeated START condition (Sr) the START condition enters again although the STOP condition is not done. SDA SCL S Sr Repeated START Condition P STOP Condition START Condition Fig.10 START・STOP・Repeated START conditions www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 11/24 2011.01 - Rev.A BU1852GUW Technical Note Acknowledge After start condition is occurred, 8 bits data will be transferred. SDA is latched by the rising edge of SCL. After 8 bits data transfer is finished by the “Master”, “Master” opens SDA to “1”. And then, “Slave” de-asserts SDA to “0” as “Acknowledge”. SDA output from “Master” Not acknowledge SDA output from “Slave” SCL 1 2 Acknowledge S START condition Fig.11 Acknowledge Writing protocol Register address is transferred after one byte of slave address with R/W bit. The 3rd byte data is written to internal nd register which defined by the 2 byte. However, when the register address increased to the final address (18h), it will be reset to (00h) after the byte transfer. S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave address R/W=0(write) Transmit from master Transmit from slave Register address data Register address increment A= acknowledge A= not acknowledge S= Start condition P= Stop condition 8 Clock pulse For Acknowledgs 9 D7 D6 D5 D4 D3 D2 D1 D0 A P data Register address increment Fig.12 Writing protocol www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 12/24 2011.01 - Rev.A BU1852GUW Technical Note Reading protocol After Writing the slave address and Read command bit, the next byte is supposed to be read data. The reading register address is the next of the previous accessed address. Reading address is incremented one by one. When the incremented address reaches the last address, the following read address will be reset to (00h). S X X X X X X X 1 A D7 D6 D5 D4 D3 D2 D1 D0 A Salve address R/W=1(Read) data Register Address increment D7 D6 D5 D4 D3 D2 D1 D0 A P data Register address increment Transmit from master Transmit from slave A=acknowledge A=not acknowledge S=Start condition P=Stop condition Fig.13 Readout protocol Complex reading protocol There is the complex reading protocol to read the specific address of registers that master wants to read. After the specifying the internal register address as writing command, master occurs repeated START condition with read command. Then, the reading access of the specified registers is supposed to start. The register address increment is the same as normal reading protocol. If the address is increased to the last, it will be reset to (00h). S X X X X X X X 0 A X X X A4 A3 A2 A1 A0 A Sr X X X X X X X 1 A Slave address R/W=0(write) Register address Slave address R/W=1(read) D7 D6 D5 D4 D3 D2 D1 D0 A data Register address increment D7 D6 D5 D4 D3 D2 D1 D0 A P data Register address increment A=acknowledge A=not aclnowledge S=Start condition P=Stop condition Sr=Repeated Start condition Transmit from master Transmit from slave Fig.14 Complex reading protocol 2 Illegal access of I C When illegal access happens, the data is annulled. The illegal accesses are as follows. ・The START condition or the STOP condition is continuously generated. ・When the Slave address and the R/W bit are written, repeated START condition or the STOP condition are generated. ・Repeated START condition or the STOP condition is generated while writing data. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 13/24 2011.01 - Rev.A BU1852GUW 4. Technical Note Register configuration Table1 shows the register map and Table2 indicates each function in the corresponding bit. Only when TW is “0”, these 2 registers can be accessed with I C. By making XRST “0”, the setting register value will be initialized shown in following register map. Table1 Register map Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h Init 00h 00h 11h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R reserved reserved GPI15 GPI7 reserved reserved GPI14 GPI6 reserved reserved GPI13 GPI5 D7 RESET reserved reserved reserved KS_C7 KS_R7 reserved IOD15 IOD7 reserved INTEN15 INTEN7 reserved GPO15 GPO7 reserved XPD15 XPU7 reserved reserved reserved KS_C6 KS_R6 reserved IOD14 IOD6 reserved INTEN14 INTEN6 reserved GPO14 GPO6 reserved XPD14 XPU6 reserved reserved reserved KS_C5 KS_R5 reserved IOD13 IOD5 reserved INTEN13 INTEN5 reserved GPO13 GPO5 reserved XPD13 XPU5 reserved reserved reserved KS_C4 KS_R4 reserved IOD12 IOD4 reserved INTEN12 INTEN4 reserved GPO12 GPO4 reserved XPD12 XPU4 reserved reserved D6 reserved reserved D5 reserved reserved D4 reserved reserved D3 reserved reserved KS_RATE * KS_C11 KS_C3 KS_R3 IOD19 IOD11 IOD3 INTEN19 INTEN11 INTEN3 GPO19 GPO11 GPO3 XPD19 XPD11 XPU3 reserved reserved 1 D2 reserved reserved D1 reserved reserved D0 reserved CLKSEL KS_C10 KS_C2 KS_R2 IOD18 IOD10 IOD2 INTEN18 INTEN10 INTEN2 GPO18 GPO10 GPO2 XPD18 XPD10 XPU2 reserved reserved KS_C9 KS_C1 KS_R1 IOD17 IOD9 IOD1 INTEN17 INTEN9 INTEN1 GPO17 GPO9 GPO1 XPD17 XPD9 XPU1 reserved reserved KS_C8 KS_C0 KS_R0 IOD16 IOD8 IOD0 INTEN16 INTEN8 INTEN0 GPO16 GPO8 GPO0 XPD16 XPD8 XPU0 INTFLT reserved keycode Reserved Reserved GPI12 GPI4 reserved GPI19 GPI11 GPI3 reserved GPI18 GPI10 GPI2 fifo_ovf GPI17 GPI9 GPI1 fifo_ind GPI16 GPI8 GPI0 *1 Do not write more than 0x7F in KS_RATE ※ Do not write “1” in the reserved resisters. The write commands to 13h-18h addresses’ registers are ignored. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 14/24 2011.01 - Rev.A BU1852GUW Table2 Register function Symbol RESET Address 00h Description Software reset. All registers are initialized by writing "1". This register value is returned to "0" automatically. Exceptionally, GPIn register is not initialized. “1” : External clock from XI is used. “0” : Internal CR oscillator is used. Key scan rate control When set to “1”, port is used as COLx for key scan. When set to “0”, it is used as GPIO port. When set to “1”, port is used as ROWy for key scan. When set to “0”, it is used as GPIO port. Technical Note CLKSEL 01h KS_RATE 02h KS_Cx 03h-04h KS_Ry 05h IODn 06h-08h GPIOn’s IO direction. When set to “1”, GPIOn direction is output. When set to “0”, GPIOn direction is input. Interrupt of GPIOn port is enabled by "1". It is masked by "0". INTENn 09h-0Bh GPOn 0Ch-0Eh Output value of GPIOn port. XPDn 0Fh-10h Pull-down of GPIOn port is on by "0" and off by "1". GPIOn should be input. XPUn 11h Pull-up of GPIOn port is on by "0" and off by "1". GPIOn should be input. “1” : interrupt filter ON (1us pulse rejection) “0” : interrupt filter OFF (bypass) Keycode that Host can read currently INTFLT 12h keycode 14h fifo_ind 15h When there are keycode data in FIFO, fifo_ind is set to “1”. “0” means fifo empty. fifo_ovf 15h When FIFO overflow happens, fifo_ovf is set to “1”. Initially “0” is stored. Input value of GPIOn port. Write command is ignored. When interrupt happens, these registers must be read. GPIn 16h-18h ※"n" is the number of GPIO[19:0] ports. “x” is the number of COL[11:0]. “y” is the number of ROW[7:0]. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 15/24 2011.01 - Rev.A BU1852GUW 5. Technical Note GPIO function GPIO configuration When some ports of COL[11:0] and ROW[7:0] are needed to be used as GPIO, TW must be “0”. Then, set the proper value in the appropriate registers through I2C. ROW[7:0] and COL[11:0] correspond to GPIO[7:0] and GPIO[19:8], respectively. By default, GPIO[19:0] ports are set to input(IODn=0) and Pull-up/down ON(XPUn/XPDn=0). (n is the number of GPIO[19:0] ports.) Refer to the following for the configuration of GPIO. Table3 GPIO configuration State of GPIO Input, Pull-up/down ON Input, Pull-up/down OFF Output, H drive Output, L drive Output, Hi-Z ※1 Register GPOn * * 1 0 0 IODn 0 0 1 1 0 XPDn/XPUn 0 1 * * 1 ※1 It is required to pull-up to more than VDD potential. How to deal with GPIO ports which are not using When set to output, GPIO port must be open. When set to input, don’t make GPIO port open. It must be forced by "0" or Pull-up/down on. Interrupt configuration The initial XINT output is Hi-Z, so it should be pull-up. When interrupt is generated, XINT port outputs L. By default, interrupt is masked with INTEN register "0". The bit to be used is made "1", and then the mask is released. In this case, IOD register should be "0"(input). Write to GPIO port After master sets the internal register address for write, the data is sent from MSB. After Acknowledge is returned, the value of each GPIO port will be changed. Write Configuration Pulse, which is trigger of changing registers, is generated at the timing of Acknowledge. SCL 1 2 3 4 5 6 7 8 9 SDA S X X X X X X X 0 Ack MSB Reg Address LSB Ack MSB Data1 (GPO[7:0]) LSB Ack P Start Condition Write Configuration Pulse GPIO[7:0] Write Acknowledge From Slave Acknowledge From Slave Stop Condition Data1 Valid tDV SCL 1 2 3 4 5 6 7 8 9 SDA S X X X X X X X 0 Ack MSB Reg Address LSB Ack MSB Data1 (GPO[7:0]) LSB Ack MSB WRSEL = Write Mode LSB Ack P Start Condition Write Configuration Pulse GPIO[7:0] Write Acknowledge From Slave Acknowledge From Slave Acknowledge From Slave Stop Condition Data1 Valid tDV Fig.15 Write to GPIO port www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 16/24 2011.01 - Rev.A BU1852GUW Technical Note Read from GPIO port After writing of the Slave address and R/W bits by master, reading GPIO port procedure begins. All ports’ status that is set to the input by IOD registers are taken into the GPI register when ACK is sent. SCL 1 2 3 4 5 6 7 8 9 SDA S X X X X X X X 1 Ack D1 [7] D1 [6] D1 [5] D1 [4] D1 [3] D1 [2] D1 [1] D1 [0] NA P Start Condition Read Acknowledge From Slave Stop Condition No Acknowledge From Master GPI[ 7:0] Reg D1 GPIO[ 7:0] D1 D2 Fig.16 Read from GPIO port Interrupt Valid/Reset When the GPIO interrupt is used, some of INTEN registers are required to be written to "1". When current GPIO port status becomes different from the value of the GPIn registers, XINT port is changed from "1" to "0". After reading GPI register, it will return to "1". When Master detects interrupt, Master must read all GPI registers that is set to input(IODn=0), even if XINT is changed while reading. It is because BU1852GUW does not latch the XINT status. Fig.13 shows one of the example of using only ROW[7:0] as GPI. In this case, Master reads only 18h register immediate after detecting XINT. XINT cannot distinguish whether just one port is different or multi ports are different from the previous value. Master is necessary to store the previous GPI register value and compare it with the current value after XINT is asserted. SCL 1 2 3 4 5 6 7 8 9 SDA S X X X X X X X 1 Ack MSB Data2 (GPI[7:0]) LSB NA P Start Condition GPIOn Data1 Read Data2 Acknowledge From Slave Stop Condition No Acknowledge From Master Data3 Data2 GPIn Reg Data1 Data2 XINT tIV tIR tIV tIR Fig.17 Interrupt Valid/Reset (Example : ROW[7:0] as GPI with interrupt) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 17/24 2011.01 - Rev.A BU1852GUW 6. Technical Note Key code Assignment 2 Table 4 shows the key code assignment. These key codes are sent through 3wire or I C corresponding to the pushed or released keys. Table4 Key codes ROW 0 M COL 0 B M COL 1 B M COL 2 B M COL 3 B M COL 4 B M COL 5 B M COL 6 B M COL 7 B M COL 8 B M COL 9 B M COL 10 B M COL 11 B 0 x8C 0x9 C 0xAC 0xBC 0xCC 0xDC 0xEC 0 xFC M : Make Key (the code when the key is pressed) B : Break Key (the code when the key is released) ROW 1 0x11 0x91 0x12 0x92 0x13 0x93 0x14 0x94 0x15 0x95 0x16 0x96 0x17 0x97 0x18 0x98 0x19 0x99 0x 1A 0x 9A 0x 1B 0x 9B 0x1 C ROW 2 0x21 0xA1 0x22 0xA2 0x23 0xA3 0x24 0xA4 0x25 0xA5 0x26 0xA6 0x27 0xA7 0x28 0xA8 0x29 0xA9 0x2A 0xAA 0x2B 0xAB 0 x2C ROW 3 0x31 0xB1 0x32 0xB2 0x33 0xB3 0x34 0xB4 0x35 0xB5 0x36 0xB6 0x37 0xB7 0x38 0xB8 0x39 0xB9 0x3A 0xBA 0x3B 0xBB 0x3C ROW 4 0x41 0xC1 0x42 0xC2 0x43 0xC3 0x44 0xC4 0x45 0xC5 0x46 0xC6 0x47 0xC7 0x48 0xC8 0x49 0xC9 0x4A 0xCA 0x4B 0xCB 0x4C ROW 5 0x51 0xD1 0x52 0xD2 0x53 0xD3 0x54 0xD4 0x55 0xD5 0x56 0xD6 0x57 0xD7 0x58 0xD8 0x59 0xD9 0x5 A 0xDA 0x5B 0xDB 0x5C ROW 6 0x 61 0xE1 0x 62 0xE2 0x 63 0xE3 0x 64 0xE4 0x 65 0xE5 0x 66 0xE6 0x 67 0xE7 0x 68 0xE8 0x 69 0xE9 0x6A 0xEA 0x6B 0xEB 0x6 C ROW 7 0x71 0xF1 0x72 0xF2 0x73 0xF3 0x74 0xF4 0x75 0xF5 0x76 0xF6 0x77 0xF7 0x78 0xF8 0x79 0xF9 0x7 A 0xFA 0x7B 0xFB 0x7C 0x01 0x81 0x02 0x82 0x03 0x83 0x04 0x84 0x05 0x85 0x06 0x86 0x07 0x87 0x08 0x88 0x09 0x89 0x0A 0x8A 0x0B 0x8B 0 x0C www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 18/24 2011.01 - Rev.A BU1852GUW 7. Technical Note Ghost Key Rejection Ghost key is an inevitable phenomenon as long as key-switch matrices are used. When three switches located at the corners of a certain matrix rectangle are pressed simultaneously, the switch that is located at the last corner of the rectangle (the ghost key) also appears to be pressed, even though the last key is not pressed. This occurs because the ghost key switch is electrically shorted by the combination of the other three switches (Fig.18). Because the key appears to be pressed electrically, it is impossible to distinguish which key is the ghost key and which key is pressed. The BU1852GUW solves the ghost key problem to use the simple method. If BU1852GUW detects any three-key combination that generates a fourth ghost key, and BU1852GUW does not report anything, indicating the ghost keys are ignored. This means that many combinations of three keys are also ignored when pressed at the same time. Applications requiring three-key combinations (such as ) must ensure that the three keys are not wired in positions that define the vertices of a rectangle (Fig. 19). There is no limit on the number of keys that can be pressed simultaneously as long as the keys do not generate ghost key events. PRESSED KEY EVENT GHOST-KEY EVENT KEY-SWITCH MATRIX Fig.18 Ghost key phenomenon EXAMPLES OF VALID THREE-KEY COMBINATIONS KEY-SWITCH MATRIX KEY-SWITCH MATRIX Fig.19 Valid three key combinations www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 19/24 2011.01 - Rev.A BU1852GUW 8. Recommended flow 2 Fig.20 shows the recommended flow when TW=0(I C protocol is selected). Technical Note Sequence Related registers power on Reset release clock select determine key scan rate assign each port to key scan and GPIO detemine GPIO direction GPI interrupt setting Control GPO port or Monitor “XINT” 01h : CLKSEL 02h : KS_RATE 03h-04h : KS_C[11:0] 05h : KS_R[7:0] 06h-08h : IOD[19:0] 09h-0Bh : INTEN[19:0] 12h : INTFLT 0Ch-0Eh : GPO[19:0] 14h-18h : Read registers Fig.20 Recommended flow and related registers Forbidden operation: 2 --- Dynamic change of TW (I C/3wire protocol should be fixed) --- Dynamic assignment change of keyscan and GPIO (should be determined initially) --- Dynamic change of keyscan rate (should be determined initially) --- Dynamic change of CLKSEL (should be determined initially) www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 20/24 2011.01 - Rev.A BU1852GUW ●Application circuit example 1.8V 0.1uF 0.1uF PORENB TESTM[1:0] VDDIO VSS VDD TW ADR 3.0V Technical Note 1.8V XRST XI VDD COL11 COL10 COL9 COL8 GPO from/to 3.0V device GPI INT XINT COL7 COL6 MPU SCL SDA VSS SCL SDA COL5 COL4 COL3 BU1852GUW COL2 COL1 COL0 ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 to Other I2C Devices Fig.21 Application circuit example www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 21/24 2011.01 - Rev.A BU1852GUW ●Appendix 1. 3wire Interface (TW=”1”) XINT Technical Note SCL invalid Start bit Bit7 Bit6 Bit5 Bit0 SDA sent by host device sent by BU1852 Fig.22 3wire protocol Figure 22 shows the original 3wire protocol of BU1852GUW. When this 3wire protocol is used, TW must be “1”. Note that this 3wire interface is completely different from I2C and other standard bus interface. Procedure 1. When BU1852GUW detects key events, XINT interrupt is generated to host with driving Low. 2. After the host detects XINT interrupt, the host is supposed to send start bit. 3. After BU1852GUW detects start bit, the 8bit data (key code) transmission on SDA will start synchronized with the rising edge of SCL clock signal, which is sent from the host. 4. 8 bit data are followed by “0” (9th bit is always “0”), and then BU1852GUW drives High on XINT line. See also section “3wire interface AC characteristics”. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 22/24 2011.01 - Rev.A BU1852GUW 2. 3wire Interface AC characteristics State START BIT 7 BIT 6 BIT 0 "0 " Technical Note t TWS U ;STA XINT t TWL OW ; CLK t TWLOW t TWH IGH ; CLK ;INT t TWHD 1 / f TWS CLK ; INTE SCL SDA t TWH D ; STA t TWH D ;DAT Fig.23 3wire interface AC timing VDD=1.8V, VDDIO=1.8V,Topr=25℃,TW=VDD Parameter SCL Clock Frequency START Condition Setup Time START Condition Hold Time SCL Low Time SCL High Time Data Hold Time XINT End Hold XINT Low Time Symbol fTWSCLK tTWSU;STA tTWHD;STA tTWLOW;CLK tTWHIGH;CLK tTWHD;DAT tTWHD;INTE tTWLOW;INT Limits Min. 0.030 20 23 23 0.1 1.35 500 Typ. 800 Max. 21.5 500 1.0 10.2 1350 Unit kHz ms µs µs µs µs µs ms Conditions www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 23/24 2011.01 - Rev.A BU1852GUW ●Ordering part number Technical Note B U 1 Part No. 8 5 2 G U W - E 2 Part No. Package GUW: VBGA035W040 Packaging and forming specification E2: Embossed tape and reel VBGA035W040 1PIN MARK 4.0 ± 0.1 Tape 0.9MAX. 4.0 ± 0.1 Embossed carrier tape (with dry pack) 2500pcs E2 The direction is the 1pin of product is at the upper left when you hold Quantity Direction of feed S 0.75 ± 0.1 35- φ 0.295± 0.05 φ 0.05 M S AB A P=0.5×5 0.5 B F E D C B A 123456 P=0.5×5 0.75 ± 0.1 0.08 S 0.10 ( reel on the left hand and you pull out the tape on the right hand ) 1pin Direction of feed (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. 24/24 2011.01 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. 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If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2011 ROHM Co., Ltd. All rights reserved. R1120A