BU2661FV

Audio ICs Low-voltage RDS / RBDS decoder BU2661FV The BU2661FV is a RDS / RBDS decoder that employs a digital PLL and has a built-in anti-aliasing filter and an eightstage BPF (switched-capacitor filter). It can operate at a low-voltage power supply (from 2.7V). Linear CMOS circuitry is used for low power consumption. FApplications RDS / RBDS compatible FM receivers, stereo systems and FM pagers. FFeatures 1) Low operating voltage (Min 2.7V). 2) Low current (Min 1.8mA). 3) Anti-aliasing filter. 4) 57kHz bandpass filter. 5) DSB demodulation (digital PLL). 6) Quality indication output for demodulated data. FAbsolute maximum ratings (Ta = 25_C) FRecommended operating conditions (Ta = 25_C) 914 Audio ICs FBlock diagram BU2661FV 915 Audio ICs FPin descriptions BU2661FV 916 Audio ICs FInput / output circuits BU2661FV 917 Audio ICs FElectrical characteristics (unless otherwise noted, Ta = 25_C, VDD = 3.0V, VSS = 0.0V) BU2661FV 918 Audio ICs FCircuit operation Output data timing BU2661FV The clock (RCLK) frequency is 1187.5Hz. Depending on the state of the internal PLL clock, the data (RDATA) is replaced in synchronous with either the rising or falling edge of the clock. To read the data, you may choose either the rising or falling edge of the clock as the reference. The data is valid for 416.7µs. after the reference clock edge. QUAL pin operation: Indicates the quality of the demodulated data. (1) Good data: HI (2) Poor data: LO (3) No signal: LO (4) Noise input: HI / LO (flutters) ARI pin operation: ARI / RDS distinction (1) ARI: HI (2) RDS)ARI: HI (3) RDS: LO (4) No signal: unstable (5) Noise input: unstable RESET input pin: Resets the digital circuit. Connect to ground or leave open during operation. FExternal dimensions (Units: mm) 919