BU99901GUZ-W

High Reliability Serial EEPROMs WL-CSP EEPROM family I2C BUS BU99901GUZ-W ●Description 2 BU99901GUZ-W series is a serial EEPROM of I C BUS interface method. ●Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) 2) Other devices than EEPROM can be connected to the same port, saving microcontroller port. 3) 1.7～3.6V single power source action most suitable for battery use. 4) FAST MODE 400kHz at 1.7～3.6V 5) Page write mode useful for initial value write at factory shipment. 6) Auto erase and auto end function at data rewrite. 7) Low current consumption At write operation (3.3V) : 0.6mA (Typ.) At read operation (3.6V) : 0.6mA (Typ.) At standby operation (3.6V) : 0.1µA (Typ.) 8) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage 9) Compact package 10) Data rewrite up to 100,000 times 11) Data kept for 40 years 12) Noise filter built in SCL / SDA terminal 13) Shipment data all address FFh ●Page write Product number Number of pages ●Absolute maximum ratings (Ta=25℃) Parameter symbol Impressed voltage VCC Permissible dissipation Storage temperature range Action temperature range Terminal voltage *1 *2 No.10001EAT15 BU99901GUZ-W 32Byte Ratings -0.3～+6.5 220 *1 -65～+125 -40～+85 -0.3～Vcc+1.0 *2 Unit V mW ℃ ℃ V Pd Tstg Topr － When using at Ta=25℃ or higher, 2.2mW to be reduced per 1℃ The Max value of Terminal Voltage is not over 6.5V. ●Memory cell characteristics (Ta=25℃, Vcc=1.7～3.6V) Limits Parameter Min. Typ. Number of data rewrite times *1 1,000,000 － Data hold years *1 *1 Max. － － Unit Times Years 40 － Not 100% TESTED ●Recommended operating conditions Parameter Write Power source voltage Read Input voltage Symbol Vcc VIN Ratings 2.7～3.3 1.7～3.6 0～Vcc Unit V V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/16 2010.09 - Rev.A BU99901GUZ-W ●Electrical characteristics (Unless otherwise specified Ta=-40～85℃､VCC=1.7～3.6V) Limits Parameter Symbol Unit Min Typ. Max. "H" Input Voltage1 "L" Input Voltage1 "H" Input Voltage2 "L" Input Voltage2 "H" Input Voltage3 "L" Input Voltage3 "L" Output Voltage1 "L" Output Voltage2 Input Leakage Current Pull Up Resistance Output Leakage Current Current consumption at action Standby Current VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOL1 VOL2 ILI ILI2 ILO ICC1 ICC2 ISB 0.7Vcc -0.3 0.8Vcc -0.3 0.9Vcc -0.3 － － -1 6 -1 － － － － － － － － － － － － － Vcc+1.0 0.3Vcc Vcc+1.0 0.2Vcc Vcc+1.0 0.1Vcc 0.4 0.2 1 14 1 4.1 mA 1.7 2.0 µA V V V V V V V V µA kΩ µA Technical Note Condition 2.5V≦Vcc≦3.6V 2.5V≦Vcc≦3.6V 1.8V≦Vcc＜2.5V 1.8V≦Vcc＜2.5V 1.7V≦Vcc＜1.8V 1.7V≦Vcc＜1.8V IOL=3.0mA , 2.5V≦Vcc≦3.6V (SDA) IOL=0.7mA , 1.7V≦Vcc＜2.5V (SDA) VIN=0～Vcc (WP, TEST) (SCL,SDA) VOUT=0～Vcc (SDA) Vcc=3.3V , fSCL =400kHz, tWR=5ms Byte Write, Page Write Vcc=3.6V , fSCL =400kHz Random read, Current read, Sequential read Vcc=3.6V, SDA ,SCL=Vcc, WP=GND ○Radiation resistance design is not made. ●Action timing characteristics(Unless otherwise specified Ta=-40～85℃､VCC=1.7～3.6V) Parameter SCL Frequency Data clock "High" time Data clock "Low" time SDA, SCL rise time SDA, SCL fall time *1 *1 Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP FAST-MODE 2.5V≦Vcc≦3.6V Min. － 0.6 1.2 － － 0.6 0.6 0 100 0.1 0.1 0.6 1.2 － － 0 0.1 1.0 Typ. － － － － － － － － － － － － － － － － － － Max. 400 － － 0.3 0.3 － － － － 0.9 － － － 5 0.1 － － － STANDARD-MODE 1.7V≦Vcc≦3.6V Min. － 4.0 4.7 － － 4.0 4.7 0 250 0.2 0.2 4.7 4.7 － － 0 0.1 1.0 Typ. － － － － － － － － － － － － － － － － － － Max. 100 － － 1.0 0.3 － － － － 3.5 － － － 5 0.1 － － － Unit kHz µs µs µs µs µs µs ns ns µs µs µs µs ms µs ns µs µs Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition data setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA,SCL terminal) WP hold time WP setup time WP valid time *1 Not 100% TESTED ●FAST-MODE and STANDARD-MODE FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out, therefore, at Vcc=2.5V～5.5V , 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/16 2010.09 - Rev.A BU99901GUZ-W ●Sync data input/output timing tR SCL tF tHIGH Technical Note SCL tHD :STA tSU :DAT tLOW tHD :DAT (Input) SDA DATA(1) SDA D1 D0 ACK DATA(n) ACK tWR tBUF SDA tPD tDH (Output) WP Stop condition ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL tSU：WP ｔHD：WP Fig.1-(a) Sync data input / output timing Fig.1-(d) WP timing at write execution SCL tSU:STA SDA SCL tHD:STA tSU:STO DATA(1) SDA D1 D0 ACK DATA(n) ACK tHIGH:WP tWR tWR START BIT STOP BIT WP Fig.1-(b) Start - stop bit ○At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP= 'LOW'. ○By setting WP "HIGH" in the area, write can be cancelled. When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. D0 WRITE DATA(n) STOP CONDITION ACK SCL SDA tWR START CONDITION Fig.1-(e) WP timing at write cancels Fig.1-(c) Write cycle timing ●Block diagram 32Kbit EEPROM array 8bit Vcc 12bit A dddress decoder S lave - word address register 12bit Data register WP START STOP TEST Control circuit ACK SCL GND High voltage generating circuit TEST terminal,please connect GND Power source voltage detection SDA Fig.2 Block diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/16 2010.09 - Rev.A BU99901GUZ-W ●Pin assignment and function Technical Note B B1 TEST B2 GND A2 SCL 2 B3 VDD A3 WP 3 A A1 SDA 1 Fig.3 BU99901GUZ-W(bottom view) Land No. B3 B2 B1 A3 A2 A1 Terminal name VDD GND TEST WP SCL SDA Input / output － － Unit Power Supply Reference voltage of all input / output TEST terminal, Connect GND Write protect terminal Serial clock input Slave and word address, Serial data input serial data output Input Input Input Input /output ●Characteristic data (The following values are Typ. ones.) 6 5 4 VIH1,2(V) 3 2 1 0 0 1 2 3 Vcc(V) 4 5 6 6 1 Ta=-40℃ Ta=25℃ Ta=85℃ VIL1,2(V) 5 4 3 2 1 0 0 Ta=-40℃ Ta=25℃ Ta=85℃ VOL1(V) 0.8 0.6 0.4 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC SPEC 0.2 SPEC 0 1 2 3 Vcc(V) 4 5 6 0 1 2 3 IOL1(mA) 4 5 6 Fig.4　'H' input voltage　VIH1,2 (SCL,SDA,WP) 1 0.8 0.6 0.4 0.2 0 0 1 2 3 IOL2(mA) 4 5 6 1.2 Fig.5　'L' input voltage　VIL (SCL,SDA,WP) 1.2 Fig.6 'L' output voltage VOL-IOL(Vcc=1.7V) SPEC 1 0.8 ILO(uA) SPEC 1 VOL2(V) ILI(uA) Ta=-40℃ Ta=25℃ Ta=85℃ 0.8 SPEC 0.6 0.4 0.2 0 0 Ta=-40℃ Ta=25℃ Ta=85℃ 0.6 0.4 0.2 0 Ta=-40℃ Ta=25℃ Ta=85℃ 1 2 3 Vcc(V) 4 5 6 0 1 2 3 Vcc(V) 4 5 6 Fig.7　'L' output voltage VOL-IOL(Vcc=2.5V) Fig.8　Input leak current ILI (SCL,WP) Fig.9　Output leak current www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/16 2010.09 - Rev.A BU99901GUZ-W ●Characteristic data (The following values are Typ. ones.) 4.5 4 3.5 3 ICC1(mA) 2.5 2 1.5 1 0.5 0 0 1 2 3 Vcc(V) 4 5 6 -0.5 0 1 2 3 Vcc(V) 4 5 6 0 2 Technical Note 3.5 3 SPEC ICC2(mA) 1.5 SPEC ICC1(mA) SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 2.5 2 1.5 1 0.5 0 0 1 2 3 Vcc(V) 4 5 6 Ta=-40℃ Ta=25℃ Ta=85℃ 1 0.5 Ta=-40℃ Ta=25℃ Ta=85℃ Fig.10　Current consumption at WRITE operation Icc1 (fscl=400kHz) 0.6 Fig.11 Current consumption at READ operation Iｃｃ2 (fscl=400kHz) 2.5 Fig.12　Current consumption at WRITE operation Icc1 (fscl=100kHz) SPEC 0.5 0.4 ICC2(mA) 0.3 0.2 0.1 0 0 1 2 3 Vcc(V) 4 5 6 2 SPEC 10000 1000 ISB(uA) fSCL（ｋHZ） Ta=-40℃ Ta=25℃ Ta=85℃ 1.5 1 0.5 0 0 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 100 10 1 0.1 0 1 2 3 Vcc(V) 4 5 6 Ta=-40℃ Ta=25℃ Ta=85℃ 1 2 3 Vcc(V) 4 5 6 Fig.13 Current consumption at READ operation　Iｃｃ2 （fscl=100kHz) 5 5 Fig.14　Stanby operation ISB 5 Fig.15　SCL frequency fSCL SPEC 4 tHIGH(us) 4 SPEC SPEC Ta=-40℃ Ta=25℃ Ta=85℃ tHD : STA(us) 4 3 2 1 0 0 1 2 3 Vcc(V) 4 5 6 2 1 0 0 Ta=-40℃ Ta=25℃ Ta=85℃ tLOW(us) 3 3 2 1 0 Ta=-40℃ Ta=25℃ Ta=85℃ 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 0 1 2 3 Vcc（V） 4 5 6 Fig.16 Data clock High Period tHIGH Fig.17 Data clock Low Period　tLOW Fig.18 Start Condition Hold Time tHD : STA 50 5.9 4.9 tSU:STA(us) 3.9 2.9 1.9 0.9 -0.1 0 1 2 3 Vcc(V) 4 5 6 tHD:DAT(HIGH) (ns) 50 SPEC 0 SPEC 0 tHD :DAT(ns) -50 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ -50 -100 -150 -200 0 1 2 3 Vcc(V) Ta=-40℃ Ta=25℃ Ta=85℃ -100 -150 -200 0 Ta=-40℃ Ta=25℃ Ta=85℃ 4 5 6 1 2 3 Vcc(V) 4 5 6 Fig.19　Start Condition Setup Time 　tSU : STA 300 200 Fig.20　Input Data Hold Time tHD : DAT（HIGH） 300 200 tSU : DAT(LOW) (ns) 4 Fig.21　Input Data Hold Time ｔHD : DAT(LOW） tSU: DAT(HIGH) (ns) SPEC 100 0 -100 -200 0 1 2 3 Vcc(V) 4 5 6 SPEC tPD0(us) 100 0 -100 -200 0 1 2 3 Vcc(V) 4 5 6 3 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 2 Ta=-40℃ Ta=25℃ Ta=85℃ Ta=-40℃ Ta=25℃ Ta=85℃ 1 0 0 1 2 3 Vcc(V) 4 5 6 Fig.22　Input Data Setup Time ｔSU: DAT(HIGH) Fig.23　Input Data Setup Time tSU : DAT(LOW) Fig.24 Data output delay time tPD0 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/16 2010.09 - Rev.A BU99901GUZ-W ●Characteristic data (The following values are Typ. ones.) 4 5 6 Technical Note 3 tPD1(us) 2 SPEC tBUF(us) 3 2 1 0 tWR(ms) Ta=-40℃ Ta=25℃ Ta=85℃ 4 SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 5 4 3 2 1 0 SPEC 1 Ta=-40℃ Ta=25℃ Ta=85℃ 0 1 2 3 Vcc(V) 4 5 6 0 0 1 2 3 Vcc(V) 4 5 6 0 1 2 3 Vcc(V) 4 5 6 Fig.25 Data output delay time ｔPD1 1 0.8 tI(SCL H) (us) 0.6 0.4 0.2 0 0 1 2 3 Vcc(V) 4 5 6 Fig.26 BUS open time before transmission　ｔBUF 0.6 0.6 Fig.27 Internal writing cycle time　ｔWR SPEC Ta=-40℃ Ta=25℃ Ta=85℃ tI(SCL L) (us) 0.5 0.4 0.3 0.2 Ta=-40℃ Ta=25℃ Ta=85℃ tI(SDA H) (us) 0.5 0.4 0.3 0.2 Ta=-40℃ Ta=25℃ Ta=85℃ SPEC 0.1 0 0 1 2 3 Vcc(V) 4 5 6 SPEC 0.1 0 0 2 Vcc(V) 4 6 Fig.28 Noise reduction efection time tI（SCL H） Fig.29　Noise reduction efection time　tI（SCL L） Fig.30　Noise reduction efection time　ｔI（SDA H） 0.6 0.5 tI(SAD L) (us) tSU : WP(us) 0.4 0.3 0.2 0.1 0 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 1 2 3 Vcc(V) 4 5 6 1.2 SPEC 1 tHIGH : WP(us) SPEC Ta=-40℃ Ta=25℃ Ta=85℃ SPEC Ta=-40℃ Ta=25℃ Ta=85℃ 0.8 0.6 0.4 0.2 0 0 1 2 3 Vcc(V) 4 5 6 Ta=-40℃ Ta=25℃ Ta=85℃ 0 1 2 3 Vcc(V) 4 5 6 Fig.31 Noise reduction efection time tI（SDA L） Fig.32 WP setup time tSU : WP Fig.33 WP efective time tHIGH : WP www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●I2C BUS communication 2 ○I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is controlled by addresses peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”, and the device that receives data is called “receiver”. SDA SCL 1-7 S START ADDRESS condition 8 9 1-7 8 9 1-7 8 9 P STOP condition R/W ACK DATA ACK DATA ACK Fig.34 Data transfer timing ○Start condition (start bit recognition) ・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. ・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. ○Stop condition (stop bit recognition) ・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' ○Acknowledge (ACK) signal ・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. ・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. ・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data). ・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. ・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. ○Device addressing ・Output slave address after start condition from master. ・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. ・The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action, and is as shown below. Setting R / W to 0 --- write (setting 0 to word address setting of random read) Setting R / W to 1 --- read Type BU99901GUZ-W 1 1 1 Slave address 0 0 0 0 R/W www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●Write Command ○Write cycle ・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 32 arbitrary bytes can be written. S T A R T SDA LINE W R I T E S T O P D0 A C K SLAVE ADDRESS 1010000 1st WORD ADDRESS ＊＊＊ WA 11 2nd WORD ADDRESS WA 0 DATA D7 A C K RA /C WK A C K Fig.35 Byte write cycle S T A R T SDA L IN E W R I T E S LA V E ADDRESS 1010000 1 st W O R D A D D R E S S (n) ＊＊ ＊＊ WA 11 2n d W O R D A D D R E S S (n ) WA 0 D A TA (n ) D7 A C K D0 A C K D A T A (n+ 31) D0 A C K S T O P RA /C WK A C K Fig.36 Page write cycle ・Data is written to the address designated by word address (n-th address). ・By issuing stop bit after 8bit data input, write to memory cell inside starts. ・When internal write is started, command is not accepted for tWR (5ms at maximum). ・By page write cycle, the following can be written in bulk: Up to 32 bytes. (Refer to "Internal address increment of "Notes on page write cycle" in P9/16.) ・As for page write command of BU99901GUZ-W, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. ・As for page write cycle of BU99901GUZ-W , after the significant 7 bits of word address, are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/16 2010.09 - Rev.A BU99901GUZ-W ○Notes on write cycle continuous input A t STOP (stop bit) write starts. Technical Note S T A R T SDA LINE SLAVE ADDRESS W R I T E WORD ADDRESS (n) DATA (n) DATA (n+31) S T O P S T A R T 1 0 1 0 P2 P1P0 WA 7 WA 0 D7 D0 D0 10 10 RA /C WK A C K A C K A C K Next command Fig.37 Page write cycle tWR (maximum :5ms) Command is not ac cepted for this period. ○Notes on page write cycle List of numbers of page write Number of pages Product number 32Byte BU99901GUZ-W ○Internal address increment Page write mode WA11 ----- WA5 WA4 WA3 WA2 WA1 WA0 0 ----- 0 0 0 0 0 0 0 ----- 0 0 0 0 0 1 0 ----- 0 0 0 0 1 0 ----------------- increment The above numbers are maximum bytes for respective types. Any bytes below these can be written. IEh In the case of BU99901GUZ-W, 1 page = 32bytes, but the page write cycle write time is 5ms at maximum for 32byte bulk write. It does not stand 5ms at maximum × 32byte = 160ms(Max.). 0 0 0 ------------- 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up For example, when it is started from address 1Eh, therefore, increment is made as below, 1Eh→1Fh→00h→01h･･･, which please note. * 1Eh･･･16 in hexadecimal, therefore, 00011110 becomes a binary number. ○Write protect (WP) terminal ・Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●Read Command ○Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession. S T A R T SDA LINE W R I T E S T A R T R E A D S T O P SLAVE ADDRESS 1st WORD ADDRESS(n) 2nd WORD ADDRESS(n) WA 0 SLAVE ADDRESS DATA(n ) It is necessary to input 'H' to the last ACK. 10 10 0 0 0 ＊ ＊ ＊ ＊W A 11 10 1 0 A 2 A1A0 D7 D0 RA /C WK A C K A C K RA /C WK A C K Fig.38 Random read cycle S T A R T SDA L IN E R E A D D7 RA /C WK S T O P D0 A C K S LA V E ADDRESS 10100 00 D A TA (n ) It is necessary to input 'H' to the last ACK. Fig. 39 Current read cycle S T A R T SDA LINE R E A D S T O P D0 A C K SLAVE ADDRESS DATA (n) DATA(n+x ) 10 1 00 00 RA /C WK D7 D0 A C K A C K D7 Fig.40 Sequential read cycle (in the case of current read cycle) ・In random read cycle, data of designated word address can be read. ・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. ・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address data can be read in succession. ・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'. ・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. ・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.41(a), Fig.41(b), Fig.41(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock×14 Start×2 SCL SDA 1 2 13 14 Normal command Normal command Fig.41-(a) The case of 14 Dummy clock + START + START+ command input Start Dummy clock×9 Start SCL SDA 1 2 8 9 Normal command Normal command Fig.41-(b) The case of START+9 Dummy clock + START + command input Start×9 SCL SDA 1 2 3 7 8 9 Normal command Normal command Fig.41-(c) START × 9 + command input * Start command from START input. ●Acknowledge polling During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R / W = 0, when to carry out current read cycle after write, slave address R / W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data so forth. During internal write, ACK = HIGH is sent back. S T O P S T Slave A address R T A C K H S T Slave A R address T A C K H First write command S T A R T Write command … tWR Second write command S T Slave A R address T A C K H S T Slave A R address T A C K L A C K L A C K L S T O P … Word address Data tWR After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession. Fig.42 Case to continuously write by acknowledge polling www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.43.) After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum). ・Rise of D0 taken clock SCL SDA D1 D0 SCL ・Rise of SDA ACK SDA Enlarged view S T Slave A R address T A A A C Word C D7 D6 D5 D4 D3 D2 D1 D0 C K address K K L L L WP cancel invalid area D0 ACK Enlarged view AS CT KO LP tWR SDA Data WP cancel valid area Write forced end WP Data is not written. Data not guaranteed Fig.43 WP valid timing ●Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig.44.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Fig.44 Case of cancel by start, stop condition during slave address input www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/16 2010.09 - Rev.A BU99901GUZ-W Technical Note ●Cautions on microcontroller connection ○Rs 2 In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used. ACK SCL RS SDA 'H' output of microcontroller 'L' output of EEPROM Microcontroller EEPROM Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. Fig.45 I/O circuit diagram ○Maximum value of Rs The maximum value of Rs is determined by following relations. (1) Fig.46 Input/output collision timing SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2) The bus electric potential ○ to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc. VCC A RS IOL RPU=10ｋΩ VOL (VCC－V OL)×RS RPU+RS ∴ RS ≦ + V OL+0.1VCC≦VIL VIL－ VOL－0.1VCC 1.1VCC－V IL × RPU Example） When V CC=3V,　V IL =0.3VCC,　VOL=0.4V, 　RPU=10kΩ , VIL Microcontroller Bus line capacity CBUS EEPROM from(2), RS ≦ 0.3×3－0.4－ 0.1×3 × 1.1×3－0.3×3 10×103 Fig.47 I/O circuit diagram ≦ 0.835［kΩ］ ○Maximum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. RPU=10Ω RS Over current I 'H' output 'L' output VCC ≦ RS ∴ RS ≧ I VCC I Example）When VCC=3V, I=10mA RS ≧ 3 -3 10×10 Microcontroller EEPROM ≧ 300［Ω］ Fig.48 I/O circuit diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/16 2010.09 - Rev.A BU99901GUZ-W ●I2C BUS input / output circuit ○Input (SCL, SDA) Technical Note Fig.49 Input pin circuit diagram ○Input/Output (SDA) VDD Fig.50 Input /output pin circuit diagram ●Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following condition at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. Recommended conditions of tR,tOFF,Vbot tR tOFF Vbot 10ms or below tOFF 0 Vbot VCC tR 10ms or longer 10ms or longer 0.3V or below 0.2V or below 100ms or below Fig.51 Rise waveform diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on . →Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. VCC SCL tLOW SDA A ft er V cc bec omes st able Af t er Vcc becom es stab le tDH tSU:DAT tSU:DAT Fig.52 When SCL='H' and SDA='L' Fig.53 When SCL='H' and SDA='L' b) In the case when the above condition 2 cannot be observed. →After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. →Carry out a), and then carry out b). www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/16 2010.09 - Rev.A BU99901GUZ-W ●Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Technical Note ●Vcc noise countermeasures ○Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. ●Notes for use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/16 2010.09 - Rev.A BU99901GUZ-W ●Ordering part number Technical Note B U 9 9 9 0 1 G U Z-W W-CELL E 2 Part No. Part No. Package GUZ: VCSP30L1 Packaging and forming specification E2: Embossed tape and reel VCSP30L1(BU99901GUZ-W) 1PIN MARK Tape 1.76±0.05 1.05±0.05 Embossed carrier tape (heat sealing method) 3000pcs E2 The direction is the 1pin of product is at the upper left when you hold Quantity 0.08±0.05 0.35MAX Direction of feed S ( reel on the left hand and you pull out the tape on the right hand ) 6-φ0.25±0.05 0.05 A B BB A 1 A 0.5 0.275±0.05 0.06 S 0.38±0.05 P=0.5×2 2 3 1pin (Unit : mm) Direction of feed Reel ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/16 2010.09 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A