Multi line sensor heads for Wide format Scanner
LSH1208-BD70A
Multi line Sensor heads(MLS) corresponding to high speed scan and to reading wrinkles and fold lines due to 6 output channels and dual light source. Newly developed shield-structure sensor IC improved anti-noise characteristic. Applications High speed reading equipment (i.e. document scanners, wide format scanners devices). Features 1) High speed reading capability due to 6 analog output. 2) Newly developed shield-structure sensor IC shuts out external noise. Moreover, it reduces malfunction due to applying electro-static as represented by IEC61000-4-2. 3) Reduction of shade due to wrinkles and fold lines by adopting dual light source. Dimensions (Unit : mm)
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1/5
2009.12 - Rev.A
LSH1208-BD70A
Characteristics
Parameter Effective scanning width Primary scan dot density Total dot number Power supply voltage Reference voltage Scanning speed Clock frequency Maximum dynamic range Minimum dynamic range Dark output Operating temperature Symbol − − − VDD VREF SLT CLK VRMax VRMin. Vod − Typ. 216 1200 10368 3.3 0.8 Unit mm dpi dots V V ms / line MHz V V V °C
Data Sheet
0.125×3
8 0.5 0.25 VREF + 0.1 − 5 to 45
Pin assignments
Pin No. No.1 No.2 No.3 No.4 No.5 No.6 No.7 No.8 No.9 No.10 No.11 No.12 No.13 No.14 No.15 Signal GND Ao1 GND Ao2 GND Ao3 GND Ao4 GND Ao5 GND Ao6 GND VREF VDD Pin No. No.16 No.17 No.18 No.19 No.20 No.21 No.22 No.23 No.24 No.25 No.26 No.27 No.28 No.29 No.30 Signal CLK GND G-GND R-GND B-GND V-LED GND G-GND R-GND B-GND V-LED GND SP VDD MODE
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2/5
2009.12 - Rev.A
LSH1208-BD70A
Timing chart (a) CLK Timing Chart
1/fCLK twCLK twCLK
Data Sheet
CLK
50%
50% ts
SP
tSETUP tHOLD
90%
Ao
1 to 3 1pixel 2pixel
(b-1) Data Output Timing Chart (1200dpi mode) After turning on the SP pulse, the analog output starts from the setting up point of 83 clock pulse.
1200dpi mode
1
2
82
83
1810
1811
CLK SP AO
VREF output period
Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 : : : : : :
Analog output period (Not guaranteed) 1 to 64pixels − − − − −
Analog output period (Guaranteed) 65 to 1728pixels 1729 to 3456pixels 3457 to 5184pixels 5185 to 6912pixels 6913 to 8640pixels 8641 to 10304pixels
Analog output period (Not guaranteed) − − − − − 10305 to 10368pixels
VREF output period 1811clock to 1811clock to 1811clock to 1811clock to 1811clock to 1811clock to
1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock
Note)The CLK section area which is over the effective pixel numbers (Output blank part) cannot be used as the analog Output standard level.
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c ○ 2009 ROHM Co., Ltd. All rights reserved.
3/5
2009.12 - Rev.A
LSH1208-BD70A
(b-2) Data Output Timing Chart (600dpi mode) After turning on the SP pulse, the analog output starts from the setting up point of 83 clock pulse.
600dpi mode
Data Sheet
1
2
82
83
946
947
CLK SP AO
VREF output period
Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 : : : : : :
Analog output period (Not guaranteed) 1 to 32pixels − − − − −
Analog output period (Guaranteed) 33 to 864pixels 865 to 1728pixels 1729 to 2592pixels 2593 to 3456pixels 3457 to 4320pixels 4321 to 5152pixels
Analog output period (Not guaranteed) − − − − − 5153 to 5184pixels
VREF output period 947clock to 947clock to 947clock to 947clock to 947clock to 947clock to
1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock
Note)The CLK section area which is over the effective pixel numbers (Output blank part) cannot be used as the analog Output standard level.
(b-3) Data Output Timing Chart (300dpi mode) After turning on the SP pulse, the analog output starts from the setting up point of 83 clock pulse.
300dpi mode
1
2
82
83
514
515
CLK SP AO
VREF output period
Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 : : : : : :
Analog output period (Not guaranteed) 1 to 22pixels − − − − −
Analog output period (Guaranteed) 23 to 432pixels 433 to 864pixels 865 to 1296pixels 1297 to 1728pixels 1729 to 2160pixels 2161 to 2570pixels
Analog output period (Not guaranteed) − − − − − 2571 to 2592pixels
VREF output period 515clock to 515clock to 515clock to 515clock to 515clock to 515clock to
1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock 1 to 82clock
Note)The CLK section area which is over the effective pixel numbers (Output blank part) cannot be used as the analog Output standard level.
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c ○ 2009 ROHM Co., Ltd. All rights reserved.
4/5
2009.12 - Rev.A
LSH1208-BD70A
Inner circuit
VDD GND
1μF×6
Data Sheet
1
10368
SP
VDD
ANALOG MEMORY CIRCUIT
CLK
VREF MODE
1
Ao1 Ao2 Ao3 Ao4 Ao5 Ao6
10368
MODE VREF VLED VLED
RGND GGND BGND
RGND GGND BGND
Peripheral circuit
Multi Line Sensor Heads
2 3 4 1 28 29 30 27 6 8 10 12 14 16 22 20, 21 23 25 R3 R3 R2 B G R B G R R3 R3 R3 C3 C3 R3 VDD C2 SP CLK C1
5, 7, 9, 11, 13, 15, 17 19, 24, 26
18
C5
R1
LED GND
C4
LED GND VLED
C4
VLED
Ao6
Ao5
Ao4
Ao3
Ao2
Ao1
VREF
GND
MODE
R1=R2=100Ω, R3=100KΩ C1=C2=47μF C3=100μF, C4=0.1μF, C5=100pF
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5/5
2009.12 - Rev.A
Notice
Notes
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