ML610Q432REFBOARD

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL610Q431-03 Issue Date: Mar.23, 2015 ML610Q431/ML610Q432 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as real-time clock, synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.24 4µs (@4.096 MHz system clock) • Internal memory − Internal 64KBbyte Flash ROM (32K×16 bits) (including unusable 1KByte TEST area) − Internal 2KByte Data RAM (2048×8 bits), 1KByte Display Allocation RAM (1024 x 8bit) − Internal 192Byte RAM for display • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 23 maskable interrupt sources (Internal sources: 19, External sources: 4) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (16-bit configuration available) • 1 kHz timer − 10 Hz/1 Hz interrupt function 1/37 FEDL610Q431-03 ML610Q431/ML610Q432 • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 1 channel • Real time clock − Year, month, day, day of the week, hour, minute, and second registers − Automatic leap year correction − Regular interrupts (0.5 sec, 1 sec, 1 minute, 1 hour) − Alarm interrupt × 2 channels (day of the week, hour, minute; month, day hour, minute) • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@4MHｚ, 50kbps@500kHz) • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Successive approximation type A/D converter − 12-bit A/D converter − Input × 2 channels • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 6 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q431: 22 channels (including secondary functions) ML610Q432: 14 channels (including secondary functions) 2/37 FEDL610Q431-03 ML610Q431/ML610Q432 • LCD driver − Dot matrix can be supported. ML610Q431: 1024 dots max. (64 seg × 16 com) ML610Q432: 1536 dots max. (64 seg × 24 com) − 1/1 to 1/24 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − Bias voltage multiplying clock selectable (8 types) − Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable − Programmable display allocation function (available only when 1/1~1/8 duty is selected) • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − (“A”version(ML610Q431A/Q432A) don’t have the oscilation stop function.) − Reset by the watchdog timer (WDT) overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (500 kHz) Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock − Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to 70°C − Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V 3/37 FEDL610Q431-03 ML610Q431/ML610Q432 • Product name – Supported Function The line-up of the ML610Q431 and the ML610Q432 is below. - Chip (Die) ML610Q431-xxxWA ROM type Low-speed oscillation stop detect reset Operating temperature Product availability Flash ROM Yes -20°C to +70°C Yes ML610Q431A-xxxWA Flash ROM - -20°C to +70°C Yes ML610Q432-xxxWA Flash ROM Yes -20°C to +70°C Yes ML610Q432A-xxxWA Flash ROM - -20°C to +70°C Yes -144-pin plastic LQFP - ROM type Low-speed oscillation stop detect reset Operating temperature Product availability ML610Q431-xxxTC Flash ROM Yes -20°C to +70°C Yes ML610Q432-xxxTC Flash ROM Yes -20°C to +70°C Yes ML610Q432A-xxxTC Flash ROM - -20°C to +70°C Yes xxx: ROM code number (xxx of the blank product is NNN) Q: Flash ROM version A: Low-speed clock oscillation stop detection reset is disabled always (A version) WA: Chip (Die), TC: LQFP 4/37 FEDL610Q431-03 ML610Q431/ML610Q432 BLOCK DIAGRAM ML610Q431 Block Diagram Figure 1 show the block diagram of the ML610Q431. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RS0* RT0* RCT0* RCM* IN1* CS1* RS1* RT1* AIN0, AIN1 PC Instruction Register Program Memory (Flash) 64Kbyte BUS Controller INT 1 RAM 2048byte RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 1 INT 1 WDT TBC SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM 1kHzTC Capture ×2 RC-ADC ×2 INT 4 INT 1 12bit-ADC BLD PWM0* INT 1 INT 5 Display RAM 192Byte P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 RTC Display Allocation RAM 1024Byte MD0* NMI P00 to P03 P10 to P11 8bit Timer ×4 GPIO INT 3 VPP SSIO Melody AVDD AVSS VREF EA Data-bus LSCLK* OUTCLK* VDDL VDDX DSR/CSR SP XT0 XT1 OSC0* OSC1* ECSR1～3 LR ALU VDD VSS RESET_N ELR1～3 LCD Driver COM0 to COM15 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG63 C1, C2, C3, C4 Figure 1 ML610Q431 Block Diagram 5/37 FEDL610Q431-03 ML610Q431/ML610Q432 ML610Q432 Block Diagram Figure 2 show the block diagram of the ML610Q432. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RS0* RT0* RCT0* RCM* IN1* CS1* RS1* RT1* VREF EA PC Instruction Register Program Memory (Flash) 64Kbyte BUS Controller INT 1 RAM 2048byte RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 1 INT 1 WDT TBC SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM 1kHzTC Capture ×2 RC-ADC ×2 INT 4 INT 1 12bit-ADC BLD PWM0* INT 1 INT 5 MD0* NMI P00 to P03 P10 to P11 8bit Timer ×4 GPIO INT 3 VPP SSIO Melody AVDD AVSS AIN0, AIN1 DSR/CSR Data-bus LSCLK* OUTCLK* VDDL VDDX LR SP XT0 XT1 OSC0* OSC1* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 P20 to P22 P30 to P35 RTC Display Allocation RAM 1024Byte Display RAM 192Byte P40 to P47 LCD Driver COM0 to COM23 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG63 C1, C2, C3, C4 Figure 2 ML610Q432 Block Diagram 6/37 FEDL610Q431-03 ML610Q431/ML610Q432 PIN CONFIGURATION SEG46 (NC) (NC) SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 (NC) SEG16 (NC) SEG15 ML610Q431 LQFP144 Pin Layout 108pin 72pin 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109pin 73pin SEG47 VDD VPP SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 AVDD VREF AVSS AIN0 AIN1 L610Q431 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 144pin 1pin P03 (NC) P02 P01 P00 NMI VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P32 P33 P34 P35 VDDX (NC) XT0 (NC) XT1 VSS VDDL VDD P10 (NC) P11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 3 14 144 C4 C3 C2 C1 VL4 VL3 VL2 VL1 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM12 COM13 COM14 COM15 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 TEST 37pin 36pin (NC): No Connection Figure 3 ML610Q431 LQFP144 Pin Configuration 7/37 FEDL610Q431-03 ML610Q431/ML610Q432 SEG46 (NC) (NC) SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 (NC) SEG16 (NC) SEG15 ML610Q432 LQFP144 Pin Layout 108pin 72pin 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 109pin 73pin SEG47 VDD VPP SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 AVDD VREF AVSS AIN0 AIN1 L610Q432 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 144pin 1pin P03 (NC) P02 P01 P00 NMI VSS P20 P21 P22 P40 P41 RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P32 P33 P34 P35 VDDX (NC) XT0 (NC) XT1 VSS VDDL VDD P10 (NC) P11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 C4 C3 C2 C1 VL4 VL3 VL2 VL1 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 TEST 37pin 36pin (NC): No Connection Figure 4 ML610Q432 LQFP144 Pin Configuration 8/37 FEDL610Q431-03 ML610Q431/ML610Q432 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 ML610Q431 Chip Pin Layout & Dimension 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 SEG16 SEG15 C4 C3 C2 C1 VL4 VL3 VL2 VL1 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM12 COM13 COM14 COM15 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 TEST P11/OSC1 4.23mm P01 1 P00 2 NMI 3 Vss 4 P20 5 P21 6 P22 7 P40 8 P41 9 RESET_N 10 P42 11 P43 12 P44 13 P45 14 P46 15 P47 16 P30 17 P31 18 P32 19 P33 20 P34 21 P35 22 VDDX 23 XT0 24 XT1 25 Vss 26 VDDL 27 VDD 28 P10/OSC029 SEG46 SEG47 VDD VPP SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 AVDD VREF AVSS AIN0 AIN1 P03 P02 3.33mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 3.33 mm × 4.23 mm 136 pins 100 µm 80 µm × 80 µm 350 µm VSS level Figure 5 ML610Q431 Chip Layout & Dimension 9/37 FEDL610Q431-03 ML610Q431/ML610Q432 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 ML610Q432 Chip Pin Layout & Dimension 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 SEG16 SEG15 C4 C3 C2 C1 VL4 VL3 VL2 VL1 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 TEST P11/OSC1 4.23mm P01 1 P00 2 NMI 3 Vss 4 P20 5 P21 6 P22 7 P40 8 P41 9 RESET_N 10 P42 11 P43 12 P44 13 P45 14 P46 15 P47 16 P30 17 P31 18 P32 19 P33 20 P34 21 P35 22 VDDX 23 XT0 24 XT1 25 Vss 26 VDDL 27 VDD 28 P10/OSC029 SEG46 SEG47 VDD VPP SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 AVDD VREF AVSS AIN0 AIN1 P03 P02 3.33mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 3.33 mm × 4.23 mm 136 pins 100 µm 80 µm × 80 µm 350 µm VSS level Figure 6 ML610Q432 Chip Layout & Dimension 10/37 FEDL610Q431-03 ML610Q431/ML610Q432 ML610Q431 Pad Coordinates Table 1 ML610Q431 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) PAD No. 1 P01 -1400 -1978 51 SEG7 1528 200 2 P00 -1300 -1978 52 SEG8 1528 300 3 NMI -1200 -1978 53 SEG9 1528 4 VSS -1100 -1978 54 SEG10 5 P20 -1000 -1978 55 SEG11 6 P21 -900 -1978 56 7 P22 -800 -1978 8 P40 -700 9 P41 -600 10 RESET_N 11 Pad Name X (μm) Y (μm) 101 VPP -1528 1600 102 SEG48 -1528 1500 400 103 SEG49 -1528 1400 1528 500 104 SEG50 -1528 1300 1528 600 105 SEG51 -1528 1200 SEG12 1528 700 106 SEG52 -1528 1100 57 SEG13 1528 800 107 SEG53 -1528 1000 -1978 58 SEG14 1528 900 108 SEG54 -1528 900 -1978 59 VL1 1528 1000 109 SEG55 -1528 800 -500 -1978 60 VL2 1528 1100 110 SEG56 -1528 700 P42 -400 -1978 61 VL3 1528 1200 111 SEG57 -1528 600 12 P43 -300 -1978 62 VL4 1528 1300 112 SEG58 -1528 500 13 P44 -200 -1978 63 C1 1528 1400 113 SEG59 -1528 400 14 P45 -100 -1978 64 C2 1528 1500 114 SEG60 -1528 300 15 P46 0 -1978 65 C3 1528 1600 115 SEG61 -1528 200 16 P47 100 -1978 66 C4 1528 1700 116 SEG62 -1528 100 17 P30 200 -1978 67 SEG15 1528 1800 117 SEG63 -1528 0 18 P31 300 -1978 68 SEG16 1528 1900 118 COM0 -1528 -100 19 P32 400 -1978 69 SEG17 1400 1978 119 COM1 -1528 -200 20 P33 500 -1978 70 SEG18 1300 1978 120 COM2 -1528 -300 21 P34 600 -1978 71 SEG19 1200 1978 121 COM3 -1528 -400 22 P35 700 -1978 72 SEG20 1100 1978 122 COM4 -1528 -500 23 VDDX 800 -1978 73 SEG21 1000 1978 123 COM5 -1528 -600 24 XT0 900 -1978 74 SEG22 900 1978 124 COM6 -1528 -700 25 XT1 1000 -1978 75 SEG23 800 1978 125 COM7 -1528 -800 26 VSS 1100 -1978 76 SEG24 700 1978 126 COM8 -1528 -900 27 VDDL 1200 -1978 77 SEG25 600 1978 127 COM9 -1528 -1000 28 VDD 1300 -1978 78 SEG26 500 1978 128 COM10 -1528 -1100 29 P10 1400 -1978 79 SEG27 400 1978 129 COM11 -1528 -1200 30 P11 1528 -1900 80 SEG28 300 1978 130 AVDD -1528 -1300 31 TEST 1528 -1800 81 SEG29 200 1978 131 VREF -1528 -1400 32 PA0 1528 -1700 82 SEG30 100 1978 132 AVSS -1528 -1500 33 PA1 1528 -1600 83 SEG31 0 1978 133 AIN0 -1528 -1600 34 PA2 1528 -1500 84 SEG32 -100 1978 134 AIN1 -1528 -1700 35 PA3 1528 -1400 85 SEG33 -200 1978 135 P03 -1528 -1800 36 PA4 1528 -1300 86 SEG34 -300 1978 136 P02 -1528 -1900 37 PA5 1528 -1200 87 SEG35 -400 1978 38 PA6 1528 -1100 88 SEG36 -500 1978 39 PA7 1528 -1000 89 SEG37 -600 1978 40 COM15 1528 -900 90 SEG38 -700 1978 41 COM14 1528 -800 91 SEG39 -800 1978 42 COM13 1528 -700 92 SEG40 -900 1978 43 COM12 1528 -600 93 SEG41 -1000 1978 44 SEG0 1528 -500 94 SEG42 -1100 1978 45 SEG1 1528 -400 95 SEG43 -1200 1978 46 SEG2 1528 -300 96 SEG44 -1300 1978 47 SEG3 1528 -200 97 SEG45 -1400 1978 48 SEG4 1528 -100 98 SEG46 -1528 1900 49 SEG5 1528 0 99 SEG47 -1528 1800 50 SEG6 1528 100 100 VDD -1528 1700 11/37 FEDL610Q431-03 ML610Q431/ML610Q432 ML610Q432 Pad Coordinates Table 2 ML610Q432 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) 1 P01 -1400 -1978 51 SEG7 1528 200 2 P00 -1300 -1978 52 SEG8 1528 300 101 VPP -1528 1600 102 SEG48 -1528 3 NMI -1200 -1978 53 SEG9 1528 1500 400 103 SEG49 -1528 4 VSS -1100 -1978 54 SEG10 1400 1528 500 104 SEG50 -1528 5 P20 -1000 -1978 55 1300 SEG11 1528 600 105 SEG51 -1528 1200 6 P21 -900 -1978 7 P22 -800 -1978 56 SEG12 1528 700 106 SEG52 -1528 1100 57 SEG13 1528 800 107 SEG53 -1528 8 P40 -700 1000 -1978 58 SEG14 1528 900 108 SEG54 -1528 9 P41 900 -600 -1978 59 VL1 1528 1000 109 SEG55 -1528 10 800 RESET_N -500 -1978 60 VL2 1528 1100 110 SEG56 -1528 700 11 P42 -400 -1978 61 VL3 1528 1200 111 SEG57 -1528 600 12 P43 -300 -1978 62 VL4 1528 1300 112 SEG58 -1528 500 13 P44 -200 -1978 63 C1 1528 1400 113 SEG59 -1528 400 14 P45 -100 -1978 64 C2 1528 1500 114 SEG60 -1528 300 15 P46 0 -1978 65 C3 1528 1600 115 SEG61 -1528 200 16 P47 100 -1978 66 C4 1528 1700 116 SEG62 -1528 100 17 P30 200 -1978 67 SEG15 1528 1800 117 SEG63 -1528 0 18 P31 300 -1978 68 SEG16 1528 1900 118 COM0 -1528 -100 19 P32 400 -1978 69 SEG17 1400 1978 119 COM1 -1528 -200 20 P33 500 -1978 70 SEG18 1300 1978 120 COM2 -1528 -300 21 P34 600 -1978 71 SEG19 1200 1978 121 COM3 -1528 -400 22 P35 700 -1978 72 SEG20 1100 1978 122 COM4 -1528 -500 23 VDDX 800 -1978 73 SEG21 1000 1978 123 COM5 -1528 -600 24 XT0 900 -1978 74 SEG22 900 1978 124 COM6 -1528 -700 25 XT1 1000 -1978 75 SEG23 800 1978 125 COM7 -1528 -800 26 VSS 1100 -1978 76 SEG24 700 1978 126 COM8 -1528 -900 27 VDDL 1200 -1978 77 SEG25 600 1978 127 COM9 -1528 -1000 28 VDD 1300 -1978 78 SEG26 500 1978 128 COM10 -1528 -1100 29 P10 1400 -1978 79 SEG27 400 1978 129 COM11 -1528 -1200 30 P11 1528 -1900 80 SEG28 300 1978 130 AVDD -1528 -1300 31 TEST 1528 -1800 81 SEG29 200 1978 131 VREF -1528 -1400 32 COM23 1528 -1700 82 SEG30 100 1978 132 AVSS -1528 -1500 33 COM22 1528 -1600 83 SEG31 0 1978 133 AIN0 -1528 -1600 34 COM21 1528 -1500 84 SEG32 -100 1978 134 AIN1 -1528 -1700 35 COM20 1528 -1400 85 SEG33 -200 1978 135 P03 -1528 -1800 36 COM19 1528 -1300 86 SEG34 -300 1978 136 P02 -1528 -1900 37 COM18 1528 -1200 87 SEG35 -400 1978 38 COM17 1528 -1100 88 SEG36 -500 1978 39 COM16 1528 -1000 89 SEG37 -600 1978 40 COM15 1528 -900 90 SEG38 -700 1978 41 COM14 1528 -800 91 SEG39 -800 1978 42 COM13 1528 -700 92 SEG40 -900 1978 43 COM12 1528 -600 93 SEG41 -1000 1978 44 SEG0 1528 -500 94 SEG42 -1100 1978 45 SEG1 1528 -400 95 SEG43 -1200 1978 46 SEG2 1528 -300 96 SEG44 -1300 1978 47 SEG3 1528 -200 97 SEG45 -1400 1978 48 SEG4 1528 -100 98 SEG46 -1528 1900 49 SEG5 1528 0 99 SEG47 -1528 1800 50 SEG6 1528 100 100 VDD -1528 1700 12/37 FEDL610Q431-03 ML610Q431/ML610Q432 PIN LIST PAD No. Primary function Q432 Q431 Pin name I/O 4,26 4,26 Vss  28, 100 28, 100 VDD  27 27 VDDL 23 23 VDDX 101 101 VPP 132 132 AVSS 130 130 AVDD 59 59 VL1 60 60 VL2 61 61 VL3 62 62 VL4 63 63 C1 64 64 C2 65 65 C3 66 66 C4 31 31 TEST 10 10 RESET_ N I 24 24 XT0 I 25 25 XT1 O 131 131 VREF  Function Negative power supply pin Secondary function Tertiary function Pin name I/O Function                                                                                                 Reset input pin       Low-speed clock oscillation pin Low-speed clock oscillation pin Reference power supply pin for successive approximation type ADC                   Positive power supply pin Power supply pin for internal logic (internally generated) Power supply pin for  low-speed oscillation (internally generated) Power supply pin for  Flash ROM Negative power supply pin for  successive approximation type ADC Positive power supply pin for successive  approximation type ADC Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Input/output pin for I/O testing  Pin name I/O Function 13/37 FEDL610Q431-03 ML610Q431/ML610Q432 PAD No. Primary function Q432 Q431 Pin name I/O Function Successive approximation type ADC input Successive approximation type ADC input Non-maskable interrupt pin Input port, External interrupt 0, Capture 0 input Input port, External interrupt 1, Capture 1 input Input port, External interrupt 2, UART0 receive Secondary function Tertiary function Pin name I/O Function Pin name I/O Function                                           133 133 AIN0 I 134 134 AIN1 I 3 3 NMI I 2 2 P00/EXI 0/CAP0 I 1 1 P01/EXI 1/CAP1 I 136 136 P02/EXI 2/RXD0 I 135 135 P03/ EXI3 I Input port, External interrupt 3 29 29 P10 I Input port OSC0 I High-speed oscillation    30 30 P11 I Input port OSC1 O High-speed oscillation    5 5 P20/ LED0 O Output port LSCLK O Low-speed clock output    6 6 P21/ LED1 O Output port OUTCLK O High-speed clock output    7 7 P22/ LED2 O Output port MD0 O Melody output    17 17 P30 I/O Input/output port IN0 I    18 18 P31 I/O Input/output port CS0 O    19 19 P32 I/O Input/output port RS0 O    20 20 P33 I/O Input/output port RT0 O    21 21 P34 I/O Input/output port RCT0 O PWM0 O 22 22 P35 I/O Input/output port RCM O   8 8 P40 SDA I/O 9 9 P41 I/O Input/output port I/O Input/output port RC type ADC0 oscillation input pin RC type ADC0 reference capacitor connection pin RC type ADC0 reference resistor connection pin RC type ADC0 resistor sensor connection pin RC type ADC0 resistor/capacitor sensor connection pin RC type ADC oscillation monitor I2C data input/output SCL I/O I2C clock input/output 11 11 P42 12 12 P43 13 13 P44/T02 P0CK 14 14 P45/T13 P1CK 15 15 P46 16 16   PWM output  RXD0 I UART data input SOUT0 SSIO data input I I/O SSIO synchronous clock O SSIO data output TXD0 O UART data output PWM0 O PWM output IN1 I RC type ADC1 oscillation input pin SIN0 I SSIO0 data input CS1 O SCK0 I/O SSIO0 synchronous clock I/O Input/output port RS1 O SOUT0 O SSIO0 data output P47 I/O Input/output port RT1 O    32 PA0 I/O      33 PA1 I/O       34 PA2 I/O       35 PA3 I/O       36 PA4 I/O       37 PA5 I/O      I/O Input/output port I/O Input/output port Input/output port, Timer 0/Timer I/O 2/PWM0 external clock input Input/output port, I/O Timer 1/Timer 3 external clock input Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port RC type ADC1 reference capacitor connection pin RC type ADC1 reference resistor connection pin RC type ADC1 resistor sensor connection pin       SIN0 SCK0 14/37 FEDL610Q431-03 ML610Q431/ML610Q432 PAD No. Primary function Q432 Q431 Pin name I/O Function Secondary function Tertiary function Pin name I/O Function Pin name I/O Function                         124 124 COM6 O LCD common pin               125 125 COM7 O LCD common pin       126 126 COM8 O LCD common pin       127 127 COM9 O LCD common pin        38 PA6 I/O  39 PA7 I/O Input/output port Input/output port     118 118 COM0 O LCD common pin   119 119 COM1 O LCD common pin   120 120 COM2 O LCD common pin   121 121 COM3 O LCD common pin   122 122 COM4 O LCD common pin   123 123 COM5 O LCD common pin   128 128 COM10 O LCD common pin       129 129 COM11 O LCD common pin       43 43 COM12 O LCD common pin       42 42 COM13 O LCD common pin       41 41 COM14 O LCD common pin       40 40 COM15 O LCD common pin       39  COM16 O LCD common pin       38  COM17 O LCD common pin       37  COM18 O LCD common pin       36  COM19 O LCD common pin       35  COM20 O LCD common pin       34  COM21 O LCD common pin       33  COM22 O LCD common pin       32  COM23 O LCD common pin       44 44 SEG0 O LCD segment pin       45 45 SEG1 O LCD segment pin       46 46 SEG2 O LCD segment pin       47 47 SEG3 O LCD segment pin       48 48 SEG4 O LCD segment pin       49 49 SEG5 O LCD segment pin       50 50 SEG6 O LCD segment pin       51 51 SEG7 O LCD segment pin       52 52 SEG8 O LCD segment pin       53 53 SEG9 O LCD segment pin       54 54 SEG10 O LCD segment pin       55 55 SEG11 O LCD segment pin       56 56 SEG12 O LCD segment pin       57 57 SEG13 O LCD segment pin       58 58 SEG14 O LCD segment pin       67 67 SEG15 O LCD segment pin       68 68 SEG16 O LCD segment pin       69 69 SEG17 O LCD segment pin       70 70 SEG18 O LCD segment pin       71 71 SEG19 O LCD segment pin       72 72 SEG20 O LCD segment pin       73 73 SEG21 O LCD segment pin       74 74 SEG22 O LCD segment pin       75 75 SEG23 O LCD segment pin       76 76 SEG24 O LCD segment pin       77 77 SEG25 O LCD segment pin       O LCD segment pin       78 78 SEG26 15/37 FEDL610Q431-03 ML610Q431/ML610Q432 PAD No. Primary function Q432 Q431 Pin name I/O Function Secondary function Pin name I/O Function Tertiary function Pin name I/O Function 79 79 SEG27 O LCD segment pin       80 80 SEG28 O LCD segment pin       81 81 SEG29 O LCD segment pin       82 82 SEG30 O LCD segment pin       83 83 SEG31 O LCD segment pin       84 84 SEG32 O LCD segment pin       85 85 SEG33 O LCD segment pin       86 86 SEG34 O LCD segment pin       87 87 SEG35 O LCD segment pin       88 88 SEG36 O LCD segment pin       89 89 SEG37 O LCD segment pin       90 90 SEG38 O LCD segment pin       91 91 SEG39 O LCD segment pin       92 92 SEG40 O LCD segment pin       93 93 SEG41 O LCD segment pin       94 94 SEG42 O LCD segment pin       95 95 SEG43 O LCD segment pin       96 96 SEG44 O LCD segment pin       97 97 SEG45 O LCD segment pin       98 98 SEG46 O LCD segment pin       99 99 SEG47 O LCD segment pin       102 102 SEG48 O LCD segment pin       103 103 SEG49 O LCD segment pin       104 104 SEG50 O LCD segment pin       105 105 SEG51 O LCD segment pin       106 106 SEG52 O LCD segment pin       107 107 SEG53 O LCD segment pin       108 108 SEG54 O LCD segment pin       109 109 SEG55 O LCD segment pin       110 110 SEG56 O LCD segment pin       111 111 SEG57 O LCD segment pin       112 112 SEG58 O LCD segment pin       113 113 SEG59 O LCD segment pin       114 114 SEG60 O LCD segment pin       115 115 SEG61 O LCD segment pin       116 116 SEG62 O LCD segment pin       117 117 SEG63 O LCD segment pin       16/37 FEDL610Q431-03 ML610Q431/ML610Q432 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary Secondary — — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. OSC1 O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin and VSS. This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1). LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P10-P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA7 I/O General-purpose input/output port. These pins are for the ML610Q431, but are not provided in the ML610Q432. P00-P03 I 17/37 FEDL610Q431-03 ML610Q431/ML610Q432 Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/Se condary Positive Secondary Positive Secondary Positive I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary — Tertiary Positive Tertiary Positive PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. Tertiary Positive Primary — External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P03 pins. Primary Positive/ negative Positive/ negative Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary External clock input pin used for both Timer 0 and Timer 2. The clocks for these timers are selected by software. This pin is used as the primary function of the P44 pin. External clock input pin used for both Timer 1 and Timer 3. The clocks for these timers are selected by software. This pin is used as the primary function of the P45 pin. Primary I/O UART TXD0 O RXD0 I Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 T02P0CK O Ｉ External interrupt NMI I EXI0-3 I Capture CAP0 I CAP1 I Timer T02P0CK T13P1CK I I Melody MD0 O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0-2 O NMOS open drain output pins to drive LED. These pins are used as the primary function of the P20-P22 pins. Primary Primary Positive/ negative Positive/ negative — Primary — Secondary Positive/ negative Primary Positive/ negative 18/37 FEDL610Q431-03 ML610Q431/ML610Q432 Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RＣT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. Successive approximation type A/D converter AVSS — Negative power supply pin for successive approximation type A/D converter. AVDD — Positive power supply pin for successive approximation type A/D converter. VREF — Reference power supply pin for successive approximation type A/D converter. AIN0 I Channel 0 analog input for successive approximation type A/D converter. AIN1 I Channel 1 analog input for successive approximation type A/D converter. LCD drive signal COM0-15 O Common output pins. COM16-23 O Common output pins. These pins are for the ML610Q432, but are not provided in the ML610Q431. SEG0-63 O Segment output pin. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1, V — VL2, VL3, and VL4, respectively. L3 VL4 C1 C2 C3 C4 For testing TEST Power supply VSS VDD VDDL — — — — — Power supply pins for LCD bias (internally generated). Capacitors C12 and C34 (see measuring circuit 1) are connected between C1 and C2 and between C3 and C4, respectively. I/O Input/output pin for testing. A pull-down resistor is internally connected. — — — VDDX — VPP — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 19/37 FEDL610Q431-03 ML610Q431/ML610Q432 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Pin VPP AVDD AVSS VREF AIN0, AIN1 VL1, VL2, VL3, VL4 C1, C2, C3, C4 RESET_N TEST NMI P00 to P03 P10 to P11 P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 COM0 to 23 SEG0 to 63 Termination of Unused Pins Recommended pin termination Open VSS VSS VSS Open Open Open Open Open Open VDD or VSS VDD Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 20/37 FEDL610Q431-03 ML610Q431/ML610Q432 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = AVSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 AVDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 3 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 4 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 6 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 7 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 8 VL3 Ta = 25°C −0.3 to +5.25 V Power supply voltage 9 VL4 Ta = 25°C −0.3 to +7.0 V Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 122 mW Storage temperature TSTG  −55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VSS = AVSS = 0V) Parameter Operating temperature Operating voltage Symbol Condition Range Unit TOP  −20 to +70 °C VDD  1.1 to 3.6 AVDD  2.2 to 3.6 30k to 36k 30k to 650k 30k to 4.2M 1.0±30% 0.1±30% V Operating frequency (CPU) fOP Capacitor externally connected to VDDL pin CL0 CL1 VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V VDD = 1.8 to 3.6V   Capacitor externally connected to VDDX pin CX  0.1±30% µF Capacitors externally connected to VL1, 2, 3, 4 pins Ca, b, c, d  1.0±30% µF Capacitors externally connected across C1 and C2 pins and across C3 and C4 pins C12, C34  1.0±30% µF Hz µF 21/37 FEDL610Q431-03 ML610Q431/ML610Q432 CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation *1 external capacitor Min. Rating Typ. Max.   32.768k  Hz RL    40k Ω  0  CDL/CGL CL=6pF of crystal *2 oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation  6   12  Symbol Condition fXTL Unit pF High-speed crystal/ceramic fXTH   4.0M / 4.096M  Hz oscillation frequency High-speed crystal oscillation CDH   24  pF external capacitor CGH   24  *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL. OPERATING CONDITIONS OF FLASH ROM Parameter Operating temperature Operating voltage Write cycles Data retention Symbol TOP VDD VDDL VPP CEP YDR Condition At write/erase *1 At write/erase *1 At write/erase *1 At write/erase   Range 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 80 10 (VSS = AVSS = 0V) Unit °C V cycles years *1 :When writing to and erasing on the flash Memory, the voltage in the specified range needs to be supplied to the VDDL pin. The VPP pin has an internal pull-down resistor. 22/37 FEDL610Q431-03 ML610Q431/ML610Q432 DC CHARACTERISTICS (1/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (1/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta = 25°C 500 kHz −10% +10% VDD = 1.3 500kHz RC oscillation fRC frequency to 3.6V Typ. Ta = −20 to Typ. 500 kHz +70°C −25% +25% LSCLK = 32.768kHz Typ. Typ. 4 PLL oscillation frequency* fPLL 8.192 MHz VDD = 1.8 to 3.6V -2.5% +2.5% Low-speed crystal oscillation TXTL   0.3 2 s 2 start time* 500kHz RC oscillation start TRC   50 500 µs time 1 High-speed crystal oscillation TXTH VDD = 1.8 to 3.6V ― 2 20 3 start time* PLL oscillation start time TPLL VDD = 1.8 to 3.6V ― 1 10 ms Low-speed oscillation stop TSTOP  0.2 3 20 *1 detect time Reset pulse width PRST  200   µs Reset noise elimination PNRST    0.3 pulse width Power-on reset activation TPOR    10 ms power rise time 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. ML610Q431A/ML610Q432A does not have this function. 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Use 4.096MHz Crystal Oscillator HC49SFWB (Kyocera). 4 * : 1024 clock average. [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 23/37 FEDL610Q431-03 ML610Q431/ML610Q432 DC CHARACTERISTICS (2/5) Parameter VL1 voltage VL1 temperature deviation VL1 voltage dependency (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (2/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. CN4–0 = 00H 0.89 0.94 0.99 CN4–0 = 01H 0.91 0.96 1.01 CN4–0 = 02H 0.93 0.98 1.03 CN4–0 = 03H 0.95 1.00 1.05 CN4–0 = 04H 0.97 1.02 1.07 CN4–0 = 05H 0.99 1.04 1.09 CN4–0 = 06H 1.01 1.06 1.11 CN4–0 = 07H 1.03 1.08 1.13 CN4–0 = 08H 1.05 1.10 1.15 CN4–0 = 09H 1.07 1.12 1.17 CN4–0 = 0AH 1.09 1.14 1.19 CN4–0 = 0BH 1.11 1.16 1.21 CN4–0 = 0CH 1.13 1.18 1.23 CN4–0 = 0DH 1.15 1.20 1.25 CN4–0 = 0EH 1.17 1.22 1.27 CN4–0 = 0FH 1.19 1.24 1.29 VDD = 3.0V, V VL1 Tj = 25°C CN4–0 = 10H 1.21 1.26 1.31 CN4–0 = 11H 1.23 1.28 1.33 CN4–0 = 12H 1.25 1.30 1.35 CN4–0 = 13H 1.27 1.32 1.37 *1 CN4–0 = 14H 1.29 1.34 1.39 *1 CN4–0 = 15H 1.31 1.36 1.41 1 *1 CN4–0 = 16H 1.33 1.38 1.43 *1 CN4–0 = 17H 1.35 1.40 1.45 *1 CN4–0 = 18H 1.37 1.42 1.47 *1 CN4–0 = 19H 1.39 1.44 1.49 *1 CN4–0 = 1AH 1.41 1.46 1.51 *1 CN4–0 = 1BH 1.43 1.48 1.53 *1 CN4–0 = 1CH 1.45 1.50 1.55 *1 CN4–0 = 1DH 1.47 1.52 1.57 *1 CN4–0 = 1EH 1.49 1.54 1.59 *1 CN4–0 = 1FH 1.51 1.56 1.61 ∆VL1 VDD = 3.0V  −1.5  mV/°C ∆VL1 VDD = 1.3 to 3.6V  5 20 mV/V VDD = 3.0V, Tj = 25°C 300kΩ load (VL4−VSS) 1/3 bias VDD = 3.0V, 1/4 bias Tj = 25°C 300kΩ load 1/3 bias (VL4−VSS) 1/4 bias Typ. −10% VL1×2 Typ. +4% Typ. −10% Typ. +4% Typ. −10% VL1×2 VL1×3 VL1×3 VL1×4    600 VL2 voltage VL2 VL3 voltage VL3 VL4 voltage VL4 LCD bias voltage generation time TBIAS V Typ. +5% ms 1 * : When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H). 24/37 FEDL610Q431-03 ML610Q431/ML610Q432 DC CHARACTERISTICS (3/5) Parameter BLD threshold voltage BLD threshold voltage temperature deviation Supply current 1 Supply current 2 Supply current 3 Supply current 4 (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (3/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. LD2–0 = 0H 1.35 LD2–0 = 1H 1.4 LD2–0 = 2H 1.45 LD2–0 = 3H 1.5 LD2–0 = 4H 1.6 LD2–0 = 5H 1.7 LD2–0 = 6H 1.8 LD2–0 = 7H 1.9 Typ. Typ. V VDD = 1.35 to 3.6V VBLD −2% +2% LD2–0 = 8H 2.0 LD2–0 = 9H 2.1 LD2–0 = 0AH 2.2 LD2–0 = 0BH 2.3 LD2–0 = 0CH 2.4 LD2–0 = 0DH 2.5 LD2–0 = 0EH 2.7 LD2–0 = 0FH 2.9 ∆VBLD IDD1 IDD2 IDD3 IDD4  0.1  Ta = 25°C Ta = -20 to +70°C  0.15 0.50   2.50 CPU: In HALT state (LTBC, RTC: 3 5 Operating* * ). High-speed oscillation: Stopped. LCD/BIAS circuits: Stopped. Ta = 25°C  0.5 1.3 Ta = -20 to +70°C   3.5 CPU: In 32.768kHz operating 1 3 state.* * High-speed oscillation: Stopped. 2 LCD/BIAS circuits: Operating.* Ta = 25°C  5 7 Ta = -20 to +70°C   12 Ta = 25°C  70 85 Ta = -20 to +70°C Ta = 25°C  VDD = 1.35 to 3.6V CPU: In STOP state. Low-speed/high-speed oscillation: stopped. CPU: In 500kHz CR operating state. 2 LCD/BIAS circuits: Operating.* %/°C µA 1 µA µA µA  100 CPU: In 4.096MHz operating  0.8 1.0 2 3 state.* * PLL: In oscillating state. Supply current 5 IDD5 mA Ta = -20 2 LCD/BIAS circuits: Operating. *   1.2 to +70°C VDD = 1.8 to 3.6V CPU: In 4.096MHz operating Ta = 2 state.*  1.5 1.6 25°C 3 4 PLL: In oscillating state. * * Supply current 6 IDD6 mA A/D: In operating state. Ta = -20 2 LCD/BIAS circuits: Operating. *   2.5 to +70°C VDD = AVDD = 3.0V 1 * : CPU operating rate is 100% (No HALT state). 2 * : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 3 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 4 * : Use 4.096MHz Crystal Oscillator HC49SFWB (Kyocera). 5 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 25/37 FEDL610Q431-03 ML610Q431/ML610Q432 DC CHARACTERISTICS (4/5) Parameter (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (4/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. Output voltage 1 nd (P20–P22/2 function is selected) (P30–P35) (P40–P47) *1 (PA0–PA7) Output voltage 2 nd (P20–P22/2 function is Not selected) Output voltage 3 (P40–P41) Output voltage 4 (COM0–15) *2 (COM16–23) (SEG0–63) Output leakage (P20–P22) (P30–P35) (P40–P47) *1 (PA0–PA7) IOH1 = −0.5mA, VDD = 1.8 to 3.6V VDD−0.5   IOH1 = -0.1mA, VDD = 1.3 to 3.6V VDD−0.3   IOH1 = -0.03mA, VDD = 1.1 to 3.6V VDD−0.3 IOL1 = +0.5mA, VDD = 1.8 to 3.6V IOL1 = +0.1mA, VDD = 1.3 to 3.6V     0.5 0.5 IOL1 = +0.03mA, VDD = 1.1 to 3.6V   0.3 VOH2 IOH1 = −0.5mA, VDD = 1.8 to 3.6V IOH1 = -0.1mA, VDD = 1.3 to 3.6V IOH1 = -0.03mA, VDD = 1.1 to 3.6V VDD−0.5 VDD−0.3 VDD−0.3       VOL2 IOL2 = +5mA, VDD = 1.8 to 3.6V   0.5 VOL3 IOL3 = +3mA, VDD = 2.0 to 3.6V 2 (when I C mode is selected)   0.4 VOH4 IOH4 = −0.2mA, VL1=1.2V VL4−0.2   VOMH4 IOMH4 = +0.2mA, VL1=1.2V   VL3+0.2 VOMH4S IOMH4S = −0.2mA, VL1=1.2V VL3−0.2   VOM4 IOM4 = +0.2mA, VL1=1.2V   VL2+0.2 VOM4S IOM4S = −0.2mA, VL1=1.2V VL2−0.2   VOML4 IOML4 = +0.2mA, VL1=1.2V   VL1+0.2 VOML4S IOML4S = −0.2mA, VL1=1.2V VL1−0.2   VOL4 IOL4 = +0.2mA, VL1=1.2V   0.2 IOOH VOH = VDD (in high-impedance state)   1 VOH1 VOL1 IOOL IIH1 Input current 1 (RESET_N) Input current 1 (TEST) IIL1 IIH1 IIL1 Input current 2 (NMI) (P00–P03) (P10–P11) (P30–P35) (P40–P47) *1 (PA0–PA7) VOL = VSS (in high-impedance state) VIH1 = VDD VDD = 1.8 to 3.6V VIL1 = VSS VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V VIH1 = VDD VDD = 1.1 to 3.6V VIL1 = Vss IIH2 VIH2 = VDD (when pulled-down) IIL2 VIL2 = VSS (when pulled-up) −1   0 −600 −600 −600 20 10 2 -1  −300 −300 −300 300 300 300  1 −20 -10 -2 600 600 600  VDD = 1.8 to 3.6V 2 30 200 VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V 0.2 0.01 −200 −200 −200 30 30 −30 −30 −30 200 200 −2 -0.2 -0.01 IIH2Z VIH2 = VDD (in high-impedance state)   1 IIL2Z VIL2 = VSS (in high-impedance state) −1   V 2 µA 3 µA 4 1 * : ML610Q431 only 2 * : ML610Q432 only 26/37 FEDL610Q431-03 ML610Q431/ML610Q432 DC CHARACTERISTICS (5/5)) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) (5/5) Rating Measuring Symbol Condition Unit circuit Min. Typ. Max. Parameter Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) Hysteresis width (RESET_N) (TEST_N) (NMI) (P00–P03) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) VDD = 1.3 to 3.6V 0.7 ×VDD  VDD VDD = 1.1 to 3.6V 0.7 ×VDD  VDD VDD = 1.3 to 3.6V 0  0.3 ×VDD VDD = 1.1 to 3.6V 0  0.2 ×VDD VDD = 2.0 to 3.6V 0.05 ×VDD 0.18 ×VDD 0.4 ×VDD VDD = 1.1 to 3.6V 0.02 ×VDD 0.18 ×VDD 0.4 ×VDD VIH2  0.7 ×VDD  VDD VIL2  0  0.3 ×VDD CIN f = 10kHz Vrms = 50mV Ta = 25°C   5 VIH1 VIL1 V 5 pF  ∆VT Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00–P03) (P10–P11) (P30–P35) (P40–P47) *1 (PA0–PA7) 1 * : ML610Q431 only HYSTERESIS WIDTH ∆VT Input signal VDD VSS Internal signal VDDL VSS 27/37 FEDL610Q431-03 ML610Q431/ML610Q432 MEASURING CIRCUITS MEASURING CIRCUIT 1 XT0 C4 XT1 C3 C2 C34 32.768kHz crystal CGH P10/OSC0 C12 C1 CDH CV: 1µF CL0: 1µF CL1: 0.1µF CX: 0.1µF Ca,Cb,Cc,Cd: 1µF C12,C34: 1µF CGH: 24pF CDH: 24pF 32.768kHz crystal: C-001R (Epson Toyocom) 4.096MHz crystal: HC49SFWB (Kyocera) P11/OSC1 4.096MHz crystal VDD AVDD VREFVDDL VDDX VL1 VL2 VL3 VL4 VSS AVSS A CV CL1 CL0 CX Ca Cb Cc Cd MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 V VL4 AVDDVREF VSSAVSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 28/37 FEDL610Q431-03 ML610Q431/ML610Q432 MEASURING CIRCUIT 3 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 A VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VL1 VL2 VL3 VL4 AVDD VREF VSSAVSS *3: Measured at the specified output pins. VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 Waveform monitoring MEASURING CIRCUIT 5 VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. 29/37 FEDL610Q431-03 ML610Q431/ML610Q432 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz  76.8 106.8 µs P00–P03 (Rising-edge interrupt) tNUL P00–P03 (Falling-edge interrupt) tNUL NMI, P00–P03 (Both-edge interrupt) tNUL AC CHARACTERISTICS (UART) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate  tTBRT  1 BRT* 1  s 1 BRT* BRT* 1 BRT* s −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0). Receive baud rate  tRBRT tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 30/37 FEDL610Q431-03 ML610Q431/ML610Q432 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. 2 When RC oscillation is active* 10   µs (VDD = 1.3 to 3.6V) SCLK input cycle tSCYC (slave mode) When high-speed oscillation is 1   µs 3 active* (VDD = 1.8 to 3.6V) SCLK output cycle 1 tSCYC   SCLK*  s (master mode) 2 When RC oscillation is active* 4   µs (VDD = 1.3 to 3.6V) SCLK input pulse width tSW (slave mode) When high-speed oscillation is 0.4   µs 3 active* (VDD = 1.8 to 3.6V) 1 1 1 SCLK* SCLK* SCLK* SCLK output pulse width tSW  s (master mode) ×0.4 ×0.5 ×0.6 2 When RC oscillation is active*   500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (slave mode) When high-speed oscillation is   240 3 active* (VDD = 1.8 to 3.6V) 2 When RC oscillation is active*   500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (master mode) When high-speed oscillation is   240 3 active* (VDD = 1.8 to 3.6V) SIN input setup time tSS  80   ns (slave mode) 2 When RC oscillation is active* 500   SIN input (VDD = 1.3 to 3.6V) setup time ns tSS When high-speed oscillation is (master mode) 240   3 active* (VDD = 1.8 to 3.6V) 2 When RC oscillation is active* 300   (VDD = 1.3 to 3.6V) SIN input tSH ns hold time When high-speed oscillation is 80   3 active* (VDD = 1.8 to 3.6V) 1 * : Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) 2 * : When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0) 3 * : When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency control register (FCON0) tSCYC tSW tSW SCLK0* tSD SD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. 31/37 FEDL610Q431-03 ML610Q431/ML610Q432 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz) (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  100 kHz SCL hold time tHD:STA  4.0   µs (start/restart condition) SCL ”L” level time tLOW  4.7   µs SCL ”H” level time tHIGH  4.0   µs SCL setup time tSU:STA  4.7   µs (restart condition) SDA hold time tHD:DAT  0  3.45 µs SDA setup time tSU:DAT  0.25   µs SDA setup time tSU:STO  4.0   µs (stop condition) Bus-free time tBUF  4.7   µs AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz) (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  400 kHz SCL hold time tHD:STA  0.6   µs (start/restart condition) SCL ”L” level time tLOW  1.3   µs SCL ”H” level time tHIGH  0.6   µs SCL setup time tSU:STA  0.6   µs (restart condition) SDA hold time tHD:DAT  0  0.9 µs SDA setup time tSU:DAT  0.1   µs SDA setup time tSU:STO  0.6   µs (stop condition) Bus-free time tBUF  1.3   µs Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 32/37 FEDL610Q431-03 ML610Q431/ML610Q432 AC CHARACTERISTICS (RC Oscillation A/D Converter) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0, RS1, Resistors for oscillation RT0, CS0, CT0, CS1 ≥ 740pF 1   kΩ RT0-1,RT1 fOSC1 Resistor for oscillation = 1kΩ 209.4 330.6 435.1 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 41.29 55.27 64.16 kHz VDD = 1.5V fOSC3 Resistor for oscillation = 100kΩ 4.71 5.97 7.06 kHz Kf1 RT0, RT0-1, RT1 = 1kHz 5.567 5.982 6.225  RS to RT oscillation frequency *1 ratio Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01  VDD = 1.5V Kf3 RT0, RT0-1, RT1 = 100kHz 0.104 0.108 0.118  fOSC1 Resistor for oscillation = 1kΩ 407.3 486.7 594.6 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 49.76 59.28 72.76 kHz VDD = 3.0V fOSC3 Resistor for oscillation = 100kΩ 5.04 5.993 7.04 kHz Kf1 RT0, RT0-1, RT1 = 1kHz 8.006 8.210 8.416  RS to RT oscillation frequency *1 ratio Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01  VDD = 3.0V Kf3 RT0, RT0-1, RT1 = 100kHz 0.100 0.108 0.115  *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) VDDX RT1 RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT0 RS0 RS0 RT0 Input pins VIH , CVR1 RT0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) AVDD VREFVSS AVSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 33/37 FEDL610Q431-03 ML610Q431/ML610Q432 Electrical Characteristics of Successive Approximation Type A/D Converter (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Resolution n    12 bit 2.7V ≤ VREF ≤ 3.6V −4  +4 Integral non-linearity error IDL 2.2V ≤ VREF ≤ 2.7V −6  +6 2.7V ≤ VREF ≤ 3.6V −3  +3 Differential non-linearity error LSB DNL 2.2V ≤ VREF ≤ 2.7V −5  +5 Zero-scale error VOFF  −6  +6 Full-scale error FSE  −6  +6 Reference voltage VREF  2.2  AVDD V SACK = 0  25  (HSCLK = 375kHz to 625kHz) Conversion time tCONV φ/CH SACK = 1  112  (HSCLK = 1.5MHz to 4.2MHz) φ: Period of high-speed clock (HSCLK) AVDD Reference voltage VREF VDD VDDL 1µF 1µF A 0.1µF − 1µF RI≤5kΩ + Analog input 0.1µF VDDX AIN0, AIN1 0.1µF VSS AVSS 34/37 FEDL610Q431-03 ML610Q431/ML610Q432 Package Dimensions (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/37 FEDL610Q431-03 ML610Q431/ML610Q432 REVISION HISTORY Page Document No. FEDL610Q431-01 FEDL610Q431-02 FEDL610Q431-03 Date Previous Edition Current Edition Description Jun.29,2010 ― 3 4 5 ― 3 4 5 23 23 33 All 33 All 3 4 ― 22 21 23 35 37 2 2 Formally edition 1.0 The product name of A version is abbed. Terminal name CRT0 is corrected to RCT0. Terminal name CRT0 is corrected to RCT0. Typ value"0" of a BLD threshold voltage temperature deviation is corrected to "0.1." Substitution of a packege dimensions. Change header and footer. Change from "Shipment" to "Product name － Supported Function" Add CLOCK GENERATION CIRCUIT OPERATING CONDITIONS Change "RESET" to "Reset pulse width (PRST) " and "Power-on reset activation power rise time (TPOR) ". Change description in Notes. Corrected a typo. “100kbps@1MHz HSCLK” is corrected to 100kbps@4MHz HSCLK. Feb.8,2011 Mar.23,2015 36/37 FEDL610Q431-03 ML610Q431/ML610Q432 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. 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LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2010 – 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 37/37