FEDD51V18165F-05
Issue Date: Nov. 01, 2013
MSM51V18165F
1,048,576-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM51V18165F is a 1,048,576-word 16-bit dynamic RAM fabricated in LAPIS
Semiconductor’s silicon-gate CMOS technology. The MSM51V18165F achieves high integration,
high-speed operation, and low-power consumption because LAPIS Semiconductor manufactures the
device in a quadruple-layer poly-silicon/double-layer metal CMOS process. The MSM51V18165F is
available in a 50/44-pin plastic TSOP.
FEATURES
· 1,048,576-word 16-bit configuration
· Single 3.3V power supply, 0.3V tolerance
· Input : LVTTL compatible, low input capacitance
· Output : LVTTL compatible, 3-state
· Refresh : 1024 cycles/16ms
· Fast page mode with EDO, read modify write capability
· CAS before RAS refresh, hidden refresh, RAS-only refresh capability
· Package:
50/44-pin 400mil plastic TSOP (P-TSOP(2)50/44-400-0.80-T3K6)
PRODUCT FAMILY
Access Time (Max.)
Family
MSM51V18165F
tRAC
tAA
tCAC
tOEA
Cycle Time
(Min.)
50ns
60ns
70ns
25ns
30ns
35ns
13ns
15ns
20ns
13ns
15ns
20ns
84ns
104ns
124ns
Power Dissipation
Operating
(Max.)
450mW
414mW
378mW
Standby
(Max.)
1.8mW
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FEDD51V18165F-05
MSM51V18165F
PIN CONFIGURATION (TOP VIEW)
VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
50 VSS
49 DQ16
NC 15
NC 16
WE 17
RAS 18
NC 19
NC 20
A0 21
A1 22
A2 23
A3 24
VCC 25
36 NC
35 LCAS
48 DQ15
47 DQ14
46 DQ13
45 VSS
44 DQ12
43 DQ11
42 DQ10
41 DQ9
40 NC
34 UCAS
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
50/44-Pin Plastic TSOP
(K Type)
Pin Name
Function
A0–A9
Address Input
RAS
Row Address Strobe
LCAS
Lower Byte Column Address Strobe
UCAS
Upper Byte Column Address Strobe
DQ1–DQ16
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (3.3V)
VSS
Ground (0V)
NC
No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must
be provided to every VSS pin.
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FEDD51V18165F-05
MSM51V18165F
FUNCTION TABLE
Input Pin
DQ Pin
Function Mode
RAS
LCAS
UCAS
WE
OE
DQ1-DQ8
DQ9-DQ16
H
*
*
*
*
High-Z
High-Z
Standby
L
H
H
*
*
High-Z
High-Z
Refresh
L
L
H
H
L
DOUT
High-Z
Lower Byte Read
L
H
L
H
L
High-Z
DOUT
Upper Byte Read
L
L
L
H
L
DOUT
DOUT
Word Read
L
L
H
L
H
DIN
Don’t Care
Lower Byte Write
L
H
L
L
H
Don’t Care
DIN
Upper Byte Write
L
L
L
L
H
DIN
DIN
Word Write
L
L
L
H
H
High-Z
High-Z
* : “H” or “L”
3/17
FEDD51V18165F-05
MSM51V18165F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on Any Pin Relative to VSS
VIN, VOUT
–0.5 to VCC+ 0.3
V
Voltage VCC Supply relative to VSS
VCC
–0.5 to 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
*: Ta = 25C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
Power Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
3.0
3.3
3.6
V
VSS
0
0
0
Input High Voltage
VIH
2.0
Input Low Voltage
VIL
0.3*2
V
*1
VCC + 0.3
0.8
V
V
Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
*2. The input voltage is VSS 1.0V when the pulse width is less than 20ns (the pulse width respect to the
point at which VSS is applied).
PIN CAPACITANCE
(Vcc = 3.3V 0.3V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Max.
Unit
CIN1
—
5
pF
(RAS, LCAS, UCAS, WE, OE)
CIN2
—
7
pF
Output Capacitance (DQ1 - DQ16)
CI/O
—
7
pF
Input Capacitance (A0 - A9)
Input Capacitance
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FEDD51V18165F-05
MSM51V18165F
DC CHARACTERISTICS
(VCC = 3.3V 0.3V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
Max.
Min.
Max.
Min.
Max.
2.4
VCC
2.4
VCC
2.4
VCC
V
0
0.4
0
0.4
0
0.4
V
All other pins not
under test = 0V
10
10
10
10
10
10
A
DQ disable
10
10
10
10
10
10
A
125
115
105
mA
1,2
RAS, CAS = VIH
2
2
2
RAS, CAS
VCC 0.2V
1
0.5
mA
0.5
0.5
125
115
105
mA
1,2
5
5
5
mA
1
125
115
105
mA
1,2
125
115
105
mA
1,3
Output High Voltage
VOH
IOH = 2.0mA
Output Low Voltage
VOL
IOL = 2mA
0V VI VCC+0.3V;
Input Leakage
Current
ILI
Output Leakage
Current
ILO
Average Power
Supply Current
ICC1
(Operating)
Power Supply
Current
ICC2
(Standby)
Average Power
Supply Current
ICC3
(CAS before RAS
Refresh)
Average Power
Supply Current
(Fast Page Mode)
RAS, CAS cycling,
tRC = Min.
CAS = VIH,
tRC = Min.
RAS = VIH,
ICC5
(Standby)
Average Power
Supply Current
0V VO VCC
RAS cycling,
(RAS-only Refresh)
Power Supply
Current
MSM51V18165 MSM51V18165 MSM51V18165
F-50
F-60
F-70
Unit Note
CAS = VIL,
DQ = enable
ICC6
RAS = cycling,
CAS before RAS
RAS = VIL,
ICC7
CAS cycling,
tHPC = Min.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
5/17
FEDD51V18165F-05
MSM51V18165F
AC CHARACTERISTICS (1/2)
(VCC = 3.3V 0.3V, Ta = 0 to 70°C) Note1,2,3
Parameter
Symbol
MSM51V18165
F-50
MSM51V18165
F-60
MSM51V18165
F-70
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
tRC
84
104
124
ns
Read Modify Write Cycle Time
tRWC
110
135
160
ns
Fast Page Mode Cycle Time
tHPC
20
25
30
ns
Fast Page Mode Read Modify Write
tHPRWC
Cycle Time
58
68
78
ns
Access Time from RAS
tRAC
50
60
70
ns
4, 5, 6
Access Time from CAS
tCAC
13
15
20
ns
4,5
Access Time from Column Address
tAA
25
30
35
ns
4,6
Access Time from CAS Precharge
tCPA
30
35
40
ns
4,12
Access Time from OE
tOEA
13
15
20
ns
4
Output Low Impedance Time from
CAS
tCLZ
0
0
0
ns
4
Data Output Hold After CAS Low
tDOH
5
5
5
ns
CAS to Data Output Buffer Turnoff Delay Time
tCEZ
0
13
0
15
0
20
ns
7,8
RAS to Data Output Buffer Turnoff Delay Time
tREZ
0
13
0
15
0
20
ns
7,8
OE to Data Output Buffer Turn-off
Delay Time
tOEZ
0
13
0
15
0
20
ns
7
WE to Data Output Buffer Turnoff Delay Time
tWEZ
0
13
0
15
0
20
ns
7
Transition Time
tT
1
50
1
50
1
50
ns
3
Refresh Period
tREF
16
16
16
ms
RAS Precharge Time
tRP
30
40
50
ns
RAS Pulse Width
tRAS
50
10,000
60
10,000
70
10,000
ns
RAS Pulse Width
(Fast Page Mode with EDO)
tRASP
50
100,000
60
100,000
70
100,000
ns
RAS Hold Time
tRSH
7
10
13
ns
RAS Hold Time referenced to OE
tROH
7
10
13
ns
CAS Precharge Time
(Fast Page Mode with EDO)
tCP
7
10
10
ns
CAS Pulse Width
tCAS
7
10,000
10
10,000
13
10,000
ns
CAS Hold Time
tCSH
35
40
45
ns
CAS to RAS Precharge Time
tCRP
5
5
5
ns
13
30
35
40
ns
13
Random Read or Write Cycle Time
RAS Hold Time from CAS Precharge tRHCP
15
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FEDD51V18165F-05
MSM51V18165F
AC CHARACTERISTICS (2/2)
(VCC = 3.3V 0.3V, Ta = 0 to 70°C) Note1,2,3
Parameter
Symbol
MSM51V18165
F-50
MSM51V18165
F-60
MSM51V18165
F-70
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Note
OE Hold Time from CAS
(DQ Disable)
tCHO
5
5
5
ns
RAS to CAS Delay Time
tRCD
11
37
14
45
14
50
ns
5
RAS to Column Address Delay Time
tRAD
9
25
12
30
12
35
ns
6
Row Address Set-up Time
tASR
0
0
0
ns
Row Address Hold Time
tRAH
7
10
10
ns
Column Address Set-up Time
tASC
0
0
0
ns
12
Column Address Hold Time
tCAH
7
10
13
ns
12
Column Address to RAS Lead Time
tRAL
25
30
35
ns
Read Command Set-up Time
tRCS
0
0
0
ns
12
Read Command Hold Time
tRCH
0
0
0
ns
9,12
Read Command Hold Time
referenced to RAS
tRRH
0
0
0
ns
9
Write Command Set-up Time
tWCS
0
0
0
ns
10,12
Write Command Hold Time
tWCH
7
10
13
ns
12
Write Command Pulse Width
tWP
7
10
10
ns
WE Pulse Width (DQ Disable)
tWPE
7
10
10
ns
OE Command Hold Time
tOEH
7
10
13
ns
OE Precharge Time
tOEP
7
10
10
ns
OE Command Hold Time
tOCH
7
10
10
ns
Write Command to RAS Lead Time
tRWL
7
10
13
ns
Write Command to CAS Lead Time
tCWL
7
10
13
ns
14
Data-in Set-up Time
tDS
0
0
0
ns
11,12
Data-in Hold Time
tDH
7
10
13
ns
11,12
OE to Data-in Delay Time
tOED
13
15
20
ns
CAS to WE Delay Time
tCWD
30
34
44
ns
10
Column Address to WE Delay Time
tAWD
42
49
59
ns
10
RAS to WE Delay Time
tRWD
67
79
94
ns
10
tCPWD
47
54
64
ns
10
CAS Active Delay Time from RAS
Precharge
tRPC
5
5
5
ns
12
RAS to CAS Set-up Time
(CAS before RAS)
tCSR
5
5
5
ns
12
RAS to CAS Hold Time
(CAS before RAS)
tCHR
10
10
10
ns
13
CAS Precharge WE Delay Time
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FEDD51V18165F-05
MSM51V18165F
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 2ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT)
are measured between VIH and VIL.
4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a
load circuit equivalent to 1 TTL load and 100pF.
The output timing reference levels are VOH=2.0 and VOL=0.8V.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit,
then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit,
then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the
open circuit condition and are not referenced to output voltage levels.
8. tCEZ, and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and
the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD
(Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify
write cycle and data out will contain data read from the selected cell; if neither of the above sets of
conditions is satisfied, then the condition of the data out (at access time) is indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to
the WE leading edge in an OE control write cycle, or a read modify write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later.
14. tCWL should be satisfied by both UCAS and LCAS.
15. tCP is determined by the time both UCAS and LCAS are high.
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FEDD51V18165F-05
MSM51V18165F
TIMING CHART
Read Cycle
RAS
tRC
tRAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tRCD
VIH
tRAD
VIL
tRAL
tASR
Address
WE
tCRP
tRSH
tCAS
VIH
tRAH
tASC
Row
VIL
tCAH
Column
tRCS
tRRH
VIH
tAA
VIL
tRCH
tROH
tREZ
tOEA
OE
VIH
VIL
tCAC
tRAC
DQ
tCEZ
tOEZ
tCLZ
VOH
Valid Data-out
Open
VOL
“H” or “L”
Write Cycle (Early Write)
tRC
tRAS
RAS
VIH
tRP
VIL
tCSH
tCRP
CAS
VIH
tRAD
VIL
tRAL
tASR
Address
VIH
VIL
tRAH
tASC
Row
OE
tCWL
VIH
tWCH
tWP
VIL
tRWL
VIH
VIL
tDS
DQ
tCAH
Column
tWCS
WE
tCRP
tRSH
tCAS
tRCD
VIH
VIL
tDH
Valid Data-in
Open
“H” or “L”
9/17
FEDD51V18165F-05
MSM51V18165F
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH
tRP
VIL
tCSH
tCRP
CAS
tCRP
tRSH
tCAS
VIH
tRAD
VIL
tASR
Address
tRCD
VIH
VIL
tRAH
Row
tCWL
tRWL
tCAH
tASC
Column
tCWD
tRCS
tRWD
WE
OE
tWP
VIH
VIL
tAWD
tAA
tOEH
tOEA
VIH
tOED
VIL
tDH
tCAC
tRAC
DQ
VI/OH
VI/OL
tOEZ
tCLZ
Valid
Data-out
tDS
Valid
Data-in
“H” or “L”
10/17
FEDD51V18165F-05
MSM51V18165F
Fast Page Mode Read Cycle (Part-1)
tRASP
tRCD
RAS
Address
tRHCP
VIH
VIL
tCSH
tCRP
CAS
tRP
tHPC
tCP
tCP
tCAS
tCAS
tCAS
VIH
VIL
VIH
VIL
tRAD
tASR
tRAH
tASC
Row
tCAH
tASC
Column
tASC
tCAH
Column
Column
tRCS
WE
OE
tOCH
tRRH
VIH
tAA
VIL
tCAC
tRAC
tAA
VIH
VIL
tCAC
tOEP
tOEA
tOEA
tOEZ
tOEZ
tDOH
VOH
Valid Data-out
VOL
tCAC
tAA
tCHO
tOEP
tCPA
tOEA
DQ
tCAH
Valid
Data-out
tREZ
Valid *
Data-out
Valid *
Data-out
tCLZ
* : Same Data,
“H” or “L”
Fast Page Mode Read Cycle (Part-2)
tRP
tRASP
tRHCP
tHPC
RAS
CAS
Address
VIH
VIL
tCRP
tCSH
tRCD
VIH
VIL
tCAS
OE
tCAS
tRAD
tASR
tRAH
Row
tASC
tCAH
tCAH
tASC
Column
Column
tRCS
WE
tCP
tCAS
VIH
VIL
tCRP
tHPC
tCP
tASC
tCAH
Column
tRCS
VIH
VIL
tAA
tRAC
tRCH
tWPE
tOEA
VIH
tAA
tCPA
tAA
tCAC
tDOH
VIL
tCAC
tCAC
DQ
VOH
VOL
tWEZ
Valid
Data-out
Valid Data-out
tCEZ
Valid
Data-out
tCLZ
“H” or “L”
11/17
FEDD51V18165F-05
MSM51V18165F
Fast Page Mode Write Cycle (Early Write)
tRP
tRASP
tCSH
RAS
tHPC
VIH
VIL
tCRP
tRCD
tCP
tCP
tCAS
CAS
Address
OE
VIL
VIH
VIL
tRAD
tASR
tASC
tRAH
Row
tASC
tCAH
Column
tASC
tCAH
Column
tWCS
tWCH
tCAH
Column
tWCS
tWCH
tWCH
VIH
VIL
VIH
VIL
tDS
DQ
tRSH
tCAS
tCAS
VIH
tWCS
WE
tHPC
VIH
tDH
tDS
Valid
Data-in
VIL
tDH
tDS
tDH
Valid
Data-in
Valid
Data-in
“H” or “L”
Fast Page Mode Read Modify Write Cycle
tRASP
tRWD
RAS
VIH
VIL
tCRP
tCPWD
tRCD
tCP
tRWL
tCWD
CAS
VIH
tASR
Address
VIH
VIL
tASC
tASC
tRAD
VIL
tHPRWC
tRAH
Row
Column
Column
tRCS
WE
VIH
VIL
tCAH
tCPA
tCWL
tCAH
tCWD
tRCS
tAWD
tAWD
tAA
tWP
tDS
tRAC
tAA
VIH
tOED
VIL
tCAC
DQ
VI/OH
VI/OL
tCLZ
tWP
tOEA
tOEA
OE
tDS
tOED
tOEH
tOEZ
tDH
Valid
Data-out
Valid
Data-in
tCAC
tOEH
tOEZ
Valid
Data-out
tDH
Valid
Data-in
tCLZ
“H” or “L”
12/17
FEDD51V18165F-05
MSM51V18165F
RAS-only Refresh Cycle
tRC
RAS
CAS
Address
tRAS
VIH
VIL
tRP
tRPC
tCRP
VIH
VIL
tASR
VIH
tRAH
Row
VIL
tCEZ
DQ
VOH
Open
VOL
Note: WE, OE = “H” or “L”
“H” or “L”
CAS before RAS Refresh Cycle
tRP
RAS
CAS
tRC
tRAS
VIH
VIL
tRPC
tCP
tRP
tCSR
tRPC
tCHR
VIH
VIL
tCEZ
DQ
VOH
VOL
Open
13/17
FEDD51V18165F-05
MSM51V18165F
Hidden Refresh Read Cycle
tRC
tRC
tRAS
RAS
tRAS
VIH
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
CAS
VIH
tRAD
VIL
tRAH
tASR
Address
VIH
tASC
Row
VIL
tCAH
Column
tRCS
WE
tCAC
VIH
VIL
tRRH
tRAL
tREZ
tAA
tROH
OE
DQ
tCEZ
tOEA
VIH
VIL
tRAC
tOEZ
tCLZ
VOH
Open
VOL
Valid Data-out
“H” or “L”
Hidden Refresh Write Cycle
tRC
tRC
tRAS
RAS
tRAS
VIH
VIL
tCRP
tRCD
tRSH
tRP
tRP
tCHR
CAS
VIH
tRAD
VIL
tASR
Address
VIH
VIL
tRAH
tASC
Row
tCAH
Column
tRAL
tRWL
tWP
WE
VIH
VIL
tWCS
OE
DQ
tWCH
VIH
VIL
VIH
tDS
tDH
Valid Data-in
VIL
“H” or “L”
14/17
FEDD51V18165F-05
MSM51V18165F
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
15/17
FEDD51V18165F-05
MSM51V18165F
REVISION HISTORY
Document
No.
Date
Page
Previous Current
Edition
Edition
Description
FEDD51V18165F-01
Oct. 2000
–
–
Final edition
FEDD51V18165F-02
Oct. 05, 2006
–
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