74AHCU04PW-Q100J

74AHCU04-Q100 Hex unbuffered inverter Rev. 3 — 18 May 2020 Product data sheet 1. General description The 74AHCU04-Q100 is high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHCU04-Q100 is a general-purpose hex unbuffered inverter. Each of the six inverters is a single stage. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Low power dissipation Balanced propagation delays Inputs accept voltages higher than VCC ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCU04PW-Q100 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74AHCU04BQ-Q100 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74AHCU04D-Q100 74AHCU04-Q100 Nexperia Hex unbuffered inverter 4. Functional diagram 1 1 1 1A 1Y 2 3 2A 2Y 4 1 3 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 6 1 9 8 1 11 10 1 13 mna342 Fig. 1. 4 1 5 5 2 12 A Y mna343 Logic symbol Fig. 2. mna045 IEC logic symbol Fig. 3. Logic diagram (one inverter) 5. Pinning information 5.1. Pinning 1 1A terminal 1 index area 2 12 6Y 2A 3 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) 74AHCU04_Q100 Product data sheet 2Y 4 11 5A 3A 5 3Y 6 GND(1) 13 6A 10 5Y 9 4A aaa-007669 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. aaa-007668 Fig. 4. 12 6Y 8 1Y 14 VCC 13 6A 2A 3 7 1 2 4Y 1A 1Y GND 74AHCU04-Q100 14 VCC 74AHCU04-Q100 Fig. 5. Pin configuration SOT762-1 (DHVQFN14) All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 2 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input 1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level Input Output nA nY L H H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit -0.5 +7.0 V -20 - -0.5 +7.0 V VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - 75 mA IGND ground current -75 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] VI < -0.5 V [1] Tamb = -40 °C to +125 °C [2] mA The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 3 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit 2.0 5.0 5.5 V 0 - 5.5 V 0 - VCC V -40 +25 +125 °C VCC = 3.3 V ± 0.3 V - - 100 ns/V VCC = 5.0 V ± 0.5 V - - 20 ns/V -40 °C to +125 °C Unit 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Conditions 25 °C -40 °C to +85 °C Min Typ Max Min Max Min Max VCC = 2.0 V 1.7 - - 1.7 - 1.7 - V VCC = 3.0 V 2.4 - - 2.4 - 2.4 - V VCC = 5.5 V 4.4 - - 4.4 - 4.4 - V VCC = 2.0 V - - 0.3 - 0.3 - 0.3 V VCC = 3.0 V - - 0.6 - 0.6 - 0.6 V VCC = 5.5 V - - 1.1 - 1.1 - 1.1 V IO = -50 μA; VCC = 2.0 V 1.8 2.0 - 1.8 - 1.8 - V IO = -50 μA; VCC = 3.0 V 2.7 3.0 - 2.7 - 2.7 - V IO = -50 μA; VCC = 4.5 V 4.0 4.5 - 4.0 - 4.0 - V IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.4 - V IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.8 - 3.7 - V IO = 50 μA; VCC = 2.0 V - 0 0.2 - 0.2 - 0.2 V IO = 50 μA; VCC = 3.0 V - 0 0.3 - 0.3 - 0.3 V IO = 50 μA; VCC = 4.5 V - 0 0.5 - 0.5 - 0.5 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA CI input capacitance - 3 10 - 10 - 10 pF 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 4 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Fig. 7. Symbol Parameter tpd propagation delay CPD [1] [2] [3] [4] power dissipation capacitance Conditions 25 °C nA to nY; see Fig. 6 -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit [1] VCC = 3.0 V to 3.6 V; CL = 15 pF [2] - 3.0 7.1 1.0 8.5 1.0 9.0 VCC = 3.0 V to 3.6 V; CL = 50 pF [2] - 3.4 10.6 1.0 12.0 1.0 13.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF [3] - 2.4 5.5 1.0 6.5 1.0 7.0 ns VCC = 4.5 V to 5.5 V; CL = 50 pF [3] - 3.5 7.0 1.0 8.0 1.0 9.0 ns [4] - 9.1 - - - - - pF CL = 50 pF; fi = 1 MHz; VI = GND to VCC ns tpd is the same as tPLH and tPHL. Typical values are measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of outputs. 10.1. Waveforms VCC PULSE GENERATOR VI VM nA input VM VI VO DUT CL 50 pF RT GND t PHL t PLH VOH VM nY output VM VOL mna344 VM = 0.5 × VCC; VI = GND to VCC. Fig. 6. The input (nA) to output (nY) propagation delay times Fig. 7. 74AHCU04_Q100 Product data sheet mna034 Test data is given in Table 7. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Test circuit for measuring switching times All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 5 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 11. Typical transfer characteristics mna353 2 VO VO (V) 700 ICC (µA) 1.5 mna352 4 VO (V) 6 ICC (mA) VO 500 3 1 300 2 2 0.5 100 1 0 4 ICC ICC 0 0 0 0.5 1 1.5 V (V) i 2 - 100 0 Tamb = 25 °C. Fig. 8. 0 1 2 3 Vi (V) -2 Tamb = 25 °C. VCC = 2.0 V; IO = 0 A Fig. 9. mna351 8 VO (V) VCC = 3.0 V; IO = 0 A 30 ICC (mA) 6 20 Rbias = 560 kΩ VCC 4 10 0.47 µF ICC 2 0 input output 100 µF VI (f = 1 kHz) A IO GND VO 0 0 2 Tamb = 25 °C. Fig. 10. VCC = 5.5 V; IO = 0 A 74AHCU04_Q100 Product data sheet mna050 4 Vi (V) 6 - 10 fi = 1 kHz at VO is constant Fig. 11. Test set-up for measuring forward transconductance All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 6 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter mna355 40 g fs (mA/V) 30 20 10 0 0 2 4 VCC (V) 6 Tamb = 25 °C. Fig. 12. Typical forward transconductance as a function of the supply voltage 12. Application information Some applications are: • • Linear amplifier (see Fig. 13) In crystal oscillator design (see Fig. 14) Remark: All values given are typical unless otherwise specified. R2 VCC 1 µF R1 R1 U04 ZL R2 U04 mna052 out Maximum Vo(p-p) = VCC - 1.5 V centered at 0.5 × VCC. Gol = open loop gain Gv = voltage gain R1 ≥ 3 kΩ, R2 ≤ 1 MΩ ZL > 10 kΩ; Gol = 12 (typical) Typical unity gain bandwidth product is 5 MHz. Fig. 13. Used as a linear amplifier 74AHCU04_Q100 Product data sheet C1 C2 mna053 C1 = 47 pF (typical) C2 = 33 pF (typical) R1 = 1 MΩ to 10 MΩ (typical) R2 optimum value depends on the frequency and required stability against changes in VCC or average minimum ICC (ICC is typically 5 mA at VCC = 5 V and fi = 10 MHz). Fig. 14. Crystal oscillator configuration All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 7 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter Table 8. External components for resonator (f < 1 MHz) All values given are typical and must be used as an initial set-up. Frequency R1 R2 C1 C2 10 kHz to 15.9 kHz 22 MΩ 220 kΩ 56 pF 20 pF 16 kHz to 24.9 kHz 22 MΩ 220 kΩ 56 pF 10 pF 25 kHz to 54.9 kHz 22 MΩ 100 kΩ 56 pF 10 pF 55 kHz to 129.9 kHz 22 MΩ 100 kΩ 47 pF 5 pF 130 kHz to 199.9 kHz 22 MΩ 47 kΩ 47 pF 5 pF 200 kHz to 349.9 kHz 10 MΩ 47 kΩ 47 pF 5 pF 350 kHz to 600 kHz 10 MΩ 47 kΩ 47 pF 5 pF Table 9. Optimum value for R2 Frequency R2 3 kHz 6 kHz 10 kHz 14 kHz >14 kHz 74AHCU04_Q100 Product data sheet Optimum for 2.0 kΩ minimum required ICC 8.0 kΩ minimum influence due to change in VCC 1.0 kΩ minimum required ICC 4.7 kΩ minimum influence by VCC 0.5 kΩ minimum required ICC 2.0 kΩ minimum influence by VCC 0.5 kΩ minimum required ICC 1.0 kΩ minimum influence by VCC - replace R2 by C3 with a typical value of 35 pF All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 8 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 15. Package outline SOT108-1 (SO14) 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 9 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 16. Package outline SOT402-1 (TSSOP14) 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 10 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 17. Package outline SOT762-1 (DHVQFN14) 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 11 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MIL Military MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHCU04_Q100 v.3 20200518 Product data sheet - Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 2 updated. Table 4: Derating values for Ptot total power dissipation updated. 74AHCU04_Q100 v.2 20151207 Modifications: • 74AHCU04_Q100 v.1 20130605 74AHCU04_Q100 Product data sheet 74AHCU04_Q100 v.2 Product data sheet - 74AHCU04_Q100 v.1 General description corrected (added "-Q100" to product types (errata)). Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 - © Nexperia B.V. 2020. All rights reserved 12 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 16. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. 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Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 13 / 14 74AHCU04-Q100 Nexperia Hex unbuffered inverter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 3 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................4 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms.................................................................5 11. Typical transfer characteristics................................. 6 12. Application information............................................. 7 13. Package outline.......................................................... 9 14. Abbreviations............................................................ 12 15. Revision history........................................................12 16. Legal information......................................................13 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 May 2020 74AHCU04_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 May 2020 © Nexperia B.V. 2020. All rights reserved 14 / 14