PHT6NQ10T,135

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia Philips Semiconductors Product specification N-channel TrenchMOS transistor FEATURES PHT6NQ10T SYMBOL QUICK REFERENCE DATA • ’Trench’ technology • Low on-state resistance • Fast switching • Low thermal resistance d VDSS = 100 V ID = 6.5 A g RDS(ON) ≤ 90 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect transistor in a plastic envelope using ’trench’ technology. Applications:• Motor and relay drivers • d.c. to d.c. converters PINNING SOT223 PIN DESCRIPTION 1 gate 2 drain 3 source 4 drain (tab) 4 2 1 The PHT6NQ10T is supplied in the SOT223 surface mounting package. 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID ID IDM PD Tj, Tstg CONDITIONS MIN. MAX. UNIT - 65 100 100 ± 20 6.5 3 4.1 1.9 26 8.3 1.8 150 V V V A A A A A W W ˚C Drain-source voltage Tj = 25 ˚C to 150˚C Drain-gate voltage Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Gate-source voltage Continuous drain current (dc) Tsp = 25 ˚C Tamb = 25 ˚C Continuous drain current (dc) Tsp = 100 ˚C Tamb = 100 ˚C Pulsed drain current Total power dissipation Tsp = 25 ˚C Tamb = 25 ˚C Operating junction and storage temperature THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-sp Thermal resistance junction to solder point Thermal resistance junction to ambient surface mounted, FR4 board surface mounted, FR4 board Rth j-amb August 1999 1 TYP. MAX. UNIT 12 15 K/W 70 - K/W Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C RDS(ON) IGSS IDSS Drain-source on-state VGS = 10 V; ID = 3 A resistance Gate source leakage current VGS = ±10 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V; current Tj = 150˚C Tj = 150˚C 100 89 2 1.2 - TYP. MAX. UNIT 3 57 10 0.05 - 4 6 90 216 100 10 500 V V V V V mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 6 A; VDD = 80 V; VGS = 10 V - 21 2.5 8.2 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 50 V; RD = 8.2 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load - 6 15 20 10 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured tab to centre of die Measured from source lead to source bond pad - 2.5 5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 633 103 61 - pF pF pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tsp = 25 ˚C VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM August 1999 MIN. TYP. MAX. UNIT - - 5.5 A - - 26 A IF = 6 A; VGS = 0 V - 0.8 1.2 V IF = 6 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V - 55 135 - ns nC 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T Normalised Power Derating, PD (%) 100 Transient thermal impedance, Zth j-sp (K/W) 100 90 80 D = 0.5 10 0.2 70 0.1 60 1 50 0.05 0.02 40 30 P D tp D = tp/T 0.1 20 single pulse T 10 0.01 1E-06 0 0 25 50 75 100 Solder Point temperature, Tsp (C) 125 150 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tsp) Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T Drain Current, ID (A) 6 Normalised Current Derating, ID (%) 100 VGS = 10V 90 8V 5 80 5.4 V Tj = 25 C 6V 70 5.2 V 5V 4 60 4.8 V 3 50 40 4.6 V 2 30 20 4.4 V 1 10 0 0 25 50 75 100 Solder Point temperature, Tsp (C) 125 0 150 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tsp); VGS ≥ 10 V 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 0.2 RDS(on) = VDS/ ID 1.8 2 Drain-Source On Resistance, RDS(on) (Ohms) 4.6V 4.8V 0.18 tp = 10 us 5V 0.16 10 100 us 5.2 V 0.14 1 ms 5.4 V 0.12 1 D.C. 1.6 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Peak Pulsed Drain Current, IDM (A) 100 0.2 0.1 10 ms 6V 0.08 100 ms 8V 0.06 0.1 VGS = 10V 0.04 0.02 0.01 Tj = 25 C 0 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp August 1999 1 2 3 4 Drain Current, ID (A) 5 6 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T Drain current, ID (A) 4.5 6 VDS > ID X RDS(ON) Threshold Voltage, VGS(TO) (V) 4 5 maximum 3.5 typical 3 4 2.5 3 minimum 2 150 C 1.5 2 Tj = 25 C 1 1 0.5 0 0 0 1 2 3 4 5 6 -60 -40 -20 Gate-source voltage, VGS (V) 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Transconductance, gfs (S) Drain current, ID (A) 1.0E-01 VDS > ID X RDS(ON) 1.0E-02 Tj = 25 C minimum 1.0E-03 150 C typical 1.0E-04 maximum 1.0E-05 1.0E-06 0 1 2 3 4 Drain current, ID (A) 5 0 6 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss 100 Crss 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 0.1 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) August 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T Source-Drain Diode Current, IF (A) 6 Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VGS = 0 V ID = 6A 5 Tj = 25 C 4 VDD = 20 V 150 C 3 VDD = 80 V Tj = 25 C 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Gate charge, QG (nC) 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) August 1999 0.1 5 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T MECHANICAL DATA Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 OUTLINE VERSION e 4.6 e1 HE Lp Q v w y 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-11-11 97-02-28 SOT223 Fig.15. SOT223 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Discrete Semiconductor Packages, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". August 1999 6 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS transistor PHT6NQ10T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification.  Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 7 Rev 1.000