PUMD3,115

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - © Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors; R1 = 10 k, R2 = 10 k Rev. 11 — 25 September 2013 Product data sheet 1. Product profile 1.1 General description NPN/PNP Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic packages. Table 1. Product overview Type number Package JEITA PNP/PNP complement NPN/NPN complement Package configuration NXP PEMD3 SOT666 - PEMB11 PEMH11 ultra small and flat lead PIMD3 SOT457 SC-74 - - small PUMD3 SOT363 SC-88 PUMB11 PUMH11 very small 1.2 Features and benefits  100 mA output current capability  Built-in bias resistors  Simplifies circuit design  Reduces component count  Reduces pick and place costs  AEC-Q101 qualified 1.3 Applications  Low current peripheral driver  Control of IC inputs  Replaces general-purpose transistors in digital applications 1.4 Quick reference data Table 2. Symbol Quick reference data Parameter Conditions Min Typ Max Unit - 50 V Per transistor; for the PNP transistor (TR2) with negative polarity VCEO collector-emitter voltage open base - IO output current - - 100 mA R1 bias resistor 1 (input) 7 10 13 k R2/R1 bias resistor ratio 0.8 1 1.2 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 2. Pinning information Table 3. Pinning Pin Description Simplified outline 1 GND (emitter) TR1 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 5 input (base) TR2 6 output (collector) TR1 6 5 4 Graphic symbol 6 5 R1 4 R2 TR2 1 2 3 TR1 R2 001aab555 1 R1 2 3 006aaa143 3. Ordering information Table 4. Ordering information Type number Package Name Description Version PEMD3 - plastic surface-mounted package; 6 leads SOT666 PIMD3 SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 PUMD3 SC-88 plastic surface-mounted package; 6 leads SOT363 4. Marking Table 5. Type number Marking code[1] PEMD3 D3 PIMD3 M7 PUMD3 D*3 [1] PEMD3_PIMD3_PUMD3 Product data sheet Marking codes * = placeholder for manufacturing site code. All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 10 V VI input voltage TR1 positive - +40 V negative - 10 V positive - +10 V input voltage TR2 negative - 40 V IO output current - 100 mA ICM peak collector current - 100 mA total power dissipation Ptot Tamb  25 C [1] PEMD3 (SOT666) - 200 mW PIMD3 (SOT457) - 250 mW PUMD3 (SOT363) - 200 mW PEMD3 (SOT666) - 300 mW PIMD3 (SOT457) - 400 mW PUMD3 (SOT363) - 300 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C Per device total power dissipation Ptot [1] PEMD3_PIMD3_PUMD3 Product data sheet Tamb  25 C [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac766 500 Ptot (mW) (1) 400 (2) 300 200 100 0 -75 -25 25 75 125 175 Tamb (°C) (1) SOT457; FR4 PCB, standard footprint (2) SOT363 and SOT666; FR4 PCB, standard footprint Fig 1. Per device: Power derating curves 6. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient in free air [1] PEMD3 (SOT666) - - 625 K/W PIMD3 (SOT457) - - 500 K/W PUMD3 (SOT363) - - 625 K/W PEMD3 (SOT666) - - 417 K/W PIMD3 (SOT457) - - 313 K/W PUMD3 (SOT363) - - 417 K/W Per device Rth(j-a) [1] PEMD3_PIMD3_PUMD3 Product data sheet thermal resistance from junction to ambient in free air [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac751 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration for PEMD3 (SOT666); typical values 006aac767 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 102 0.2 0.1 0.05 10 0.02 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for PIMD3 (SOT457); typical values PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 5 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac750 103 duty cycle = 1 Zth(j-a) (K/W) 0.75 0.5 0.33 0.2 102 0.1 0.05 0.02 10 0.01 0 1 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration for PUMD3 (SOT363); typical values PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 6 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 7. Characteristics Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor; for the PNP transistor (TR2) with negative polarity ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 100 nA ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A - - 1 A VCE = 30 V; IB = 0 A; Tj = 150 C - - 5 A IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A - - 400 A hFE DC current gain VCE = 5 V; IC = 5 mA 30 - - VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - - 150 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 A - 1.1 0.8 V VI(on) on-state input voltage VCE = 0.3 V; IC = 10 mA 2.5 1.8 - V R1 bias resistor 1 (input) 7 10 13 k R2/R1 bias resistor ratio 0.8 1 1.2 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - - 2.5 pF - - 3 pF TR1 (NPN) - 230 - MHz TR2 (PNP) - 180 - MHz TR1 (NPN) TR2 (PNP) fT [1] PEMD3_PIMD3_PUMD3 Product data sheet transition frequency VCB = 5 V; IC = 10 mA; f = 100 MHz [1] Characteristics of built-in transistor. All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 7 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac768 103 hFE 006aac769 1 (1) VCEsat (V) (2) (3) 102 10-1 (1) 10 (2) (3) 1 10-1 1 102 10 10-2 1 102 10 IC (mA) IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 100 C (1) Tamb = 100 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 40 C (3) Tamb = 40 C Fig 5. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 6. 006aac770 10 TR1 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 006aac771 10 VI(off) (V) VI(on) (V) (1) (1) (2) 1 (2) 1 (3) 10-1 10-1 1 (3) 102 10 10-1 10-1 IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 100 C (3) Tamb = 100 C TR1 (NPN): On-state input voltage as a function of collector current; typical values PEMD3_PIMD3_PUMD3 Product data sheet 10 IC (mA) (1) Tamb = 40 C Fig 7. 1 Fig 8. TR1 (NPN): Off-state input voltage as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 8 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac772 3 Cc (pF) 006aac757 103 fT (MHz) 2 102 1 0 0 10 20 30 40 50 VCB (V) 10 10-1 102 10 IC (mA) f = 1 MHz; Tamb = 25 C Fig 9. 1 VCE = 5 V; Tamb = 25 C TR1 (NPN): Collector capacitance as a function of collector-base voltage; typical values 006aac773 103 hFE Fig 10. TR1 (NPN): Transition frequency as a function of collector current; typical values of built-in transistor 006aac774 -1 (1) VCEsat (V) (2) (3) 102 -10-1 (1) 10 (2) (3) 1 -10-1 -1 -102 -10 -10-2 -1 IC (mA) IC (mA) VCE = 5 V IC/IB = 20 (1) Tamb = 100 C (1) Tamb = 100 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 40 C (3) Tamb = 40 C Fig 11. TR2 (PNP): DC current gain as a function of collector current; typical values PEMD3_PIMD3_PUMD3 Product data sheet -102 -10 Fig 12. TR2 (PNP): Collector-emitter saturation voltage as a function of collector current; typical values All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 9 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 006aac775 -10 006aac776 -10 VI(off) (V) VI(on) (V) (1) (1) (2) (2) -1 -1 (3) -10-1 -10-1 -1 -102 -10 (3) -10-1 -10-1 -1 IC (mA) -10 IC (mA) VCE = 0.3 V VCE = 5 V (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = 25 C (2) Tamb = 25 C (3) Tamb = 100 C (3) Tamb = 100 C Fig 13. TR2 (PNP): On-state input voltage as a function of collector current; typical values 006aac777 6 Cc (pF) Fig 14. TR2 (PNP): Off-state input voltage as a function of collector current; typical values 006aac763 103 fT (MHz) 4 102 2 0 0 -10 -20 -30 -40 -50 VCB (V) f = 1 MHz; Tamb = 25 C Product data sheet -1 -102 -10 IC (mA) VCE = 5 V; Tamb = 25 C Fig 15. TR2 (PNP): Collector capacitance as a function of collector-base voltage; typical values PEMD3_PIMD3_PUMD3 10 -10-1 Fig 16. TR2 (PNP): Transition frequency as a function of collector current; typical values of built-in transistor All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 10 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 1.7 1.5 6 3.1 2.7 0.6 0.5 5 6 4 1.1 0.9 5 4 2 3 0.6 0.2 0.3 0.1 1.7 1.5 3.0 2.5 1.3 1.1 1.7 1.3 pin 1 index 1 2 1 3 0.18 0.08 0.27 0.17 0.5 pin 1 index 0.40 0.25 0.95 1 0.26 0.10 1.9 Dimensions in mm Dimensions in mm 04-11-08 Fig 17. Package outline PEMD3 (SOT666) 04-11-08 Fig 18. Package outline PIMD3 (SOT457/SC-74) 2.2 1.8 6 2.2 1.35 2.0 1.15 1.1 0.8 5 4 2 3 0.45 0.15 pin 1 index 1 0.3 0.2 0.65 0.25 0.10 1.3 Dimensions in mm 06-03-16 Fig 19. Package outline PUMD3 (SOT363/SC-88) PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 11 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 10. Soldering 3.45 1.95 0.45 0.55 (6×) (6×) 0.95 solder lands solder resist 3.3 2.825 0.95 solder paste occupied area 0.7 (6×) Dimensions in mm 0.8 (6×) 2.4 sot457_fr Fig 20. Reflow soldering footprint PIMD3 (SOT457/SC-74) 5.3 1.5 (4×) solder lands 1.475 0.45 (2×) 5.05 solder resist occupied area 1.475 Dimensions in mm preferred transport direction during soldering 1.45 (6×) 2.85 sot457_fw Fig 21. Wave soldering footprint PIMD3 (SOT457/SC-74) PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 12 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 2.65 solder lands 2.35 1.5 0.4 (2×) 0.6 0.5 (4×) (4×) solder resist solder paste 0.5 (4×) 0.6 (2×) occupied area 0.6 (4×) Dimensions in mm 1.8 sot363_fr Fig 22. Reflow soldering footprint PUMD3 (SOT363/SC-88) 1.5 solder lands 0.3 2.5 4.5 solder resist occupied area 1.5 Dimensions in mm 1.3 1.3 preferred transport direction during soldering 2.45 5.3 sot363_fw Fig 23. Wave soldering footprint PUMD3 (SOT363/SC-88) PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 13 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 2.75 2.45 2.1 1.6 solder lands 0.4 (6×) 0.25 (2×) 0.538 2 1.7 1.075 0.3 (2×) 0.55 (2×) placement area solder paste occupied area 0.325 0.375 (4×) (4×) Dimensions in mm 1.7 0.45 (4×) 0.6 (2×) 0.5 (4×) 0.65 (2×) sot666_fr Fig 24. Reflow soldering footprint PEMD3 (SOT666) PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 14 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 11. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PEMD3_PIMD3_ PUMD3 v.11 20130925 Product data sheet - PEMD3_PIMD3_ PUMD3 v.10 Modifications: PEMD3_PIMD3_ PUMD3 v.10 • • • • • • • • • • Section 1 “Product profile”: updated Section 4 “Marking”: updated Table 6 “Limiting values”: Ptot updated according to the latest measurements Table 7 “Thermal characteristics”: updated according to the latest measurements Table 8 “Characteristics”: ICEO updated according to the latest measurements, fT added Figure 1 to 3, 9, 10, 15 and 16: added Figure 5 to 8 and Figure 11 to 14: updated Section 8 “Test information”: added Section 10 “Soldering”: added Section 12 “Legal information”: updated 20091115 Product data sheet - PEMD3_PIMD3_ PUMD3 v.9 PEMD3_PIMD3_ PUMD3 v.9 20050518 Product data sheet - PEMD3_PIMD3_ PUMD3 v.8 PEMD3_PIMD3_ PUMD3 v.8 20041206 Product data sheet - PEMD3_PUMD3 v.7 PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 15 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors 12. Legal information 12.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PEMD3_PIMD3_PUMD3 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 16 of 18 PEMD3; PIMD3; PUMD3 NXP Semiconductors NPN/PNP resistor-equipped transistors No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 12.4 Trademarks Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PEMD3_PIMD3_PUMD3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 11 — 25 September 2013 © NXP B.V. 2013. All rights reserved. 17 of 18 NXP Semiconductors PEMD3; PIMD3; PUMD3 NPN/PNP resistor-equipped transistors 14. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 9 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Quality information . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 September 2013 Document identifier: PEMD3_PIMD3_PUMD3