KBY00U00VA-B450

Rev. 1.0, Jul. 2010 KBY00U00VA-B450 MCP Specification 8Gb DDP (512M x16) NAND Flash + 4Gb (64M x32 + 64M x32) 2/CS,2CKE DDP Mobile DDR SDRAM datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. -1- KBY00U00VA-B450 datasheet History Draft Date Jun. 10, 2010 Rev. 1.0 MCP Memory Revision History Revision No. 0.0 Remark Preliminay Editor H.J.Min Initial issue. - 8Gb DDP NAND Flash V-die_Ver 0.0 - 4Gb DDP Mobile DDR C-die_Ver 0.2 - Finalized _Ver 1.1 Revision 1.0v 1. Chapter 2.2 Recommended Operating Conditions revised. Revision 1.1v 1. Chapter 2.8 Read / Program / Erase Characteristics Parameter reviesed. _Ver 1.0 - Corrected errata. - Revised DC characteristics. 1.0 Jul. 28, 2010 Final J.S.Ahn -2- KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 1. FEATURES • Operating Temperature : -25°C ~ 85°C • Package : 137 FBGA Type - 10.5mmx13mmx1.2mmt, 0.8mm pitch • Voltage Supply - 1.8V Device : 1.7V ~ 1.95V • Organization - Memory Cell Array : (256M + 8M) x 16bit for 4Gb (512M + 16M) x 16bit for 8Gb DDP - Data Register : (2K + 64) x 16bit • Automatic Program and Erase - Page Program : (2K + 64)Word - Block Erase : (128K + 4K)Word • Page Read Operation - Page Size : (2K + 64)Word - Random Read : 60μs(Max.) (TBD) - Serial Access : 42ns(Min.) • Fast Write Cycle Time - Page Program time : 420μs(Typ.) (TBD) - Block Erase Time : 3ms(Typ.) (TBD) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology -Endurance : TBD Program/Erase Cycles with 4bit/256Word ECC for x16 • Command Driven Operation • Unique ID for Copyright Protection • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle. • Bidirectional data strobe (DQS). • Four banks operation. • Differential clock inputs (CK and CK). • MRS cycle with address key programs. - CAS Latency (3) - Burst Length (2, 4, 8, 16) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs. - Partial Array Self Refresh (Full, 1/2, 1/4 Array) - Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8) • Internal Temperature Compensated Self Refresh. • All inputs except data & DM are sampled at the positive going edge of the system clock (CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • DM for write masking only. • Auto refresh duty cycle. - 7.8us • Clock stop capability • 2/CS, 2CKE Operating Frequency DDR400 Speed @CL3 NOTE : 1) CAS Latency 1) 200MHz Address configuration Organization 64Mx32 64Mx32 /CS CS0 CS1 CKE CKE0 CKE1 Bank BA0,BA1 BA0,BA1 Row A0 - A13 A0 - A13 Column A0 - A9 A0 - A9 - DM is internally loaded to match DQ and DQS identically. -3- KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 2. GENERAL DESCRIPTION The KBY00U00VA is a Multi Chip Package Memory which combines 8Gbit DDP Nand Flash Memory(organized with two pieces of 4Gbit Nand Flash Memory) and 4Gbit DDR synchronous high data rate Dynamic RAM(organized with two pieces of 2Gbit Mobile DDR SDRAM). NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 420μs(TBD) on the (2K+64)Word page and an erase operation can be performed in typical 3ms(TBD) on a (128K+4K)Word block. Data in the data register can be read out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the writeintensive systems can take advantage of the device′s extended reliability of TBD program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. In 4G bit DDP Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The KBY00U00VA is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 137-ball FBGA Type. -4- KBY00U00VA-B450 datasheet 2 DNU CKE1d A4d A5d A8d A11d /RASd /CASd /CS0d BA1d A2d VSSd IO1n IO8n DNU 3 /REn /WPn A7d CKE0d /CS1d DQ15d DQ20d BA0d A10d A3d A13d IO2n IO9n 4 CLEn ALEn A9d DQ18d DQ17d DQ16d DQ21d DQ14d A0d DQ0d NC IO10n IO11n 5 VCCn VSSn DQ25d DQS3d DQ19d DQS1d DQ13d DQ11d DQ7d DQ1d IO3n VCCn IO12n 6 /CEn R/Bn DQ27d DQ22d DQ24d DM1d DQ12d DQ10d DQ8d DQ2d IO5n IO6n VSSn 7 /WEn DQ31d DQ29d DM3d DQ23d DQ9d DQS2d DQS0d DQ6d DQ3d IO14n IO13n IO4n 8 VDDd DQ30d DQ28d DQ26d DM2d CKd /CKd DM0d DQ4d DQ5d IO7n IO15n VDDd - Rev. 1.0 MCP Memory 3. PIN CONFIGURATION A B C D E F G H J K L M N P R 1 NC VSSd VDDd A6d A12d NC VDDd VSSd /WEd A1d VDDd IO0n NC DNU 9 DNU VSSd VDDQd VSSQd VDDQd VSSQd VDDQd VSSd VSSQd VDDQd VDDQd VSSQd VDDQd VSSd DNU 10 DNU NC VSSQd VDDQd VSSQd VDDQd VSSQd VDDd VDDQd VSSQd VSSQd VDDQd VSSQd NC DNU 137 FBGA: Top View (Ball Down) NAND Mobile DRAM Power Ground NC/DNU -5- KBY00U00VA-B450 datasheet Pin Function(Mobile DRAM) Pin Name /CEn /REn /WPn /WEn ALEn CLEn R/Bn IO0n ~ IO15n VCCn VSSn Chip Enable Read Enable Write Protection Write Enable Rev. 1.0 MCP Memory 4. PIN DESCRIPTION Pin Name CKd,/CKd CKE0d,CKE1d /CS0d,/CS1d /RASd /CASd /WEd A0d ~ A13d BA0d ~ BA1d DM0d ~ DM3d DQS0d ~ DQS3d DQ0d ~ DQ31d VDDd VDDQd VSSd VSSQd Pin Function(NAND Flash) Differential System Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Input Bank Address Input Input Data Mask Data Strobe Data Input/Output Power Supply Data Out Power Ground DQ Ground Pin Name DNU NC Do Not Use No Connection Pin Function Address Latch Enable Command Latch Enable Ready/Busy Output Data Input/Output Power Supply Ground -6- KBY00U00VA-B450 datasheet KB Y 00 U 0 0 V A - B 450 Rev. 1.0 MCP Memory 5. ORDERING INFORMATION Samsung MCP Memory(4chips) Device Type NAND + NAND + SDRAM + SDRAM NOR Flash Density, Voltage, Organization, Bank Size, Boot Block 00 : None NAND Flash Density, Voltage, Organization U : 4G NAND*2, 1.8V/1.8V, x16 UtRAM Density, Voltage, Organization 0 : None SRAM Density, Voltage, Organization 0 : None Access Time 450 : NAND Flash 42ns NAND Flash 42ns Mobile DDR SDRAM 5ns Mobile DDR SDRAM 5ns Package B : FBGA(HF, OSP LF) Version A : 2nd Generation DRAM Interface, Density, Voltage, Organization, Option V : Mobile DDR SDRAM, 2G*2, 1.8V/1.8V, x32,2CS/2CKE -7- KBY00U00VA-B450 datasheet VCCn VSSn Rev. 1.0 MCP Memory 6. FUNCTIONAL BLOCK DIAGRAM /CEn /REn /WPn /WEn ALEn CLEn R/Bn 8Gb DDP NAND Flash Memory IO0n to IO15n VDDd VDDQd VSSd VSSQd CKd,/CKd CKE0d,CKE1d /CS0d,/CS1d /RASd /CASd /WEd A0d~A13d BA0d~BA1d DM0d~DM3d DQS0d~DQS3d 4Gb 2CS,2CKE DDP Mobile DDR SDRAM DQ0d to DQ31d -8- KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 7. PACKAGE DIMENSION 137-Ball Fine pitch Ball Grid Array Package (measured in millimeters) Units:millimeters #A1 INDEX MARK 10.50±0.10 0.10 MAX 10.50±0.10 0.80 x 9 = 7.20 10 9 8 7 6 5 4 3 2 1 (Datum A) #A1 A B C D (Datum B) E F G H J K L M N P R 0.32±0.05 1.10±0.10 TOP VIEW 137-∅0.45±0.05 ∅ 0.20 M A B A B 0.80 0.80 x 14 = 11.20 3.60 0.80 13.00±0.10 5.60 BOTTOM VIEW -9- 13.00±0.10 KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 8Gb DDP (512M x16) NAND Flash V-die - 10 - KBY00U00VA-B450 datasheet A13 - A30* X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4,096M + 128M Bit for 4Gb 8,192M + 256M Bit for 8Gb DDP NAND Flash ARRAY Rev. 1.0 MCP Memory VCC VSS A0 - A12 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0 CE RE WE Control Logic & High Voltage Generator Global Buffers I/0 7 CLE ALE WP [Figure 1] Functional Block Diagram 1 Block = 64 Pages (256K + 8K) Byte 2,048 blocks for 4Gb 4,096 blocks for 8Gb DDP 4K Bytes 128 Bytes 1 Page = (4K + 128)Bytes 1 Block = (4K + 128)Byte x 64 Pages = (256K + 8K) Bytes 1 Device = (4K+128)B x 64Pages x 2,048 Blocks = 4,224 Mbits for 4Gb 8 bit 1 Device = (4K+128)B x 64Pages x 4,096 Blocks = 8,448 Mbits for 8Gb DDP Page Register 4K Bytes 128 Bytes I/O 0 ~ I/O 7 [Figure 2] Array Organization [Table 1] Array address (x8) I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A30 is Row address for 8G DDP. In case of 4G Mono, A30 must be set to "Low" I/O 1 A1 A9 A14 A22 *A30 I/O 2 A2 A10 A15 A23 *L I/O 3 A3 A11 A16 A24 *L I/O 4 A4 A12 A17 A25 *L I/O 5 A5 *L A18 A26 *L I/O 6 A6 *L A19 A27 *L I/O 7 A7 *L A20 A28 *L Address Column Address Column Address Row Address Row Address Row Address A0 A8 A13 A21 A29 - 11 - KBY00U00VA-B450 datasheet A12 - A29* X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4,096M + 128M Bit for 4Gb 8,192M + 256M Bit for 8Gb DDP NAND Flash ARRAY Rev. 1.0 MCP Memory VCC VSS A0 - A11 Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS Output Driver I/0 0 CE RE WE Control Logic & High Voltage Generator Global Buffers I/0 15 CLE ALE WP [Figure 3] Functional Block Diagram 1 Block = 64 Pages (128K + 4K)Word 2,048 blocks for 4Gb 4,096 blocks for 8Gb DDP 2K Words 64 Words 1 Page = (2K + 64)Word 1 Block = (2K + 64)Word x 64 Pages = (128K + 4K)Words 1 Device = (2K + 64)Word x 64Pages x 2,048 Blocks = 4,224 Mbits for 4Gb 16 bit 1 Device = (2K + 64)Word x 64Pages x 4,096 Blocks = 8,448 Mbits for 8Gb DDP Page Register 2K Words I/O 0 ~ I/O 15 64 Words [Figure 4] Array Organization [Table 2] Array address (x16) I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A29 is Row address for 8G DDP. In case of 4G Mono, A29 must be set to "Low" I/O 1 A1 A9 A13 A21 *A29 I/O 2 A2 A10 A14 A22 *L I/O 3 A3 A11 A15 A23 *L I/O 4 A4 *L A16 A24 *L I/O 5 A5 *L A17 A25 *L I/O 6 A6 *L A18 A26 *L I/O 7 A7 *L A19 A27 *L I/O 8~I/O 15 *L *L *L *L *L Address Column Address Column Address Row Address Row Address Row Address Row Address Column Address A0 A8 A12 A20s A28 - 12 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 1.0 PRODUCT INTRODUCTION NAND Flash Memory has addresses multiplexed into 8 I/Os(x16 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 3 defines the specific commands of the device. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. [Table 3] Command Sets Function Read Read ID Read for Copy Back Reset Page Program Copy-Back Program Block Erase Random Data Input 1) Random Data Output Read Status NOTE : 1) Random Data Input/Output can be executed in a page. Caution : Any undefined command inputs are prohibited except for above command set of Table 3. 1) 1st Cycle 00h 90h 00h FFh 80h 85h 60h 85h 05h 70h 2nd Cycle 30h 35h 10h 10h D0h E0h - Acceptable Command during Busy O O - 13 - KBY00U00VA-B450 datasheet Symbol VCC VIN VI/O TSTG IOS Rating -0.6 to + 2.45 -0.6 to + 2.45 Rev. 1.0 MCP Memory Unit V °C mA 1.1 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Storage Temperature Short Circuit Current Ios -0.6 to Vcc + 0.3 (< 2.45V) -65 to +100 5 NOTE : 1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods Block Replacement Verify ECC -> ECC Correction ECC : Error Correcting Code --> RS Code or BCH Code etc. Example) 4bit correction & 512-byte NOTE : A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Software scheme such as caching into RAM is recommended. Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Program Completed No Program Error * * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. - 19 - KBY00U00VA-B450 NAND Flash Technical Notes (Continued) Erase Flow Chart datasheet Start Write 60h Write Block Address Write D0h Read Status Register Rev. 1.0 MCP Memory Read Flow Chart Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ? Yes Erase Completed No No Erase Error * Reclaim the Error Verify ECC Yes Page Read Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st (n-1)th nth (page) { { Block A 1 an error occurs. Buffer memory of the controller. Block B 2 1st (n-1)th nth (page) * Step1 When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3 Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4 Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme. ∼ ∼ - 20 - KBY00U00VA-B450 NAND Flash Technical Notes (Continued) datasheet Rev. 1.0 MCP Memory 2.4 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. Page 63 (64) : Page 63 (64) : Page 31 (32) : Page 31 (1) : Page 2 Page 1 Page 0 (3) (2) (1) Page 2 Page 1 Page 0 (3) (32) (2) Data register Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) From the LSB page to MSB page DATA IN: Data (1) Data (64) - 21 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 2.5 System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 4,224byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. ≈ ≈ CE don’t-care ≈≈ ≈ ≈ I/Ox 80h Address(5Cycles) Data Input Data Input ≈ ALE ≈≈ WE ≈≈ CE ≈ CLE 10h tCS CE tCH CE tCEA tREA tWP WE I/Ox [Figure 6] Program Operation with CE don’t-care RE out ≈ CE don’t-care CE RE ALE R/B ≈ ≈≈ ≈ tR I/Ox ≈ WE 00h Address(5Cycle) 30h Data Output(serial access) [Figure 7] Read Operation with CE don’t-care. - 22 - ≈ ≈≈ ≈≈ ≈ CLE KBY00U00VA-B450 NOTE : Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) I/O I/Ox I/O 0 ~ I/O 7 I/O 0 ~ I/O 7 I/O 0 ~ I/O 15 I/O 0 ~ I/O 15 DATA Data In/Out ~4,224byte ~4,224byte ~2,112Word ~2,112Word datasheet ADDRESS Col. Add1 A0~A7 A0~A7 A0~A7 A0~A7 Col. Add2 A8~A12 A8~A12 A8~A11 A8~A11 Row Add1 A13~A20 A13~A20 A12~A19 A12~A19 Rev. 1.0 MCP Memory Row Add2 A21~A28 A21~A28 A20~A27 A20~A27 Row Add3 A29 A29~A30 A28 A28~A29 - 23 - KBY00U00VA-B450 datasheet tCLS tCS tCLH tCH Rev. 1.0 MCP Memory 3.0 TIMING DIAGRAMS 3.1 Command Latch Cycle CLE CE WE tWP tALS ALE tDS I/Ox tALH tDH Command 3.2 Address Latch Cycle tCLS CLE tCS tWC CE tWC tWC tWC tWP WE tALS ALE tDS I/Ox tDH tWH tALH tWP tALS tALH tWH tWP tALS tWH tALH tWP tALS tWH tALH tALS tALH tDS tDH tDS tDH tDS tDH tDS tDH Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 - 24 - KBY00U00VA-B450 datasheet tCLH Rev. 1.0 MCP Memory 3.3 Input Data Latch Cycle ≈ CLE tCH CE tWC ALE tALS WE tDS I/Ox tWH tDH tDS tDH ≈ tWP tWP ≈ tWP tDH tDS ≈ DIN 0 DIN 1 DIN final tRC 3.4 * Serial Access Cycle after Read (CLE=L, WE=H, ALE=L) ≈ CE tREA RE tRHZ I/Ox tRR R/B NOTE : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ≈ ≈ tRP tREH tCHZ tREA tCOH ≈ tREA tRHZ tROH Dout Dout Dout - 25 - ≈ ≈ KBY00U00VA-B450 datasheet tCLR tCLS tCS Rev. 1.0 MCP Memory 3.5 Status Read Cycle CLE tCLH CE tCH tCEA tWHR RE tDS I/Ox 70h tDH tIR tREA tRHZ tRHOH tWP WE tCHZ tCOH Status Output 3.6 Read Operation tCLR CLE CE tWC WE tWB tAR ALE tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 tRC tRHZ 30h ≈≈ ≈ Dout N Dout N+1 Dout M Column Address Row Address Busy R/B - 26 - KBY00U00VA-B450 datasheet tCLR Rev. 1.0 MCP Memory 3.7 Read Operation (Intercepted by CE) CLE CE tCSD WE tWB tAR ALE tR RE tRR I/Ox 00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h tCHZ tCOH tRC Dout N Dout N+1 Dout N+2 Column Address Row Address Busy R/B - 27 - KBY00U00VA-B450 CLE tCLR 3.8 Random Data Output In a Page CE WE tWB tAR tRHW tWHR datasheet - 28 - ALE tR tRC tREA RE tRR Col. Add2 Row Add1 Row Add2 Row Add3 I/Ox Row Address Busy 00h Col. Add1 30h Dout N Dout N+1 05h Col Add1 Col Add2 E0h Dout M Dout M+1 Column Address Column Address R/B Rev. 1.0 MCP Memory KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 3.9 Page Program Operation CLE CE WE tADL ALE tWB tPROG tWHR RE Din Din N M 1 up to m Byte Serial Input I/Ox 80h ≈≈ ≈ tWC tWC tWC Co.l Add1 Col. Add2 Row Add1 Row Add2 Row Add3 10h Program Command 70h Read Status Command I/O0 SerialData Column Address Input Command Row Address ≈ R/B I/O0=0 Successful Program I/O0=1 Error in Program NOTE : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. - 29 - KBY00U00VA-B450 CLE CE tADL tADL ≈ WE ≈ tWC tWC tWC tWB tPROG ALE tWHR 3.10 Page Program Operation with Random Data Input ≈≈ ≈≈ datasheet NOTE : 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. ≈ - 30 Col. Add2 Row Add1 Row Add2 Row Add3 RE I/Ox Row Address 80h 85h Col. Add1 Din N Din M Col. Add1 Col. Add2 Din J Din K Serial Input 10h Program Command 70h Read Status Command I/O0 Serial Data Column Address Input Command Serial Input Random Data Column Address Input Command R/B Rev. 1.0 MCP Memory KBY00U00VA-B450 CLE CE tWHR tPROG tWB tR tRC tADL tWC tWB WE ALE 3.11 Copy-Back Program Operation with Random Data Input ≈≈ ≈≈ datasheet ≈ Busy Copy-Back Data NOTE : Input Command 1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. ≈ - 31 35h Data N Data 1 RE I/Ox 85h Row Address 00h Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Col Add1 Col Add2 Row Add1 Row Add2 Row Add3 Data 1 Data N 10h Row Address 70h I/Ox Read Status Command Column Address Column Address R/B Busy I/O0=0 Successful Program I/O0=1 Error in Program Rev. 1.0 MCP Memory KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 3.12 Block Erase Operation CLE CE tWC WE tWB ALE tBERS tWHR RE I/Ox 60h Row Add1 Row Add2 Row Add3 D0h 70h I/O 0 Row Address Auto Block Erase Setup Command Erase Command ≈ R/B Busy Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase - 32 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 3.13 Read ID Operation CLE CE WE tAR ALE RE tREA I/Ox 90h Read ID Command 00h Address 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Maker Code Device Code Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) Device Code (2nd Cycle) ACh A3h BCh B3h 3rd Cycle 00h 01h 00h 01h 4th Cycle 26h 26h 66h 66h 5th Cycle 56h 5Ah 56h 5Ah 3.13.1 ID Definition Table 90 ID : Access command = 90H Description 1st Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number Page Size, Block Size,Redundant Area Size, Organization Plane Number, Plane Size, ECC Level - 33 - KBY00U00VA-B450 3rd ID Data ITEM datasheet Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not supported supported Not supported supported 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 I/O # 7 6 5 4 3 Rev. 1.0 MCP Memory 2 1 0 0 1 1 0 1 0 1 0 0 1 0 1 Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Interleave Program Between Multii-Chips Cache Program 4th ID Data ITEM Description 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 Reserved Reserved X8 X16 0 or 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O # 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 Page Size (without Redundant Area) Block Size (without Redundant Area) Redundant Area Size (Byte/512byte) Organization Reserved 5th ID Data ITEM Description 1bit ECC/512Byte 2bit ECC/512Byte 4bit ECC/512Byte Reserved 1 2 4 8 64KB 128KB 256KB 512KB 1Gb 2Gb 4Gb 8Gb Reserved 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O # 7 6 5 4 3 2 1 0 0 1 1 0 0 1 0 1 ECC level Plane Number Plane Size (without Redundant Area) Reseved - 34 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.0 DEVICE OPERATION 4.1 PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 4,224 bytes(2,112 Wrods) of data within the selected page are transferred to the data registers in 60μs(tR) typically. The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 42ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. ALE R/B RE I/Ox 00h ≈ ≈≈ WE ≈ CE ≈ CLE tR ≈ Address(5Cycle) Col. Add.1,2 & Row Add.1,2,3 30h Data Output(Serial Access) Data Field Spare Field [Figure 8] Read Operation - 35 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or consecutive byte up to 4,224 Bytes(2,112 Words), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 4,224 Bytes(2,112 Words) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The bytes(words) other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/ O 0) may be checked(Figure 9). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add.1,2,3 Data tPROG "0" 10h 70h I/O0 "1" Fail Pass [Figure 9] Program & Read Status Operation R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data Address & Data Input Col. Add.1,2 Data tPROG "0" 85h 10h 70h I/O0 "1" Fail Pass [Figure 10] Random Data Input In a Page - 36 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.3 COPY-BACK PROGRAM Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 4,224 Bytes(2,112 Words) data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11 & Figure 12). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 12. R/B I/Ox 00h Add.(5Cycles) 35h tR ≈ tPROG ≈ Data Output 85h Add.(5Cycles) 10h 70h I/O0 "1" Fail "0" Pass Col. Add.1,2 & Row Add.1,2,3 Source Address Col. Add.1,2 & Row Add.1,2,3 Destination Address [Figure 11] Page Copy-Back Program Operation NOTE : 1) Copy-Back Program operation is allowed only within the same memory plane. R/B I/Ox 00h Add.(5Cycles) 35h tR ≈ tPROG ≈ Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Col. Add.1,2 Data 10h 70h Col. Add.1,2 & Row Add.1,2,3 Source Address Col. Add.1,2 & Row Add.1,2,3 Destination Address There is no limitation for the number of repetition. [Figure 12] Page Copy-Back Program Operation with Random Data Input - 37 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.4 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only Block address is valid while page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence. R/B I/Ox 60h tBERS "0" Address Input(3Cycle) Row Add 1,2,3 Fail D0h 70h I/O0 "1" Pass [Figure 13] Block Erase Operation 4.5 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/ O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. [Table 4] Status Register Definition for 70h Command I/O I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not Use Not use Not use Not use Not Use Not Use Ready/Busy Write Protect Busy : "0" Protected : "0" Pass : "0" Don’t -cared Don’t -cared Don’t -cared Don’t -cared Don’t -cared Ready : "1" Not Protected : "1" Definition Fail : "1" NOTE : 1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed. - 38 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.6 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence. CLE CE WE tCLR tCEA tAR ALE tWHR RE I/OX 90h 00h Address. 1cycle tREA ECh Device Code Device code 3rd Cyc. 4th Cyc. 5th Cyc. Maker code [Figure 14] Read ID Operation Device 4Gb(x8) 8Gb DDP(x8) 4Gb(x16) 8Gb DDP(x16) Device Code (2nd Cycle) ACh A3h BCh B3h 3rd Cycle 00h 01h 00h 01h 4th Cycle 26h 26h 66h 66h 5th Cycle 56h 5Ah 56h 5Ah 4.7 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 15 below. R/B I/OX FFh tRST [Figure 15] RESET Operation [Table 5] Device Status After Power-up Operation mode Mode 00h Command is latched After Reset Waiting for next command - 39 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4.8 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/ B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig.17). Its value can be determined by the following guidance. Vcc Rp VCC ibusy Ready Vcc R/B open drain output 1.8V device - VOL : 0.1V, VOH : VCC-0.1V VOH CL tf GND Device VOL Busy tr [Figure 16] Rp vs tr ,tf & Rp vs ibusy @ Vcc = 1.8V, Ta = 25°C , CL = 30pF tr,tf [ns] 1.70 2m 346 0.89 259 0.60 173 2.6 2.6 0.45 2.5 Ibusy [A] 400 Ibusy 1m 200 86 2.7 tr tf 1K 2K 3K Rp(ohm) 4K Rp value guidance Rp(min, 1.8V part) = VCC(Max.) - VOL(Max.) IOL + ΣIL = 1.85V 3mA + ΣIL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 40 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 5.0 DATA PROTECTION & POWER UP SEQUENCE The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 1ms is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides additional software protection. ~ 1.5V VCC High ≈ ~ 1.5V WP WE ≈ 5 ms max 1ms Operation Invalid [Figure 17] AC Waveforms for Power Transition Don’t care ≈ Ready/Busy ≈ ≈ Don’t care - 41 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 5.1 WP AC TIMING GUIDE Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: 1. Enable Mode WE I/O WP R/B tww(min.100ns) 80h ≈ 10h 80h 2. Disable Mode WE I/O WP R/B tww(min.100ns) [Figure 18] Program Operation ≈ 10h 60h 1. Enable Mode WE I/O WP R/B tww(min.100ns) ≈ D0h 60h 2. Disable Mode WE I/O WP R/B tww(min.100ns) [Figure 19] Erase Operation ≈ D0h - 42 - KA100O015E-BJTT datasheet Rev. 1.0 MCP Memory 4Gb DDP (64M x32 + 64Mx32) 2/CS Mobile DDR SDRAM C-die - 43 - KA100O015E-BJTT datasheet POWER ON PARTIAL SELF REFRESH SELF REFRESH REFS REFSX EMRS MRS MRS IDLE ALL BANKS PRECHARGED REFA AUTO REFRESH Rev. 1.0 MCP Memory 1.0 FUNCTIONAL DESCRIPTION POWER APPLIED PRECHARGE ALL BANKS CKEL CKEH ACT POWER DOWN POWER DOWN CKEH CKEL WRITE WRITEA READA READ READ ROW ACTIVE BURST STOP READ WRITEA WRITE WRITEA READA WRITEA PRE PRE PRE READA READA PRE PRECHARGE PREALL Automatic Sequence Command Sequence Figure 1. State diagram - 44 - KA100O015E-BJTT datasheet Rev. 1.0 MCP Memory 2.0 MODE REGISTER DEFINITION 2.1 Mode Register Set (MRS) The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on CS, RAS, CAS and WE (The Mobile DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A13 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency (read latency from column address) uses A4 ~ A6, A7 ~ A13 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation. BA1 BA0 A13 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 0 0 RFU1) 0 0 0 CAS Latency BT Burst Length Mode Register A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved Burst Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Reserved 2 4 8 16 Reserved Reserved Reserved Figure 2. Mode Register Set NOTE : 1) RFU (Reserved for future use) should stay "0" during MRS cycle - 45 - KA100O015E-BJTT [Table 1] Burst address ordering for burst length Burst Length 2 Starting Address (A3, A2, A1, A0) xxx0 xxx1 xx00 4 xx01 xx10 xx11 x000 x001 x010 8 x011 x100 x101 x110 x111 0000 0001 0010 0011 0100 0101 0110 16 0111 1000 1001 1010 1011 1100 1101 1110 1111 datasheet Sequential Mode 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 Rev. 1.0 MCP Memory Interleave Mode 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 - 46 - KA100O015E-BJTT datasheet Rev. 1.0 MCP Memory 2.2 Extended Mode Register Set (EMRS) The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1, low on BA0(The Mobile DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A13 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A7 are used for driver strength control. "High" on BA1 and "Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6,A7, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 A13 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 1 0 RFU1) 0 0 DS RFU1) PASR Mode Register DS A7 0 0 0 0 1 1 1 1 NOTE : 1) RFU (Reserved for future use) should stay "0" during EMRS cycle PASR A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Refreshed Area Full Array 1/2 Array 1/4 Array Reserved Reserved Reserved Reserved Reserved Full 1/2 1/4 1/8 3/4 3/8 5/8 7/8 A6 0 0 1 1 0 0 1 1 A5 0 1 0 1 0 1 0 1 Driver Strength Figure 3. Extended Mode Register Set - 47 - KA100O015E-BJTT datasheet Rev. 1.0 MCP Memory 2.3 Internal Temperature Compensated Self Refresh (TCSR) 1. In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the real device temperature. 2. TCSR ranges for IDD6 shown in the table are only examples. 3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Self Refresh Current (IDD6) Temperature Range 85 °C 45 °C NOTE : 1) IDD6 85°C are guaranteed, IDD6 45°C are typical value. Full Array 1700 400 1/2 Array 1400 270 1/4 Array 1200 200 Unit uA 2.4 Partial Array Self Refresh (PASR) 1. In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array. BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 BA1=0 BA0=0 BA1=1 BA0=0 BA1=0 BA0=1 BA1=1 BA0=1 - Full Array - 1/2 Array - 1/4 Array Partial Self Refresh Area Figure 4. EMRS code and TCSR, PASR - 48 - KA100O015E-BJTT datasheet Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value - 0.5 ~ 2.7 - 0.5 ~ 2.7 - 0.5 ~ 2.7 - 55 ~ + 150 1.0 50 Rev. 1.0 MCP Memory 3.0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Unit V V V °C W mA NOTE : 1) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 4.0 DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS=0V, TC = -25°C to 85°C) Parameter Supply voltage (for device with a nominal VDD of 1.8V) I/O Supply voltage Input logic high voltage Address Data Address Data Symbol VDD VDDQ VIH(DC) Min 1.7 1.7 0.8 x VDDQ 0.7 x VDDQ -0.3 -0.3 0.9 x VDDQ -2 -5 Max 1.95 1.95 VDDQ + 0.3 VDDQ + 0.3 0.2 x VDDQ 0.3 x VDDQ 0.1 x VDDQ 2 5 Unit V V V V V V V V uA uA Note 1 1 2 Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current VIL(DC) VOH(DC) VOL(DC) II IOZ 2 IOH = - 0.1mA IOL = 0.1mA 3 NOTE : 1) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 3) Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. - 49 - KA100O015E-BJTT datasheet Symbol IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R Test Condition tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I OUT =0 mA address inputs are SWITCHING; 50% data change each burst transfer Rev. 1.0 MCP Memory 5.0 DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode DDR400 70 1.0 mA 1.0 8 mA 4 6 mA 5 Unit mA Note Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) 15 mA 10 100 mA 80 160 Values 1700 400 1400 270 1200 200 uA uA uA 5 mA 1 Operating Current (Burst Mode) one bank active; BL = 4; tCK = tCKmin; continuous write bursts; IDD4W address inputs are SWITCHING; 50% data change each burst transfer IDD5 tRC ≥ tRFC; tCK = tCKmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE TCSR Range CKE is LOW; t CK = t CKmin; Extended Mode Register set to all 0’s; address and control inputs are STABLE; data bus inputs are STABLE Full Array 1/2 Array 1/4 Array 85°C 45°C 85°C 45°C 85°C 45°C Refresh Current Self Refresh Current IDD6 NOTE : 1) IDD5 is measured in the below test condition. Density tRFC 128Mb 80 256Mb 80 512Mb 110 1Gb 140 2Gb 140 Unit ns 2) IDD specifications are tested after the device is properly initialized. 3) Input slew rate is 1V/ns. 4) Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ; HIGH is defined as V IN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 5) IDD6 85°C are guaranteed, IDD6 45°C are typical value. - 50 - KA100O015E-BJTT datasheet Symbol VIH (AC) VIL (AC) VIX (AC) Min 0.8 x VDDQ -0.3 0.4 x VDDQ Max VDDQ + 0.3 0.2 x VDDQ 0.6 x VDDQ Rev. 1.0 MCP Memory 6.0 AC OPERATING CONDITIONS & TIMMING SPECIFICATION Parameter/Condition Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Input Crossing Point Voltage, CK and CK inputs Unit V V V Note 1 1 2 NOTE : 1) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2) The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. - 51 - KA100O015E-BJTT datasheet Symbol CL=3 tCK tRC tRAS tRCD tRP tRRD tWR tDAL tCDLR tCCD tCH tCL CL=3 CL=3 tAC tDQSCK tDQSQ CL=3 tRPRE tRPST tDQSS tWPRES tWPREH tDQSH tDQSL tDSS tDSH tDSC fast slew rate slow slew rate fast slew rate slow slew rate tIS tIH tIPW fast slew rate slow slew rate fast slew rate slow slew rate tDS tDH tDIPW tLZ tHZ tWPST 0.4 0.9 0.4 0.75 0 0.25 0.4 0.4 0.2 0.2 0.9 0.9 1.1 0.9 1.1 2.2 0.48 0.58 0.48 0.58 1.2 1.0 5 0.6 1.1 0.6 0.6 DDR400 Min 5 55 40 15 15 10 12 2 1 0.45 0.45 2 2 0.55 0.55 5 5 0.4 1.1 0.6 1.25 70,000 Max Rev. 1.0 MCP Memory 7.0 AC TIMMING PARAMETERS & SPECIFICATIONS Parameter Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address delay Clock high level width Clock low level width DQ Output data access time from CK / CK DQS Output data access time from CK / CK Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in low level width DQS falling edge to CK setup time DQS falling edge hold time from CK DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Address & Control input pulse width DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width DQ & DQS low-impedence time from CK / CK DQ & DQS high-impedence time from CK / CK DQS write postamble time Unit ns ns ns ns ns ns ns tCK tCK tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns 7 8 7 8 5 4 3 Note 1,2 ns ns ns ns ns tCK 6,7 6,8 6,7 6,8 - 52 - KA100O015E-BJTT datasheet Parameter Symbol tWPRE tREF tMRD tPDEX tCKE tRFC tXSR tQH tQHS tHP tHP tCLmin or tCHmin tCLmin or tCHmin 2 2 2 120 120 tHPmin - tQHS 0.5 DDR400 Min 0.25 64 Max Rev. 1.0 MCP Memory Unit tCK ms tCK tCK tCK ns ns ns ns ns ns 9 Note DQS write preamble time Refresh interval time Mode register set cycle time Power down exit time CKE min. pulse width (high and low pulse width) Auto refresh cycle time Exit self refresh to active command Data hold from DQS to earliest DQ edge Data hold skew factor Clock half period Clock half period NOTE : 1) tCK (max) value is measured at 100ns. 2) The only time that the clock Frequency is allowed to be changed is during clock stop, power-down, self-refresh modes. 3) In case of below 33MHz (tCK=30ns) condition, SEC could support tDAL (=2*tCK). tDAL =(tWR/tCK) + (tRP/tCK) 4) tAC (min) value is measured at the high Vdd(1.95V) and cold temperature (-25°C). tAC (max) value is measured at the low Vdd(1.7V) and hot temperature (85°C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.6 in next Page). 5) The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 6) I/O Delta Rise/Fall Rate(1/slew-rate) Derating Data Rise/Fall Rate (ns/V) 0 ±0.25 ±0.5 ΔtDS (ps) 0 +50 +100 ΔtDH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. 7) Input slew rate 1.0 V/ ns. 8) Input slew rate 0.5V/ns and < 1.0V/ns. 9) Maximum burst refresh cycle : 8 - 53 - KA100O015E-BJTT datasheet Value 0.8 x VDDQ / 0.2 x VDDQ 0.5 x VDDQ 1.0 0.5 x VDDQ See Figure 6 Rev. 1.0 MCP Memory 8.0 AC OPERATING TEST CONDITIONS (VDD = 1.7V to 1.95V, TC = -25°C to 85°C) Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition Unit V V V/ns V 1.8V 13.9KΩ Output 10.6KΩ 20pF - VOH (DC) = 0.9 x VDDQ, IOH = -0.1mA - VOL (DC) = 0.1 x VDDQ, IOL = 0.1mA Figure 5. DC Output Load Circuit Vtt=0.5 x VDDQ 50Ω Output Z0=50Ω Test load values need to be proportional to the driver strength which is set by the controller. - Test load for Full Driver Strength Buffer (20pF) - Test load for Half Driver Strength Buffer (10pF) Figure 6. AC Output Load Circuit 1), 2) NOTE : 1) The circuit shown above represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half driver strength with a nominal 10pF load parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design / characterization. Use of IBIS or other simulation tools for system design validation is suggested. 2) Based on nominal impedance at 0.5 x VDDQ. The impedence for Half(1/2) Driver Strength is designed 55ohm. And for other Driver Strength, it is designed proportionally. - 54 - KA100O015E-BJTT datasheet Parameter Symbol CIN1 CIN2 COUT CIN3 Min 1.5 1.5 2.0 2.0 Rev. 1.0 MCP Memory 9.0 INPUT/OUTPUT CAPACITANCE (VDD=1.8, VDDQ=1.8V, TC = 25°C, f=100MHz) Max 3.0 3.5 4.5 4.5 Unit pF pF pF pF Input capacitance (A0 ~ A13, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance (CK, CK) Data & DQS input / output capacitance Input capacitance (DM) - 55 - KA100O015E-BJTT datasheet Parameter Rev. 1.0 MCP Memory Specification 0.9V 0.9V 3V-ns 3V-ns 10.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS & CONTROL PINS Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS Maximum Amplitude Overshoot Area Volts (V) VDD VSS Maximum Amplitude Time (ns) Undershoot Area Figure 7. AC Overshoot and Undershoot Definition for Address and Control Pins 11.0 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR CK, DQ, DQS AND DM PINS Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDDQ Maximum undershoot area below VSSQ Maximum Amplitude Overshoot Area Specification 0.9V 0.9V 3V-ns 3V-ns Volts (V) VDDQ VSSQ Maximum Amplitude Time (ns) Undershoot Area Figure 8. AC Overshoot and Undershoot Definition for CK, DQ, DQS and DM Pins - 56 - KA100O015E-BJTT datasheet CKEn-1 H H CKEn X H L H X X CS L L L H L L RAS L L H X L H CAS L L H X H L WE L H H X H H V V BA0,1 Rev. 1.0 MCP Memory 12.0 COMMAND TRUTH TABLE Command Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit A10/AP OP CODE X A13~11, A9~A0 Note 1, 2 3 3 3 3 L H H X Row Address L H L Column Address (A0~A9) Column Address (A0~A9) X V X L H X Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Exit DM No operation (NOP) : Not defined 4 4 4 4, 6 7 H H H X X X L L L H L X H L H L H H L X H X X H X H X L H H X H X X H X H L L L X H X X H X H V H 5 Active Power Down H L H L H L X X L H H H X X H X H X 8 9 9 X H L X H (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) NOTE : 1) OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2) EMRS / MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3) Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4) BA0 ~ BA1 : Bank select addresses. 5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6) During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7) Burst stop command is valid at every burst length. 8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM. - 57 - KA100O015E-BJTT datasheet RAS H H L L L L H H H L L L L H H H L L L L H H CAS H L H H L L H L L H H L L H L L H H L L H L WE L X H L H L L H L H L H L L H L H L H L L H Address X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 Command Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/READA Rev. 1.0 MCP Memory 13.0 FUNCTIONAL TRUTH TABLE Current State CS L L PRECHARGE STANDBY L L L L L L L L L L L L L L L L L L L L Action ILLEGAL 2) ILLEGAL 2) Bank Active, Latch RA ILLEGAL 4) AUTO-Refresh 5) Mode Register Set 5) NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active/ILLEGAL 2) Precharge/Precharge All ILLEGAL ILLEGAL Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge 3) READ ILLEGAL Bank Active/ILLEGAL 2) Terminate Burst, Precharge 10) ILLEGAL ILLEGAL ILLEGAL Terminate Burst With DM=High, Latch CA, Begin Read, Determine Auto-Precharge 3) L WRITE L L L L L L READ with AUTO PRECHARGE6) (READA) L L L L L L L L L H H H L L L L H H L L H L L H H L L H L H L L H L H L H L BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Active PRE/PREA Refresh MRS Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto-Precharge 3) Bank Active/ILLEGAL 2) Terminate Burst With DM=High, Precharge 10) ILLEGAL ILLEGAL ILLEGAL NOTE6 ILLEGAL NOTE6 NOTE6 ILLEGAL ILLEGAL ACTIVE STANDBY - 58 - KA100O015E-BJTT datasheet RAS H H H L L L L H H L L L L H H L L L L H H H L L L L H H L L L L H H L L L L CAS H L L H H L L H L H H L L H L H H L L H L L H H L L H L H H L L H L H H L L WE L H L H L H L L X H L H L L X H L H L L H L H L H L L X H L H L L X H L H L Address X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command Burst Stop READ/READA WRITE/WRITEA Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Burst Stop READ/WRITE Active PRE/PREA Refresh MRS Rev. 1.0 MCP Memory Action ILLEGAL NOTE7 NOTE7 NOTE7 NOTE7 ILLEGAL ILLEGAL ILLEGAL 2) ILLEGAL 2) ILLEGAL 2) NOP 4 )(Idle after tRP) ILLEGAL ILLEGAL ILLEGAL 2) ILLEGAL 2) ILLEGAL 2) ILLEGAL 2) ILLEGAL ILLEGAL ILLEGAL 2) ILLEGAL 2) WRITE ILLEGAL 2) ILLEGAL 2) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Current State CS L L WRITE with AUTO RECHARGE7) (WRITEA) L L L L L L L PRECHARGING (DURING tRP) L L L L L ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L L L L L L L WRITE RECOVERING (DURING tWR OR tCDLR) L L L L L L L REFRESHING L L L L L MODE REGISTER SETTING L L L L L - 59 - KA100O015E-BJTT datasheet CKE n H H H H H L H L H L L L L L L X CS H L L L L X X X X L H L L L L X RAS X H H H L X X X X L X H H H L X CAS X H H L X X X X X L X H H L X X WE X H L X X X X X X H X H L X X X Add X X X X X X X X X X X X X X X X Rev. 1.0 MCP Memory Action Exit Self-Refresh Exit Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) Exit Power Down (Idle after tPDEX) NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down (H=High Level, L=Low level, X=Don′t Care) Current State CKE n-1 L L L L L L L L H H H H H H H L SELFREFRESHING 8) POWER DOWN ALL BANKS IDLE 9) NOTE : 1) All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2) ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. (ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3) Must satisfy bus contention, bus turn around and write recovery requirements. 4) NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5) ILLEGAL if any bank is not idle. 6) Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7) Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8) CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9) Power-Down, Self-Refresh can be entered only from All Bank Idle state. - 60 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory Mobile DDR SDRAM Device Operation & Timing Diagram - 61 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory Device Operations - 62 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 1. PRECHARGE The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. [Table 1] Bank selection for precharge by Bank address bits A10/AP 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Precharge Bank A Only Bank B Only Bank C Only Bank D Only All Banks 2. NO OPERATION(NOP) & DEVICE DESELECT The device should be deselected by deactivating the CS signal. In this mode, Mobile DDR SDRAM should ignore all the control inputs. The Mobile DDR SDRAM is put in NOP mode when CS is activated and RAS, CAS and WE are deactivated. Both Device Deselect and NOP command can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation, the operation will be completed. - 63 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 3. ROW ACTIVE The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock (CK). The Mobile DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time, tRCD(min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between interleaved Bank Activation commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time, tRRD(min). Any system or application incorporating random access memory products should be properly designed, tested and qualifided to ensure proper use or access of such memory products. Disproportionate, excessive and/or repeated access to a particular address or addresses may result in reduction of product life. 0 CK CK Address Bank A Row Addr. Bank A Activate 1 2 3 4 5 Tn Tn+1 Tn+2 Bank A Col. Addr. RAS-CAS delay(tRCD) Write A with Auto Precharge Bank B Row Addr. Bank B Activate Bank A Row. Addr. Bank A Activate RAS-RAS delay time(tRRD) NOP NOP ROW Cycle Time(tRC) NOP Command NOP NOP : Don′t care Figure 1. Bank Activation Command Cycle timing 4. READ BANK This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling (rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS cycle. 5. WRITE BANK This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS cycle. - 64 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 6. BURST READ OPERATION Burst Read operation in Mobile DDR SDRAM is in the same manner as the Mobile SDR SDRAM such that the Burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs determine the starting address for the Burst. The Mode Register sets type of burst (Sequential or interleave) and burst length(2, 4, 8, 16). The first output data is available with a CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by Mobile DDR SDRAM until the burst length is completed. 0 CK CK Command READ A NOP 1 2 3 4 5 6 7 8 NOP NOP NOP NOP NOP NOP NOP tDQSCK DQS Hi-Z tRPRE Preamble tAC DQs Hi-Z tRPST Postamble Dout 0 Dout 1 Dout 2 Dout 3 Figure 2. Burst read operation timing NOTE : 1) Burst Length=4, CAS Latency= 3. - 65 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 7. BURST WRITE OPERATION The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock (CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 0 CK CK Command tDQSS(max) DQS Hi-Z NOP 1 2 3 4 5 6 7 8 WRITEA NOP WRITEB NOP NOP NOP NOP tWR NOP tDQSS(max) tWPREH tWPRES DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3 tDQSS(min) DQS Hi-Z tDQSS(min) tWPRES tWPREH tWR DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 0 Din 1 Din 2 Din 3 tDS tDH Figure 3. Burst write operation timing NOTE : 1) Burst Length=4. 2) The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. - 66 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 8. READ INTERRUPTED BY A READ A Burst Read can be interrupted by new Read command of any bank before completion of the burst. When the previous burst is interrupted, the new address with the full burst length override the remaining address. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. 0 CK CK Command 1 2 3 4 5 6 7 8 tCCD(min) READ READ NOP NOP NOP NOP NOP NOP NOP DQS Hi-Z tDQSCK tRPRE Preamble tRPST Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3 DQs Hi-Z Figure 4. Read interrupted by a read timing NOTE : 1) Burst Length=4, CAS Latency=3 9. READ INTERRUPTED BY A WRITE & BURST STOP To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs (Output drivers) in a high impedance state. 0 CK CK Command READ 1 2 3 4 5 6 7 8 Burst Stop NOP NOP NOP WRITE NOP NOP NOP tDQSCK DQS Hi-Z tRPRE tAC tDQSS tWPREH tRPST tWPRES Dout 0 Dout 1 Din 0 Din 1 Din 2 tWPST Din 3 DQs Hi-Z tWPRE Figure 5. Read interrupted by a write and burst stop timing NOTE : 1) Burst Length=4, CAS Latency=3 . The following functionality establishes how a Write command may interrupt a burst Read. 1. For Write commands interrupting a burst Read, a Burst Terminate command is required to stop the burst read and tri-state the DQ bus prior to valid input write data. Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. - 67 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 10. READ INTERRUPTED BY A PRECHARGE A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. The latency from a precharge command to invalid output is equivalent to the CAS latency. CK CK 0 1 2 3 4 5 6 7 8 1tCK Command READ Precharge NOP NOP NOP NOP NOP NOP NOP DQS Hi-Z tDQSCK tRPRE tAC Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 DQs Hi-Z Interrupted by precharge Figure 6. Read interrupted by a precharge timing NOTE : 1) Burst Length=8, CAS Latency=3 . When a burst Read command is issued to a Mobile DDR SDRAM, a Precharge command may be issued to the same bank before the Read burst is completed. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a burst Read, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (Row Precharge time). 2. When a Precharge command interrupts a burst Read operation, the Precharge command given on a rising clock edge terminates the burst with the last valid data word presented on DQ pins at CL-1(CL=CAS Latency) clock cycles after the command has been issued. Once the last data word has been output, the output buffers are tri-stated. A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with Autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP from rising clock that comes CL(CL=CAS Latency) clock cycles before the end of the Read burst. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK (where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to X.5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock edge).In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. - 68 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 11. WRITE INTERRUPTED BY A WRITE A Burst Write can be interrupted by a new Write command before completion of the burst, where the interval between the successive Write commands must be at least one clock cycle(tCCD(min)). When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. CK CK 0 1 2 3 4 5 6 7 8 tCCD(min) Command NOP WRITE A WRITE b NOP NOP NOP NOP NOP NOP DQS Hi-Z DQs Hi-Z Din A0 Din A1 Din B0 Din B1 Din B2 Din B3 Figure 7. Write interrupted by a write timing NOTE : 1) Burst Length=4. - 69 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 12. WRITE INTERRUPTED BY A PRECHARGE & DM A burst write operation can be interrupted by a precharge of the same bank before completion of the burst. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. 0 CK CK Command tDQSS(max) DQS Hi-Z NOP 1 2 3 4 5 6 7 8 WRITE A NOP NOP NOP NOP tWR PrechargeA WRITE B NOP tDQSS(max) tWPREH tDQSS(max) tWPREH DQs Hi-Z tWPRES Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 tWPRES Dinb0 Dinb1 DM tDQSS(min) DQS Hi-Z tDQSS(min) tWPRES tWPREH tWR tDQSS(min) tWPRES tWPREH DQs Hi-Z Dina0 Dina1 Dina2 Dina3 Dina4 Dina5 Dina6 Dina7 Dinb0 Dinb1 Dinb2 DM Figure 8. Write interrupted by a precharge and DM timing NOTE : 1) Burst Length=8. Precharge timing for Write operations in Mobile DDR SDRAM requires enough time to allow ’write recovery’ which is the time required by a Mobile DDR SDRAM core to properly store a full ’0’ or ’1’ level before a Precharge operation. For Mobile DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the Mobile DDR SDRAM, the data path is eventually synchronized with the address path by switching clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must make reference to only the clock domain that affects internal write operation, i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the precharge command. 1. For the earliest possible Precharge command following a burst Write without interrupting the burst, the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. - 70 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 13. WRITE INTERRUPTED BY A READ & DM A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention Mobile DDR SDRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. 0 CK CK Command tDQSS(max) DQS Hi-Z tWPRES 1 2 3 4 5 6 7 8 9 NOP WRITE NOP NOP NOP tCDLR READ NOP NOP NOP NOP NOP tDQSS(max) DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 Dout2 Dout3 Dout4 DM tDQSS(min) DQS Hi-Z tWPRES tDQSS(min) tCDLR DQs Hi-Z Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout0 Dout1 Dout2 Dout3 Dout4 DM Figure 9. Write interrupted by a Read and DM timing NOTE : 1) Burst Length=8, CAS Latency=3 . The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a burst Write, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed. 2. For Read commands interrupting a burst Write, the DM pin must be used to mask the input data words which immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the Mobile DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS input is ignored by the Mobile DDR SDRAM. 5. Refer to Burst write operation. - 71 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 14. BURST STOP The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. However, the burst stop command is not supported during a burst write operation. 0 CK CK Command READ A 1 2 3 4 5 6 7 8 Burst Stop NOP NOP NOP NOP NOP NOP NOP The burst read ends after a delay equal to the CAS latency. DQS Hi-Z DQs Hi-Z Dout 0 Dout 1 Figure 10. Burst stop timing NOTE : 1) Burst Length=4, CAS Latency= 3. The Burst Stop command is a mandatory feature for Mobile DDR SDRAM. The following functionality is required: 1. The Burst Stop command may only be issued on the rising edge of the input clock, CK. 2. Burst Stop is only a valid command during Read bursts. 3. Burst Stop during a Write burst is undefined and shall not be used. 4. Burst Stop applies to all burst lengths. 5. Burst Stop is an undefined command during Read with autoprecharge and shall not be used. 6. When terminating a burst Read command, the BST command must be issued LBST (“BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The Burst Stop command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). - 72 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 15. DM MASKING The Mobile DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated(DM high) during write operation, Mobile DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe. 0 CK CK Command WRITE NOP 1 2 3 4 5 6 7 8 NOP NOP NOP NOP NOP NOP NOP tDQSS DQS Hi-Z tWPRES tWPREH DQs Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din7 Hi-Z DM masked by DM=H Figure 11. DM masking timing NOTE : 1) Burst Length=8. - 73 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 16. READ WITH AUTO PRECHARGE If A10/AP is high when read command is issued, the read with auto-precharge function is performed. If a read with auto-precharge command is issued, the Mobile DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. 0 CK CK Command BANK A ACTIVE NOP NOP NOP READ A Auto Precharge 1 2 3 4 5 6 7 8 9 10 11 NOP NOP NOP NOP NOP NOP NOP tRP DQS Hi-Z Bank can be reactivated at completion of tRP2) DQs Hi-Z tRAS(min) Dout0 Dout1 Dout2 Dout3 Auto-Precharge starts Figure 12. Read with auto precharge timing NOTE : 1) Burst Length=4, CAS Latency= 3. 2) The row active command of the precharge bank can be issued after tRP from this point. Asserted command READ READ+AP Active Precharge NOTE : 1) AP = Auto Precharge. For same Bank 5 READ +No Illegal Legal AP1) 6 READ+No AP READ + AP Illegal Legal 7 Illegal Illegal Illegal Illegal 5 Legal Legal Legal Legal For Different Bank 6 Legal Legal Legal Legal 7 Legal Legal Legal Legal READ + AP - 74 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 17. WRITE WITH AUTO PRECHARGE If A10/AP is high when write command is issued, the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR(min). 0 CK CK Command BANK A ACTIVE 1 2 3 4 5 6 7 8 9 10 11 12 13 NOP NOP NOP WRITE A Auto Precharge NOP NOP NOP NOP NOP NOP NOP NOP NOP DQS Hi-Z Bank can be reactivated at completion of tRP2) DQs Hi-Z Din 0 Din 1 Din 2 Din 3 tWR Internal precharge start tRP Figure 13. Write with auto precharge timing NOTE : 1) Burst Length=4. 2) The row active command of the precharge bank can be issued after tRP from this point. Asserted command WRITE WRITE+ AP READ READ+AP Active Precharge For same Bank 5 WRITE+ No AP1) WRITE+ AP Illegal Illegal Illegal Illegal 6 WRITE+ No AP WRITE+ AP READ+ NO AP+DM2) READ + AP+DM Illegal Illegal 7 Illegal Illegal READ+ NO AP+DM READ + AP+DM Illegal Illegal 8 Illegal Illegal READ+ NO AP READ + AP Illegal Illegal 9 Illegal Illegal Illegal Illegal Illegal Illegal 10 Illegal Illegal Illegal Illegal Illegal Illegal 5 Legal Legal Illegal Illegal Legal Legal For Different Bank 6 Legal Legal Illegal Illegal Legal Legal 7 Legal Legal Illegal Illegal Legal Legal 8 Legal Legal Legal Legal Legal Legal 9 Legal Legal Legal Legal Legal Legal NOTE : 1) AP = Auto Precharge. 2) DM : Refer to "27. Write Interrupted by Precharge & DM ". - 75 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 18. AUTO REFRESH & SELF REFRESH 18.1. Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. Once this cycle has been started, no control of the external address pins are required because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the tRFC(min). CK CK Command PRE NOP NOP Auto Refresh ∼ ∼∼ NOP NOP NOP ACT NOP NOP CKE = High tRP ∼ tRFC(min) DQ DQS High-Z High-Z Figure 14. Auto refresh timing NOTE : 1) tRP=3CLK 2) Device must be in the all banks idle state prior to entering Auto refresh mode. 18.2. Self Refresh A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including system clock(CK, CK) can be disabled except CKE. The clock is internally disabled during Self Refresh operation to reduce power. Before returning CKE high to exit the Self Refresh mode, apply stable clock input signal with Deselect or NOP command asserted. CK CK Self Refresh ∼∼ ∼∼ Stable Clock NOP NOP NOP ∼∼ Command NOP ∼ NOP Active NOP tRFC tXSR(min) tIS DQ DQS High-Z High-Z ∼ CKE tIS Figure 15. Self refresh timing NOTE : 1) Device must be in the all banks idle state prior to entering Self Refresh mode. 2) The minimum time that the device must remain in Self Refresh mode is tRFC. - 76 - ∼ KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 19. POWER DOWN The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set in high for at least tPDEX prior to Row active command. Refresh operations cannot be performed during power down mode, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. ∼∼ CK CK Command Precharge NOP NOP Precharge power down Entry Precharge power Active down Exit (NOP) Active power down Entry ∼∼ Active power down Exit ∼ ∼∼ ∼ ∼∼ Read tCKE tPDEX tCKE ∼ tIS DQ tIS High-Z tIS ∼ CKE tIS DQS High-Z Figure 16. Power down entry and exit timing NOTE : 1) Device must be in the all banks idle state prior to entering Power Down mode. 2) The minimum power down duration is specified by tCKE. - 77 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 20. CLOCK STOP Stopping a clock during idle periods is an effective method of reducing power consumption. The LPDDR SDRAM supports clock stop under the following conditions : - the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pulses per access command depends on the device’s AC timing parameters and the clock frequency; - the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met; - CKE is held High When all conditions have been met, the device is either in "idle state"or "row active state" and clock stop mode may be entered with CK held Low and CK held Hight. Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command any be applied. Additional clock pulses might be required depending on the system characteristics. Figure shows clock stop mode entry and exit. - Initially the device is in clock stop mode - The clock is restarted with the rising edge of T0 and a NOP on the command inputs - With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command is completed. - Tn is the last clock pulse required by the access command latched with T1 - The clock can be stopped after Tn. T0 CK T1 T2 Tn ~ ~ CK CKE ~~ Timing Condition ~ ~~ ~ ~~~~ Command Address DQ, DQS NOP CMD NOP NOP NOP Valid High-Z ~~~~ Clock Stopped Exit Valid Clock Command Stop Mode Enter clock Stop Mode Figure 17. Clock Stop Mode Entry and Exit - 78 - ∼ = Don’t Care ~ KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory Timing Diagram - 79 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 1. POWER UP SEQUENCE FOR MOBILE DDR SDRAM ≈≈ ≈≈ CK CK CKE HiGH ≈ ≈ ≈ ≈ CS ≈≈ ≈≈ RAS ≈≈ ≈≈ CAS ≈≈ ≈≈ WE ≈≈ ≈≈ ADDR Key Key RAa ≈≈ ≈≈ BA0 ≈≈ ≈≈ BA1 ≈≈ ≈≈ A10/AP Key Key RAa DQs Hi-Z Hi-Z Hi-Z ≈ ≈ ≈ ≈ DM tRP Precharge (All Bank) Auto Refresh tRFC Auto Refresh tRFC Normal MRS Row Active (A-Bank) Extended MRS : Don’t care Figure 18. Power Up Sequence for Mobile DDR SDRAM NOTE : 1) Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. - Apply VDD before or at the same time as VDDQ. 2) Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3) Issue precharge commands for all banks of the devices. 4) Issue 2 or more auto-refresh commands. 5) Issue a mode register set command to initialize the mode register. 6) Issue a extended mode register set command for the desired operating modes after normal MRS. The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. All banks have to be in idle state prior to adjusting MRS and EMRS set. - 80 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 2. BASIC TIMING tCH tCL tCK tCH tCL tCK 0 CK CK CKE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HIGH CS tIS tIH RAS CAS WE BA0, BA1 BAa BAa BAb A10/AP Ra ADDR (A0~An) Ra Ca Cb tDQSS tRPRE tRPST tDSC tDQSL tWPST DQS Hi-Z tDQSCK Hi-Z tWPRES Qa0 Qa1 Qa2 Qa3 Hi-Z tDQSH tWPREH Db0 Db1 Db2 Db3 DQs Hi-Z tAC Hi-Z Hi-Z tQHS tDS tDH DM COMMAND ACTIVE READ WRITE : Don’t care Figure 19. Basic Timing (Setup, Hold and Access Time @BL=4, CL=3) - 81 - KBY00U00VA-B450 datasheet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Rev. 1.0 MCP Memory 3. MULTI BANK INTERLEAVING READ 14 15 CK CK CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb ADDR (A0~An) Ra Rb Ca Cb tRRD DQS Hi-Z tCCD DQs Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 DM tRCD COMMAND ACTIVE ACTIVE READ READ : Don’t care Figure 20. Multi Bank Interleaving READ (@BL=4, CL=3) - 82 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 4. MULTI BANK INTERLEAVING WRITE 0 CK CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb BAa BAb A10/AP Ra Rb ADDR (A0~An) Ra Rb Ca Cb tRRD DQS Hi-Z tCCD DQs Hi-Z Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM tRCD COMMAND ACTIVE ACTIVE WRITE WRITE : Don’t care Figure 21. Multi Bank Interleaving WRITE (@BL=4) - 83 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 5. READ WITH AUTO PRECHARGE 0 CK CK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP Ra ADDR (A0~An) Ca Ra Auto precharge start tRP NOTE1) DQS (CL=3) DQs (CL=3) Hi-Z Hi-Z Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 DM COMMAND READ ACTIVE : Don’t care Figure 22. Read with Auto Precharge (@BL=8) NOTE : 1) The row active command of the precharge bank can be issued after tRP from this point. - 84 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 6. WRITE WITH AUTO PRECHARGE 0 CK CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP Ra ADDR (A0~An) Ca Ra tWR DQS Auto precharge start tRP NOTE1) Hi-Z DQs Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Hi-Z DM COMMAND WRITE ACTIVE : Don’t care Figure 23. Write with Auto Precharge (@BL=8) NOTE : 1) The row active command of the precharge bank can be issued after tRP from this point - 85 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 7. WRITE FOLLOWED BY PRECHARGE 0 CK CK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ca tWR DQS Hi-Z DQs Da0 Da1 Da2 Da3 Hi-Z DM COMMAND WRITE PRE CHARGE : Don’t care Figure 24. Write followed by Precharge (@BL=4) - 86 - KBY00U00VA-B450 datasheet 1 2 3 4 5 6 7 8 9 10 11 Rev. 1.0 MCP Memory 8. WRITE INTERRUPTED BY PRECHARGE & DM 0 CK CK 12 13 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa BAb BAc A10/AP ADDR (A0~An) Ca Cb Cc DQS Hi-Z DQs Hi-Z Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dc4 Dc5 Dc6 Dc7 DM tWR COMMAND WRITE PRE CHARGE tCCD WRITE WRITE : Don’t care Figure 25. Write Interrupted by Precharge & DM (@BL=8) - 87 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 9. WRITE INTERRUPTED BY A READ 0 CK CK 1 2 3 4 5 6 7 8 9 10 11 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) DQS Hi-Z Ca Cb DQs Hi-Z Da0 Da1 Da2 Da3 Da4 Da5 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 Masked by DM DM tCDLR COMMAND WRITE READ : Don’t care Figure 26. Write Interrupted by a Read (@BL=8, CL=3) - 88 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 10. READ INTERRUPTED BY PRECHARGE 0 CK CK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAa A10/AP ADDR (A0~An) Ca DQS Hi-Z 2 tCK Valid DQs Hi-Z Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 DM COMMAND READ PRE CHARGE : Don’t care Figure 27. Read Interrupted by Precharge (@BL=8, CL=3) - 89 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 11. READ INTERRUPTED BY A WRITE & BURST STOP 0 CK CK 1 2 3 4 5 6 7 8 9 10 11 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) Ca Cb DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM COMMAND READ Burst Stop WRITE : Don’t care Figure 28. Read Interrupted by a Write & Burst Stop (@BL=8, CL=3) - 90 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 12. READ INTERRUPTED BY A READ 0 CK CK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa BAb A10/AP ADDR (A0~An) Ca Cb DQS Hi-Z DQs Hi-Z Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7 DM COMMAND READ READ : Don’t care Figure 29. Read Interrupted by a Read (@BL=8, CL=3) - 91 - KBY00U00VA-B450 datasheet Rev. 1.0 MCP Memory 13. DM FUNCTION 0 CK CK 1 2 3 4 5 6 7 8 9 10 CKE HIGH CS RAS CAS WE BA0,BA1 BAa A10/AP ADDR (A0~An) Ca DQS Hi-Z DQs Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Hi-Z DM COMMAND WRITE : Don’t care Figure 30. DM Function (@BL=8) only for write - 92 -