KM681000CL-L

PRELIMINARY KM681000C Family Document Title 128K x8 bit Low Power CMOS Static RAM CMOS SRAM Revision History Revision No. 0.0 0.1 History Initial draft First revision - Seperate read and write at ICC, ICC1 ICC = ICC1 → Read : 15mA, Write : 35mA Finalized - Add 70ns speed bin for commercial product and 85ns speed bin for industrial. Revised - Improved operating current Add typical value. ICC Read : 15mA → 10mA(Remove write current) ICC2 : 90mA → 60mA - Speed bin change Remove 45ns from commercial part Remove 55ns and 100ns from industrial part. Draft Date November 22, 1995 April 15, 1996 Remark Design target Preliminary 1.0 September 5, 1996 Final 2.0 November 5, 1997 Final The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 2.0 November 1997 PRELIMINARY KM681000C Family 128K x8 bit Low Power CMOS Static RAM FEATURES • Process Technology: TFT • Organization: 128K x8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F/R CMOS SRAM GENERAL DESCRIPTION The KM681000C families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby (ISB1, Max) 50µA 10µA 50µA 15µA 60mA 32-SOP 32-TSOP1-F/R Operating (ICC2, Max) PKG Type KM681000CL KM681000CL-L KM681000CLI KM681000CLI-L Commercial(0~70°C) 4.5~5.5V Industrial(-40~85°C) 55/70ns 32-DIP, 32-SOP 32-TSOP1-F/R 70ns PIN DESCRIPTION A11 A9 A8 VCC A13 WE A15 CS2 CS2 A15 VCC WE N.C A13 A16 A14 A8 A12 A9 A7 A6 A11 A5 OE A4 A10 CS 1 A4 A5 A6 A7 I/O6 A12 I/O5 A14 A16 I/O4 N.C VCC A15 CS2 WE A13 A8 A9 A11 I/O8 I/O7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 FUNCTIONAL BLOCK DIAGRAM OE A10 CS 1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Clk gen. Precharge circuit. N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 A4 A5 A6 A7 A8 A12 A13 A14 A15 A16 VCC VSS Memory array 1024 rows 128×8 columns 32-TSOP Type1 - Forward 25 24 23 22 21 20 19 18 17 Row select 32-DIP 32-SOP 25 24 23 22 21 20 19 18 17 32-TSOP Type1 - Reverse 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS 1 A10 OE CS 1 CS2 I/O1 I/O8 Data cont I/O Circuit Column select Data cont A0 A1 A2 A3 A9 A10 A11 Name CS1,CS2 OE WE A0~A16 Function Chip Select Inputs Output Enable Write Enable Address Inputs Name I/O1~I/O8 Vcc Vss N.C Function Data Inputs/OutPower Ground No Connection WE OE Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 2.0 November 1997 PRELIMINARY KM681000C Family PRODUCT LIST Commercial Temperature Products(0~70 °C) Part Name KM681000CLP-5 KM681000CLP-7 KM681000CLP-5L KM681000CLP-7L KM681000CLG-5 KM681000CLG-7 KM681000CLG-5L KM681000CLG-7L KM681000CLT-5L KM681000CLT-7L KM681000CLR-5L KM681000CLR-7L Function 32-DIP, 55ns, L-pwr 32-DIP, 70ns, L-pwr 32-DIP, 55ns, LL-pwr 32-DIP, 70ns, LL-pwr 32-SOP, 55ns, L-pwr 32-SOP, 70ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr 32-TSOP1-R, 55ns, LL-pwr 32-TSOP1-R, 70ns, LL-pwr Industrial Temperature Products(-40~85 °C) Part Name KM681000CLGI-7 KM681000CLGI-7L KM681000CLTI-7L KM681000CLRI-7L Function 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr 32-TSOP1-R, 70ns, LL-pwr CMOS SRAM FUNCTIONAL DESCRIPTION CS 1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X1) WE X1) X1) H H L I/O Pin High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disable Read Write Power Standby Standby Active Active Active 1. X means don′t care(Must be in high or low status.) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN, VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 260°C, 10sec (Lead Only) Unit V V W °C °C °C Remark KM681000CL KM681000CLI - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 2.0 November 1997 PRELIMINARY KM681000C Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 Max 5.5 0 Vcc+0.5 0.8 2) CMOS SRAM Unit V V V V Note 1. Commercial Product : TA=0 to 70°C and Industrial Product :TA=-40 to 85°C, otherwise specified. 2. Overshoot : Vcc+3.0V for≤30ns pulse width. 3. Undershoot : -3.0V for≤30ns pulse width. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled not, 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 6 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) KM681000CL Standby Current (CMOS) KM681000CL-L KM681000CLI KM681000CLI-L ISB1 VOL VOH ISB VIN=Vss to Vcc CS1=VIH or CS 2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read Cycle time=1µs, 100% duty, IIO=0mA, CS 1≤0.2V, CS2≥VCC-0.2V, V IN≤0.2V or VIN≥VCC-0.2V Read Write 2.4 Test Conditions Min -1 -1 Typ 5 2 20 45 1 0.3 1 0.3 Max 1 1 10 5 35 60 0.4 3 50 10 50 15 µA mA V V mA Unit µA µA mA mA Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other input=VIL or VIH CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS 2≤0.2V Other input =0~Vcc Low Power Low Low Power Low power Low Low Power 4 Revision 2.0 November 1997 PRELIMINARY KM681000C Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL CL1) CMOS SRAM 1. Including scope and jig capacitance AC CHARACTERISTICS Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR1,tWR2 tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol VDR 11) Test Condition CS ≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V KM681000CL Vcc=3.0V, CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V Min 2.0 0 5 Typ 1 1 - Max 5.5 20 10 25 10 - Unit V Data retention current IDR KM681000CL-L KM681000CLI KM681000CLI-L µA Data retention set-up Recovery time tSDR tRDR See data retention waveform ms 1. CS1≥Vcc-0.2v, CS2 ≥Vcc-0.2V or CS2 ≤0.2V 5 Revision 2.0 November 1997 PRELIMINARY KM681000C Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA Data Valid CMOS SRAM TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS 1 tHZ(1,2) CS 2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 2.0 November 1997 PRELIMINARY KM681000C Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 2.0 November 1997 PRELIMINARY KM681000C Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) CMOS SRAM tWC Address tAS(3) CS 1 tAW CS 2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS 2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. t CW is measured from the CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CS1≥VCC-0.2V CS1 GND CS2 controlled VCC 4.5V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS 2≤0.2V 8 Revision 2.0 November 1997 PRELIMINARY KM681000C Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) 0.25 +0.10 -0.05 0.004 0.010+0.002 - CMOS SRAM Units: millimeter(inch) #32 #17 13.60 ±0.20 0.535±0.008 #1 42.31 1.666 MAX 41.91 ±0.20 1.650±0.008 #16 3.81±0.20 0.150±0.008 5.08 0.200 MAX 1 5.24 0 .600 0~15° ( 1.91 ) 0.075 0.46±0.10 0.018±0.004 1.52±0.10 0.060±0.004 3.30±0.30 0.130±0.012 2.54 0.100 0.38 MIN 0.015 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #32 #17 14.12 ±0.30 0.556±0.012 11.43±0.20 0.450±0.008 1 3.34 0 .525 #1 20.87 MAX 0.822 20.47±0.20 0.806 ±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX +0.10 0.20 -0.05 0.004 0.008+0.002 - 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX + 0.100 -0.050 +0.004 0.016 -0.002 ( 0.71 ) 0.028 0.41 1.27 0.050 0.05 0.002 MIN 9 Revision 2.0 November 1997 PRELIMINARY KM681000C Family PACKAGE DIMENSIONS 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820F) 0.20 +0.10 -0.05 CMOS SRAM Units: millimeter(inch) 0.004 0.008+0.002 - 20.00±0.20 0.787±0.008 #32 ( 8.00 0.315 0.25 ) 0.010 #1 8.40 0.331 MAX 0.50 0.0197 #16 #17 1.00±0.10 0.039 ±0.004 1.20 0.047 MAX +0.10 -0.05 0.004 0.006+0.002 - 0.05 0.002 MIN 0.25 0.010 TYP 18.40±0.10 0.724 ±0.004 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32 THIN SMALL OUTLINE PACKAGE TYPE1 (0820R) 0.20 +0.10 -0.05 0.004 0.008+0.002 - 20.00±0.20 0.787±0.008 #17 ( 8 .40 0. 331 MAX 8.00 0.315 0.25 ) 0.010 #16 0.50 0.0197 #1 #32 1.00±0.10 0.039±0.004 1.20 0.047 MAX 0.05 0.002 MIN 0.25 0.010 TYP 18.40±0.10 0.724±0.004 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 10 Revision 2.0 November 1997 0.10 MAX 0.004 +0.10 -0.05 0.004 0.006 +0.002 - 0.15 0.10 MAX 0.004