M381L6523BUM-LB3

256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die with 64/72-bit Non ECC/ECC 66 TSOP-II INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM Table of Contents DDR SDRAM 1.0 Ordering Information................................................................................................................... 4 2.0 Operating Frequencies................................................................................................................ 4 3.0 Feature.......................................................................................................................................... 4 4.0 Pin Configuration (Front side/back side) ................................................................................. 5 5.0 Pin Description ............................................................................................................................ 5 6.0 Functional Block Diagram .......................................................................................................... 6 6.1 256MB, 32M x 64 Non ECC Module (M368L3324BT(U)).....................................................................................6 6.2 512MB, 64M x 64 Non ECC Module (M368L6523BT(U)) ....................................................................................7 6.3 512MB, 64M x 72 ECC Module (M381L6523B(U)) ..............................................................................................8 6.4 1GB, 128M x 64 Non ECC Module (M368L2923BT(U)) .......................................................................................9 6.5 1GB, 128M x 72 ECC Module (M381L2923BT(U)) ........................................................................................... 10 7.0 Absolute Maximum Ratings...................................................................................................... 11 8.0 DC Operating Conditions.......................................................................................................... 11 9.0 DDR SDRAM IDD spec table ..................................................................................................... 12 9.1 M368L3324BT(U) [ (32M x 16) * 4, 256MB Non ECC Module ] ............................................................................... 12 9.2 M368L6523BT(U) [ (64M x 8) * 8, 512MB Non ECC Module ] ................................................................................. 12 9.3 M381L6523BT(U) [ (64M x 8) * 9, 512MB ECC Module ] .......................................................................................... 13 9.4 M368L2923BT(U) [ (64M x 8) * 16, 1GB Non ECC Module ] .................................................................................... 13 9.5 M381L2923BT(U) [ (64M x 8) * 18, 1GB ECC Module ] ............................................................................................ 14 10.0 AC Operating Conditions........................................................................................................ 15 11.0 Input/Output Capacitance ....................................................................................................... 15 12.0 AC Timming Parameters & Specifications ............................................................................ 16 13.0 System Characteristics for DDR SDRAM .............................................................................. 17 14.0 Component Notes.................................................................................................................... 18 15.0 System Notes ........................................................................................................................... 19 16.0 Command Truth Table............................................................................................................. 20 17.0 Physical Dimensions............................................................................................................... 21 17.1 32M x 64 (M368L3324BT(U)) ..................................................................................................... 21 17.2 64Mx64 (M368L6523BT(U)) ....................................................................................................... 22 17.3 64Mx72 (M381L6523BT(U)) ....................................................................................................... 23 17.4 128Mx64 (M368L2923BT(U)) ..................................................................................................... 24 17.5 128Mx72 (M381L2923BT(U)) ..................................................................................................... 25 Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM Revision History Revision 0.0 1.0 1.1 Month February August June Year 2003 2003 2005 - First version for internal review - Revision 1.0 spec release. - Deleted “B0, AA, A2” speed and changed master format. History DDR SDRAM Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 184Pin Unbuffered DIMM based on 512Mb B-die (x8, x16) 1.0 Ordering Information Part Number M368L3324BT(U)M-C(L)CC/B3 M368L6523BT(U)M-C(L)CC M368L6523BT(U)N-C(L)B3 M381L6523BT(U)M-C(L)CC/B3 M368L2923BT(U)M-C(L)CC M368L2923BT(U)N-C(L)B3 M381L2923BT(U)M-C(L)CC/B3 Density 256MB 512MB 512MB 1GB 1GB Organization 32M x 64 64M x 64 64M x 72 128M x 64 128M x 72 Component Composition 32Mx16 (K4H511638B) * 4EA 64Mx8 (K4H510838B) * 8EA 64Mx8 (K4H510838B) * 9EA 64Mx8 (K4H510838B) * 16EA 64Mx8 (K4H510838B) * 18EA Height 1,250mil 1,250mil 1,250mil 1,250mil 1,250mil Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free) 2.0 Operating Frequencies CC(DDR400@CL=3) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP 166MHz 200MHz 3-3-3 B3(DDR333@CL=2.5) 133MHz 166MHz 2.5-3-3 3.0 Feature • VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333 • VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400 • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided • SSTL_2 Interface • 66pin TSOP II (Leaded & Pb-Free(RoHS compliant)) package Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 4.0 Pin Configuration (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD *CS2 DQ48 DQ49 VSS *CK2 *CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 DDR SDRAM Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ CS0 CS1 DM5 VSS DQ46 DQ47 *CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Note : 1. * : These pins are not used in this module. 2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module. 3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L2923B ]. 4. Pins 137, 138 are NC for x16 1Row module (M368L3324B). 5.0 Pin Description Pin Name A0 ~ A12 BA0 ~ BA1A DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7(for x72 module) Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name Function DM0 ~7,8(for ECC) Data - in mask Power supply VDD (2.5V for DDR333, 2.6V for DDR400) Power Supply for DQS VDDQ (2.5V for DDR333, 2.6V for DDR400) VSS Ground VREF Power supply for reference VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V ) SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM VDDID VDD, VDDQ level detection NC No connection Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ) Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 6.0 Functional Block Diagram 6.1 256MB, 32M x 64 Non ECC Module (M368L3324BT(U)) (Populated as 1 bank of x16 DDR SDRAM Module) DDR SDRAM CS0 DQS1 DM1 DQ13 DQ14 DQ12 DQ15 DQ9 DQ10 DQ8 DQ11 DQS0 DM0 DQ0 DQ3 DQ4 DQ7 DQ5 DQ2 DQ1 DQ6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS DQS5 DM5 DQ41 DQ42 DQ45 DQ43 DQ44 DQ46 DQ40 DQ47 DQS0 DM0 DQ32 DQ35 DQ36 DQ39 DQ33 DQ38 DQ37 DQ34 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D0 D2 DQS3 DM3 DQ29 DQ26 DQ25 DQ30 DQ28 DQ27 DQ24 DQ31 DQS0 DM0 DQ20 DQ23 DQ16 DQ19 DQ17 DQ22 DQ21 DQ18 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS DQS3 DM3 DQ57 DQ62 DQ56 DQ58 DQ61 DQ63 DQ60 DQ59 DQS0 DM0 DQ48 DQ51 DQ52 DQ50 DQ49 DQ55 DQ53 DQ54 D1 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D3 BA0 - BA1 A0 - A12 RAS CAS CKE0 WE BA0-BA1: DDR SDRAMs D0 - D3 A0-A12: DDR SDRAMs D0 - D3 RAS: DDR SDRAMs D0 - D3 CAS: DDR SDRAMs D0 - D3 CKE: DDR SDRAMs D0 - D3 WE: DDR SDRAMs D0 - D3 Clock Wiring Clock DDR SDRAMs Input CK0/CK0 CK1/CK1 CK2/CK2 NC 2 DDR SDRAMs 2 DDR SDRAMs VDDSPD VDD/VDDQ SPD D0 - D3 D0 - D3 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA VREF VSS D0 - D3 D0 - D3 Notes: 1. DQ-to-I/O wiring is shown as recomended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms + 5% Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 6.2 512MB, 64M x 64 Non ECC Module (M368L6523BT(U)) (Populated as 1 bank of x8 DDR SDRAM Module) DDR SDRAM CS0 DQS0 DM0 DM/ CS DQS DQS4 DM4 DM/ CS DQS Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1 D0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 I/O 7 I/O 4 I/O 1 I/O 3 I/O 6 I/O 5 I/O 0 I/O 2 D4 DM/ CS DQS DM/ CS DQS VDDSPD VDD/VDDQ SPD D0 - D7 D0 - D7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 7 I/O 5 I/O 1 I/O 0 I/O 6 I/O 4 I/O 3 I/O 2 D1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 I/O 6 I/O 4 I/O 3 I/O 1 I/O 7 I/O 5 I/O 2 I/O 0 D5 VREF VSS D0 - D7 D0 - D7 D3/D0/D5 DM/ CS DQS DM/ CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 6 I/O 5 I/O 3 I/O 0 I/O 7 I/O 4 I/O 2 I/O 1 D2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 I/O 7 I/O 5 I/O 1 I/O 0 I/O 6 I/O 4 I/O 3 I/O 2 Cap/Cap/Cap D6 CK0/1/2 R=120Ω Cap/D1/D6 Cap/Cap/Cap D4/D2/C7 CK0/1/2 Card Edge Cap DM/ CS DQS Cap/Cap/Cap DM/ CS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 7 I/O 4 I/O 2 I/O 1 I/O 6 I/O 5 I/O 3 I/O 0 D3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 5 I/O 4 I/O 1 I/O 0 I/O 7 I/O 6 I/O 3 I/O 2 D7 BA0 - BA1 A0 - A12 RAS CAS CKE0 WE BA0-BA1 : DDR SDRAMs D0 - D7 A0-A12 : DDR SDRAMs D0 - D7 RAS : DDR SDRAMs D0 - D7 CAS : DDR SDRAMs D0 - D7 CKE : DDR SDRAMs D0 - D7 WE : DDR SDRAMs D0 - D7 Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 * Clock Wiring DDR SDRAMs 2 DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms + 5% *Clock Net Wiring Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 6.3 512MB, 64M x 72 ECC Module (M381L6523BT(U)) (Populated as 1 bank of x8 DDR SDRAM Module) DDR SDRAM CS0 DQS0 DM0 DM/ CS DQS DQS4 DM4 DM/ CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1 D0 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 I/O 7 I/O 4 I/O 3 I/O 0 I/O 6 I/O 5 I/O 2 I/O 1 D4 SCL WP Serial PD SDA A0 SA0 A1 SA1 A2 SA2 DM/ CS DQS DM/ CS DQS VDDSPD VDD/VDDQ SPD D0 - D8 D0 - D8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 7 I/O 5 I/O 1 I/O 0 I/O 6 I/O 4 I/O 3 I/O 2 D1 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 I/O 6 I/O 4 I/O 3 I/O 2 I/O 7 I/O 5 I/O 1 I/O 0 D5 VREF VSS D0 - D8 D0 - D8 D3/D0/D6 DM/ CS DQS DM/ CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 6 I/O 5 I/O 3 I/O 0 I/O 7 I/O 4 I/O 2 I/O 1 D2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 Cap/Cap/Cap D6 CK0/1/2 R=120Ω D4/D1/D7 Cap/Cap/Cap D5/D2/D8 Cap/Cap/Cap CK0/1/2 Card Edge DM/ CS DQS DM/ CS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 I/O 7 I/O 4 I/O 3 I/O 1 I/O 6 I/O 5 I/O 2 I/O 0 D3 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 5 I/O 4 I/O 1 I/O 0 I/O 7 I/O 6 I/O 3 I/O 2 D7 DM/ CS DQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 5 I/O 4 I/O 3 I/O 1 I/O 7 I/O 6 I/O 2 I/O 0 D8 BA0 - BA1 A0 - A12 RAS CAS CKE0 WE BA0-BA1 : DDR SDRAMs D0 - D8 A0-A12 : DDR SDRAMs D0 - D8 RAS : DDR SDRAMs D0 - D8 CAS : DDR SDRAMs D0 - D8 CKE : DDR SDRAMs D0 - D8 WE : DDR SDRAMs D0 - D8 Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 * Clock Wiring DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms + 5% *Clock Net Wiring Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 6.4 1GB, 128M x 64 Non ECC Module (M368L2923BT(U)) (Populated as 2 bank of x8 DDR SDRAM Module) DDR SDRAM CS1 CS0 DQS0 DM0 DM/ CS DQS DM/ CS DQS DQS4 DM4 DM/ CS DQS DM/ CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D0 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D8 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 I/O 7 I/O 6 I/O 1 I/O 2 I/O 5 I/O 4 I/O 3 I/O 0 D4 I/O 0 I/O 1 I/O 6 I/O 5 I/O 2 I/O 3 I/O 4 I/O 7 D12 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 5 I/O 6 I/O 1 I/O 0 I/O 7 I/O 4 I/O 3 I/O 2 D1 I/O 2 I/O 1 I/O 6 I/O 7 I/O 0 I/O 3 I/O 4 I/O 5 D9 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D5 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D13 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 5 I/O 4 I/O 1 I/O 0 I/O 7 I/O 6 I/O 3 I/O 2 D2 I/O 2 I/O 3 I/O 6 I/O 7 I/O 0 I/O 1 I/O 4 I/O 5 D10 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 I/O 7 I/O 6 I/O 1 I/O 2 I/O 5 I/O 4 I/O 3 I/O 0 D6 I/O 0 I/O 1 I/O 6 I/O 5 I/O 2 I/O 3 I/O 4 I/O 7 D14 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 5 I/O 6 I/O 1 I/O 0 I/O 7 I/O 4 I/O 3 I/O 2 D3 I/O 2 I/O 1 I/O 6 I/O 7 I/O 0 I/O 3 I/O 4 I/O 5 D11 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D7 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D15 D3/D0/D5 VDDSPD SPD Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA VREF VSS VDD/VDDQ D11/D8/D13 D0 - D15 D0 - D15 D0 - D15 D0 - D15 R=120Ω CK0/1/2 CK0/1/2 Card Edge *Cap/D1/D6 * Cap/D9/D14 D4/D2/D7 D12/D10/D15 BA0 - BA1 A0 - A12 RAS CAS CKE 0/1 WE BA0-BA1 : DDR SDRAMs D0 - D15 A0-A12: DDR SDRAMs D0 - D15 RAS : DDR SDRAMs D0 - D15 CAS : DDR SDRAMs D0 - D15 CKE : DDR SDRAMs D0 - D15 WE : DDR SDRAMs D0 - D15 Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 * Clock Wiring DDR SDRAMs 4 DDR SDRAMs 6 DDR SDRAMs 6 DDR SDRAMs Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms + 5% *Clock Net Wiring Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 6.5 1GB, 128M x 72 ECC Module (M381L2923BT(U)) (Populated as 2 bank of x8 DDR SDRAM Module) CS1 CS0 DQS0 DM0 DM/ CS DQS DM/ CS DQS DDR SDRAM DQS4 DM4 DM/ CS DQS DM/ CS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D0 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D9 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D4 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D13 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D1 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D10 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D5 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D14 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D2 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D11 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D6 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D15 DM/ CS DQS DM/ CS DQS DM/ CS DQS DM/ CS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D3 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D7 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D16 DM/ CS DQS DM/ CS DQS CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 D8 I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D17 D3/D0/D5 D12/D9/D14 R=120Ω VDDSPD VDD/VDDQ SPD D8/D1/D6 D17/D10/D15 D4/D2/D7 D13/D11/D16 Serial PD SCL WP A0 SA0 BA0 - BA1 A0 - A12 RAS CAS CKE0/1 WE A1 SA1 A2 SDA CK0/1/2 D0 - D17 D0 - D17 Card Edge VREF D0 - D17 D0 - D17 SA2 VSS BA0-BA1 : DDR SDRAMs D0 - D17 A0-A12 : DDR SDRAMs D0 - D17 RAS : DDR SDRAMs D0 - D17 CAS : DDR SDRAMs D0 - D17 CKE : DDR SDRAMs D0 - D17 WE : DDR SDRAMs D0 - D17 Clock Input *CK0/CK0 *CK1/CK1 *CK2/CK2 * Clock Wiring DDR SDRAMs 6 DDR SDRAMs 6 DDR SDRAMs 6 DDR SDRAMs Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%. 4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms + 5% *Clock Net Wiring Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 7.0 Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN,VOUT VDD,VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 DDR SDRAM Unit V V °C W mA 1.5 * # of component 50 Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 8.0 DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C) Parameter Supply voltage(for device with a nominal VDD of 2.5V for DDR333) Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR333) I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V Symbol VDD VDD VDDQ VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL Min 2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5 Unit V V V V V V V V V V uA uA mA mA mA mA Note 1 2 3 4 Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 9.0 DDR SDRAM IDD spec table 9.1 M368L3324BT(U) [ (32M x 16) * 4, 256MB Non ECC Module ] DDR SDRAM (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) 660 760 20 120 100 220 400 920 1,120 1,060 20 12 1,800 B3(DDR333@CL=2.5) 500 620 20 120 100 120 200 780 860 1,000 20 12 1,620 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.2 M368L6523BT(U) [ (64M x 8) * 8, 512MB Non ECC Module ] (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) 1,320 1,480 40 240 200 440 760 1,600 1,920 2,120 40 24 3,440 B3(DDR333@CL=2.5) 1,000 1,200 40 240 200 240 400 1,320 1,520 2,000 40 24 3,200 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 9.3 M381L6523BT(U) [ (64M x 8) * 9, 512MB ECC Module ] (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) 1,485 1,665 45 270 225 500 855 1,800 2,160 2,385 45 27 3,870 B0(DDR333@CL=2.5) 1,130 1,350 45 270 230 270 450 1,490 1,710 2,250 45 27 3,600 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.4 M368L2923BT(U) [ (64M x 8) * 16, 1GB Non ECC Module ] (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) 2,080 2,240 80 480 400 880 1,520 2,360 2,680 2,880 80 48 4,200 B0(DDR333@CL=2.5) 1,400 1,600 80 480 400 480 800 1,720 1,920 2,400 80 48 3,600 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 9.5 M381L2923BT(U) [ (64M x 8) * 18, 1GB ECC Module ] (VDD=2.7V, T = 10°C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC (DDR400@CL=3) 2,340 2,520 90 540 450 990 1,710 2,655 3,015 3,240 90 54 4,725 B3 (DDR333@CL=2.5) 1,580 1,800 90 540 450 540 900 1,940 2,160 2,700 90 54 4,050 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 10.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 Max DDR SDRAM Unit V V V V Note 3 3 1 2 0.5*VDDQ+0.2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Vtt=0.5*VDDQ RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) 11.0 Input/Output Capacitance Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7, DM8(for ECC)) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 Min 41 34 34 25 6 6 Max 45 38 38 30 7 7 - (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz) M368L3324BT(U) M368L6523BT(U) M381L6523BT(U) Min 49 42 42 25 6 6 Max 57 50 50 30 7 7 Min 51 44 44 25 6 6 6 Max 60 53 53 30 7 7 7 Unit pF pF pF pF pF pF pF Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0,CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7, DM8(for ECC)) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 M368L2923BT(U) Min 65 42 42 28 10 10 Max 81 50 50 34 12 12 - M381L2923BT(U) Min 69 44 44 28 10 10 10 Max 87 53 53 34 12 12 12 Unit pF pF pF pF pF pF pF Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 12.0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.0 Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup time(slow) Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time CL=2.5 CL=3.0 tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 0.4 15 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin tCK DDR SDRAM B3 (DDR333@CL=2.5) Min Max 60 72 70K 42 18 18 12 15 1 12 10 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 +0.65 +0.65 -0.7 -0.7 12 0.45 0.45 2.2 1.75 75 200 7.8 0.5 0.6 0.4 18 (tWR/tCK) + (tRP/tCK) tCK 23 tHP -tQHS tCLmin or tCHmin 7.8 0.55 0.6 +0.7 +0.7 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK us ns ns ns tCK 14 21 20, 21 21 12 j, k j, k 18 18 15, 17~19 15, 17~19 16~19 16~19 11 11 13 22 70K Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR CC (DDR400@CL=3.0) Min Max 55 70 40 15 15 10 15 2 6 5 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.2 0.2 0.35 0.35 0.6 0.6 0.7 0.7 -0.65 -0.65 10 0.4 0.4 2.2 1.75 75 200 Unit ns ns ns ns ns ns ns tCK ns ns Note Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 13.0 System Characteristics for DDR SDRAM DDR SDRAM The following specification parameters are required in systems using DDR333 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR400 MIN TBD MAX TBD DDR333 MIN TBD MAX TBD Units V/ns Notes a, m Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns ∆tIS 0 +50 +100 ∆tIH 0 0 0 Units ps ps ps Notes i i i Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns ∆tDS 0 +75 +150 ∆tDH 0 +75 +150 Units ps ps ps Notes k k k Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns ∆tDS 0 +50 +100 ∆tDH 0 +50 +100 Units ps ps ps Notes j j j Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR400 MIN TBD MAX TBD DDR333 MIN TBD MAX TBD Notes e,m Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 14.0 Component Notes DDR SDRAM 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50Ω Output (Vout) 30pF Figure 1 : Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate ≥ 1.0 V/ns 16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns 17. For CK & CK slew rate ≥ 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers. 22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 15.0 System Notes: a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. DDR SDRAM Test point Output 50Ω VSSQ Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. VDDQ 50Ω Output Test point Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 16.0 Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H H L H H H H All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined L H H X H L H H H L H CKEn X X H L H X X X X X L H L CS L L L L H L L L L L H L X H L H L RAS L L L H X L H H H L X V X X H X V X X H X H X H DDR SDRAM (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) CAS L L L H X H L L H H X V X X H X V WE BA0,1 A10/AP L L H H X H H L L L X V X X H X V X X 8 9 9 X X V X L H V V V A0 ~ A9 A11, A12 Note 1, 2 1, 2 3 3 3 3 OP CODE OP CODE X X Row Address (A0~A9, A11,A12) L H L H X X Column Address Column Address Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection 4 4 4 4, 6 7 5 Burst Stop Precharge Active Power Down Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 1.1 June 2005 256MB, 512MB, 1GB Unbuffered DIMM 17.0 Physical Dimensions 17.1 32M x 64 (M368L3324BT(U)) DDR SDRAM Units : Inches (Millimeters) 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) 1.25 ± 0.006 (31.75 ± 0.15) (2X) 0.157 (4.00±0.1) 0.118 Min (3.00 Min) A B 0.100 (2.30) 2.500 +0.1/-0.0 0.10 M C BA (64.77) 2.55 1.95 (10.00) 0.393 (49.53) 0.100 ± 0.0079 0.250 (6.350) (2.50 ± 0.2 ) 0.039 ± 0.002 (1.000 ± 0.050) 0.118 Min (3.00 Min) 0.0787 R (2.00) 0.1496 (3.80) 0.0078 ±0.006 (0.20 ±0.15) 0.050 (1.270) 0.1575 ± 0.004 (4.00 ± 0.1) 0.10 M C A M B 2.175 0.071 (1.80) Detail A Detail B Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 32Mx16 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H511638B Rev. 1.1 June 2005 0.7 (17.80) 0.098 Max (2.47 Max) 0.050 ± 0.0039 (1.270 ± 0.10) 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 17.2 64Mx64 (M368L6523BT(U)) Units : Inches (Millimeters) 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) 1.25 ± 0.006 (31.75 ± 0.15) (2X) 0.157 (4.00 ± 0.1) 0.118 Min (3.00Min) A B 0.100 (2.30) 2.500 +0.1/-0.0 0.10 M C BA (10.00) 0.393 2.55 1.95 (64.77) (49.53) 0.100 ± 0.0079 0.250 (6.350) (2.50 ± 0.2) 0.039 ± 0.002 (1.000 ± 0.050) 0.0787 R (2.00) 0.0078 ± 0.006 (0.20 ± 0.15) 0.050 (1.270) 0.118 Min (3.00Min) 0.1496 (3.80) 2.175 Detail A 0.071 (1.80) 0.1575 ± 0.004 (4.00 ± 0.1) 0.10 M C A M B Detail B Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 64Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B Rev. 1.1 June 2005 0.7 (17.80) 0.07 Max (1.20 Max) 0.050 ± 0.0039 (1.270 ± 0.10) 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 17.3 64Mx72 (M381L6523BT(U)) Units : Inches (Millimeters) 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) 1.25 ± 0.006 (31.75 ± 0.15) (2X) 0.157 (4.00 ± 0.1) 0.118 Min (3.00 Min) A B 0.100 (2.30) 2.500 +0.1/-0.0 0.10 M C BA (10.00) 0.393 2.55 1.95 (64.77) (49.53) (2.50 ) 0.100 0.250 (6.350) 0.039 ± 0.002 (1.000 ± 0.050) 0.0787 R (2.00) 0.0078 ± 0.006 (0.20 ± 0.15) 0.050 (1.270) 0.118 Min (3.00 Min) 0.1496 (3.80) 2.175 Detail A 0.071 (1.80) 0.1575 ± 0.004 (4.00 ± 0.1) 0.10 M C A M B Detail B Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 64Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B Rev. 1.1 June 2005 0.7 (17.80) 0.07 Max (1.20 Max) 0.050 ± 0.0039 (1.270 ± 0.10) 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 17.4 128Mx64 (M368L2923BT(U)) Units : Inches (Millimeters) 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) 1.25 ± 0.006 (31.75 ± 0.15) (2X) 0.157 (4.00 ± 0.1) 0.118 Min (3.00 Min) A B 0.100 (2.30) 2.500 +0.1/-0.0 0.10 M C BA 2.55 (10.00) 0.393 1.95 (64.77) (49.53) 0.100 ± 0.0079 0.250 (6.350) (2.50 ± 0.2) 0.039 ± 0.002 (1.000 ± 0.050) 0.0787 R (2.00) 0.0078 ± 0.006 (0.20 ± 0.15) 0.050 (1.270) 0.118 Min (3.00 Min) 0.1496 (3.80) 2.175 Detail A 0.071 (1.80) 0.1575 ± 0.004 (4.00 ± 0.1) 0.10 M C A M B Detail B Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 64Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B Rev. 1.1 June 2005 0.7 (17.80) 0.145 Max (3.67 Max) 0.050 ± 0.0039 (1.270 ± 0.10) 256MB, 512MB, 1GB Unbuffered DIMM DDR SDRAM 17.5 128Mx72 (M381L2923BT(U)) Units : Inches (Millimeters) 5.25 ± 0.005 (133.350 ± 0.13) 5.077 (128.950) 1.25 ± 0.006 (31.75 ± 0.15) (2X) 0.157 (4.00 ± 0.1) 0.118 Min (3.00 Min) A B 0.100 ± 0.005 (2.30 ± 0.13) 2.500 +0.1/-0.0 0.10 M C BA 2.55 (10.00) 0.393 1.95 (64.77) (49.53) (2.50 ) 0.100 0.250 (6.350) 0.039 ± 0.002 (1.000 ± 0.050) 0.0787 R (2.00) 0.0078 ± 0.006 (0.20 ± 0.15) 0.050 (1.270) 0.118 Min (3.00 Min) 0.1496 (3.80) 2.175 Detail A 0.071 (1.80) 0.1575 ± 0.004 (4.00 ± 0.1) 0.10 M C A M B Detail B Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 64Mx8 DDR SDRAM, TSOPII. DDR SDRAM Part No : K4H510838B Rev. 1.1 June 2005 0.7 (17.80) 0.145 Max (3.67 Max) 0.050 ± 0.0039 (1.270 ± 0.10)