S3C8465

S3C8465/C8469/P8469 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM8 microcontrollers have an external interface that provides access to external memory and other peripheral devices. A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to one interrupt level at a time. S3C8465/C8469 MICROCONTROLLER The S3C8465/C8469 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter, UART, SIO, ZCD extended PWM application field. Its powerful SAM87 CPU architecture includes. The internal register file is logically expanded to increase the on-chip register space. The S3C8465/C8469 has 16/32K bytes of on-chip program ROM. A sophisticated bus interface enables access to external memory and other peripherals when you use the chip in ROM-less mode. Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core: — Large number of programmable I/O ports (total 56 pins) — One asynchronous UART module — One synchronous SIO module — Analog-to-digital converter with eight input channels and 10-bit resolution — One 8-bit basic timer for watchdog function — One 8-bit timer/counter with three operating modes (timer 0) — One 8-bit timer for zero-cross detection circuit (timer 2) — Two general-purpose 16-bit timer/counters with four operating modes (timer module 1) — PWM block with one capture module, 16-bit timer/counter, PWM extension mode, and two PWM outputs — One zero cross detection module The S3C8465/C8469 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, PWM, capture, SIO, UART and ZCD functions. It is available in a 64-pin SDIP or 64-pin QFP package. OTP The S3P8469 is an OTP (One Time Programmable) version of the S3C8465/C8469 microcontroller. The S3P8469 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P8469 is comparable to the S3C8465/C8469, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C8465/C8469/P8469 FEATURES CPU • SAM87 CPU core Timer/Counters • • Memory • • • 528-byte general purpose register area 16/32K-byte internal program memory ROM-less operating mode • • One 8-bit basic timer for watchdog function One 8-bit timer/counter with three operating modes (timer 0) One 8-bit timer for the zero-cross detection circuit Two 16-bit general-purpose timer/counters with four operating modes (timer C and D) External Interface • • 64K-byte external data memory area 64K-byte external program memory area (ROM-less mode) UART • • One UART module Full duplex serial I/O interface with three UART modes Instruction Set • • 79 instructions IDLE and STOP instructions added for power-down modes A/D Converter • • • Eight analog input pins 10-bit conversion resolution 20 µs conversion time (10 MHz CPU clock) Instruction Execution Time • 500 ns at 12 MHz fOSC (minimum) Zero Cross Detection Circuit • Interrupts • • • 21 interrupt sources and 21 vectors Eight interrupt levels Fast interrupt processing Zero cross detection circuit that generates a digital signal in synchronization with an AC signal input Buzzer Frequency Output • 200 Hz to 20 kHz signal can be generated General I/O • • Seven I/O ports (total 56 pins) Seven bit-programmable ports Oscillator Frequency • • 1 MHz to 12 MHz external crystal oscillator Maximum 12 MHz CPU clock PWM and Capture • • Two 14-bit PWM output One capture Operating Temperature Range • – 40°C to + 85°C Operating Voltage Range Serial I/O • • • One synchronous serial I/O module Selectable transmit and receive rates Selectable baud rate for Rx and Tx respectively Package Types • 64-pin SDIP, 64-pin QFP • 2.7 V to 5.5 V 1-2 S3C8465/C8469/P8469 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 (A8-A15) P1.0-P1.7 (AD0-AD7) P2.0-P2.3 P2.4/ZCD-P2.7/INT3 Basic Timer Port 0 Port 1 Port 0 XIN XOUT T0CK T0 TCG TDG TCCK TDCK PWM0 PWM1 CAPA SI SO SCK RxD TxD ADC0 -ADC7 SAM8 BUS OSC Port 3 Timer P3.0-P3.7 Port I/O and Interrupt Control Timers C and D Port 4 P4.0/INT4P4.7/INT11 PWM/ CAP SAM8 CPU Port 5 P5.0-P5.7 SIO UART 16/32-Kbyte ROM ADC 528-byte Register File Port 6 P6.0-P6.7 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8465/C8469/P8469 PIN ASSIGNMENTS P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7/CAPA P4.2/INT6 P4.1/INT5/RxD VDD VSS XOUT XIN EA P4.0/INT4 P3.7/TxD RESET P3.6/SO P3.5/SI P3.4/SCK P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8465 S3C8469 64-SDIP-750 (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P2.0/AS P2.1/DS P2.2/R/W P2.3/DM P2.4/ZCD P2.5/BUZ Figure 1-2. Pin Assignment Diagram (64-SDIP) 1-4 S3C8465/C8469/P8469 PRODUCT OVERVIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 P0.1/A9 P0.2/A10 P0.3/A11 P0.4/A12 P0.5/A13 P0.6/A14 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7CAPA P4.2/INT6 P4.1/INT5/RxD VDD VSS XOUT XIN EA P4.0/INT4 P3.7/TxD RESET P3.6/SO P3.5/SI P3.4/SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3C8465/C8469 64-QFP-1420F (Top View) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package) P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 P2.5/BUZ P2.4/ZCD P2.3/DM P2.2/R/W P2.1/DS P2.0/AS P6.0 20 21 22 23 24 25 26 27 28 29 30 31 32 1-5 PRODUCT OVERVIEW S3C8465/C8469/P8469 Table 1-1. S3C8465/C8469 Pin Descriptions Pin Name P0.0–P0.7 Pin Type I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or push-pull, open-drain, output. Pull-up resistors are assignable by software. Port 0 can also be configured as external interface address line A8–A15 Same general characteristics as port 0. Port 1 can also be configured as external interface address/data lines AD0–AD7 Bit-programmable I/O port for Schmitt trigger input or push-pull output. P2.0–P2.3 can be configured for external bus control signals. P2.4–P2.7 are used for general I/O or for the ZCD, BUZ, INT2 and INT3 Bit-programmable I/O port for Schmitt trigger input or push-pull output. Each port 3 pin has an alternative function: P3.0: PWM0 (PWM0 module output) P3.1: PWM1 (PWM1 module ouptut) P3.2: T0 (T0 capture input or PWM output) P3.3: T0CK (timer 0 external clock input) P3.4: SCK (SIO module input) P3.5: SI (SIO module clock I/O) P3.6: SO (SIO module output) P3.7: TxD: SO1 (The T0 function for P3.2 is selected using the T0CON register.) Bit-programmable I/O port for Schmitt trigger input or push-pull output. Port 4 pins are used external interrupts INT4–INT11 or for the following share functions: P4.1: RxD (UART module input) P4.3: CAPA (capture input) P4.4: TCCK (timer/counter C clock input) P4.5: TDCK (timer/counter D clock input) P4.6: TCG (timer C gate input) P4.7: TDG (timer D gate input) Circuit Number 1 Pin Number 8–1 (1, 64–58) Share Pins – A8–A15 P1.0–P1.7 I/O 1 64–57 (57–50) 38–35 (31–28) 34–31 (27–24) 30–22 (23–15) – AD0–AD7 – AS, DS DM, R/W ZCD, BUZ INT2, INT3 (See pin description) P2.0–P2.3 I/O 2 P2.4–P2.7 P3.0–P3.7 I/O 3 4 P4.0–P4.7 I/O 5 21, 15–9 (14–2) (See pin description) 1-6 S3C8465/C8469/P8469 PRODUCT OVERVIEW Table 1-1. S3C8465/C8469 Pin Descriptions (Continued) Pin Name P5.0–P5.7 Pin Type I/O Pin Description Bit-programmable I/O port for Schmitt trigger input or push-pull, output. Pull-up resistors are assignable by software. Port 5 pins can also be used as A/D converter inputs. Individual pins are software configurable as input or push-pull, open-drain, output. Pull-up resistors are assignable by software. External interface address/data line External bus control signals Circuit Number 6 Pin Number 49–56 (42–49) Share Pins ADC0– ADC7 P6.0–P6.7 I/O 1 39–46 (32–39) 64–57 (57–50) 38–35 (31–28) – AD0–AD7 AS DS R/W DM ZCD BUZ PWM0 PWM1 T0 (CAP) T0CK SCK SI, SO TxD INT2–INT3 INT4 RxD/INT5 INT6 CAPA/INT7 I/O I/O 6 2 P1.0–P1.7 P2.0–P2.3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Zero cross detector input 200 Hz–20 kHz frequency output for buzzer sound PWM output T0 capture input or PWM output External clock input for Timer 0 SIO clock signal SIO data input/output UART data output External interrupts: the triggering edge is selectable. External interrupts: the triggering edge is selectable. UART data input or external interrupt: the triggering edge is selectable. Capture module input or external interrupt: the triggering edge is selectable. 2 2 3 3 3 3 3 3 2 4 4 4 34 (27) 33 (26) 30, 29 (23, 22) 28 (21) 27 (20) 26 (19) 25, 24 (18, 17) 22 (15) 32, 31 (25, 24) 21 (14) 15 (8) 14,13 (7, 6) P2.4 P2.5 P3.0–P3.1 P3.2 P3.3 P3.4 P3.5–P3.6 P3.7 P2.6–P2.7 P4.0 P4.1 P4.2–P4.3 1-7 PRODUCT OVERVIEW S3C8465/C8469/P8469 Table 1-1. S3C8465/C8469 Pin Descriptions (Concluded) Pin Name TCCK/INT8 TCDK/INT9 TCG/INT10 TDG/INT11 ADC0– ADC7 XIN, XOUT RESET EA Pin Type I/O I/O I/O – I I Pin Description Timer/counter C and D clock input or external interrupts: the triggering edge is selectable. Timer/counter C and D clock input or external interrupts: the triggering edge is selectable. A/D converter inputs System clock input and output pins System reset pin External access (EA) pin with three modes: 0 V: Normal operation (internal ROM) 5 V: ROM-less operation (external interface) 12.5 V: OTP read/write mode A/D converter reference voltage input and ground Voltage input pin and ground Circuit Number 4 4 5 – 7 – Pin Number 12, 11 (5, 4) 10, 9 (3, 2) 49–56 (42–49) 19, 18 (12, 11) 23 (16) 20 (13) Share Pins P4.4–P4.5 P4.6–P4.7 P5.0–P5.7 – – – AVREF, AVSS VDD ,VSS – – – – 47, 48 (40, 41) 16, 17 (9, 10) – – NOTE: Pin numbers shown in parentheses "( )" are for the 64-pin QFP package. 1-8 S3C8465/C8469/P8469 PRODUCT OVERVIEW PIN CIRCUITS Table 1-2. Pin Circuit Assignments for the S3C8465/C8469 Circuit Number 1 2 3 4 5 6 7 Circuit Type I/O I/O I/O I/O I/O I/O I S3C8465/C8469 Assignments Port 0,1 and port 6 Port 2 (P2.0–P2.3 only) Port 2 (P2.4–P2.7 only) Port 3 Port 4 Port 5 RESET NOTE: Diagrams of circuit types 1–7 are presented below. 1-9 PRODUCT OVERVIEW S3C8465/C8469/P8469 VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Open-drain Output DIsable In Figure 1-4. Pin Circuit Type 1 (Port 0,1 and Port 6) VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 2 (Low Byte) Data External Interface (AS, DS, R/W, DM) Select M U X Data VDD In/Out Output DIsable In Figure 1-5. Pin Circuit Type 2 (Port 2, P2.0–P2.3 only) 1-10 S3C8465/C8469/P8469 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 2 (High Byte) Data Control Output (BUZ) Select M U X VDD In/Out Output DIsable External Interrupt Input Normal Input ZCD Input Noise Filter Figure 1-6. Pin Circuit Type 3 (Port 2, P2.4–P2.7 only) 1-11 PRODUCT OVERVIEW S3C8465/C8469/P8469 VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable Port 3 Control Output Select M U X Data VDD In/Out Output DIsable Normal Input Figure 1-7. Pin Circuit Type 4 (Port 3) VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Output DIsable External Interrupt Input Alternative Input Normal Input Noise Filter Figure 1-8. Pin Circuit Type 5 (Port 4) 1-12 S3C8465/C8469/P8469 PRODUCT OVERVIEW VDD Pull-up Resistor (Typical Value: 47 KΩ) Pull-up Enable VDD Data In/Out Output DIsable Normal Input Analog Input Figure 1-9. Pin Circuit Type 6 (Port 5) VDD Pull-up Resistor (Typical Value: 200 KΩ) RESET Figure 1-10. Pin Circuit Type 7 (RESET) 1-13 S3C8465/C8469/P8469 ELECTRICAL DATA 19 OVERVIEW ELECTRICAL DATA In this chapter, S3C8465/C8469 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — Serial I/O timing characteristics — UART timing characteristics in mode 0 — A/D converter electrical characteristics — Zero crossing detector — External memory timing characteristics 19-1 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL All input ports All output ports One I/O pin active All I/O pins active Output Current Low One I/O pin active Total pin current for ports 0, 2–4, and 6 Total pin current for ports 1 and 5 Operating Temperature Storage Temperature TA TSTG – – Conditions – Rating – 0.3 to + 6.5 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 18 – 60 + 30 + 100 + 200 – 40 to + 85 – 65 to + 150 °C °C Unit V V V mA mA Table 19-2. Input/Output Capacitance (TA = – 40°C to 85°C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are tied to VSS Min – Typ – Max 10 Unit pF 19-2 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-3. D.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage VIL1 VIL2 Output High Voltage VOH Conditions VDD = 2.7 V to 5.5 V All Port and RESET VDD = 4.5 V to 5.5 V XIN and XOUT VDD = 2.7 V to 5.5 V All Ports and RESET VDD = 4.5 V to 5.5 V XIN and XOUT VDD = 4.5 V to 5.5 V IOH = – 1 mA All Ports VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 1,5, and 6 VDD = 4.5 V to 5.5 V IOL = 4 mA Ports 0, 2, 3, and 4 VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XOUT VIN = 0 V All input pins except and ILIL2 and RESET VIN = 0 V XIN, XOUT VOUT = VDD All output pins VOUT = 0 V All output pins – – – – – – – – 1 20 –1 µA µA VDD – 1.0 – Min 0.8 VDD VDD – 1.0 – – 0.2 VDD 0.1 – V V Typ – Max VDD Unit V Output Low Voltage VOL1 – 0.4 2.0 V VOL2 Input High Leakage Current ILIH1 ILIH2 Input Low Leakage Current ILIL1 ILIL2 Output High Leakage Current Output Low Leakage Current ILOH1 ILOL – 20 2 –2 µA µA 19-3 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-3. D.C. Electrical Characteristics (Continued) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Pull-up Resistor Symbol RP1 RP2 Conditions VDD = 5 V; VIN = 0 V VDD = 3 V; Ports 0–6 VDD = 5 V; VIN = 0 V VDD = 3 V; RESET only Supply Current (note) Min 30 30 100 200 – Typ 47 – 200 400 16 Max 70 350 400 800 30 Unit kΩ IDD1 VDD = 4.5 V to 5.5 V RUN mode 12 MHz CPU clock VDD = 2.7 V to 3.3 V 8 MHz CPU clock mA 5.5 3 12 6 IDD2 VDD = 4.5 V to 5.5 V Idle mode 12 MHz CPU clock VDD = 2.7 V to 3.3 V 8 MHz CPU clock 1 1 2.5 5 µA IDD3 VDD = 4.5 V to 5.5 V Stop mode VDD = 2.7 V to 3.3 V Stop mode NOTE: Supply current does not include current drawn through internal pull-up resistors, ZCD, ADC and external output current loads. Table 19-4. A.C. Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Interrupt Input High, Low Width RESET Input Low Width Symbol tINTH, tINTL tRSL Conditions Ports 2, 3, and 4 Input Min – – Typ 270 1500 Max – – Unit ns ns tINTL tRSL 0.8 VDD 0.2 VDD tINTH Figure 19-1. Input Timing Measurement Points 19-4 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-5. Oscillation Characteristics (TA = – 40°C + 85°C) Oscillator Main Crystal or Ceramic XIN XOUT Clock Circuit Test Condition VDD = 4.5 V to 5.5 V VDD = 2.7 V to 4.5 V Min 1 1 Typ – – Max 12 8 Unit MHz C1 C2 External Clock (Main System) XIN XOUT VDD = 4.5 V to 5.5 V VDD = 2.7 V to 4.5 V 1 1 – – 12 8 MHz CPU Clock 12 kHz Main Oscillator Frequency 8 kHz 1 kHz 1 2 3 2.7 V Supply Voltage (V) 4 5 5.5 V 6 7 Figure 19-2. Operating Voltage Range 19-5 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-6. Oscillation Stabilization Time (TA = – 40°C + 85°C, VDD = 2.7 V to 5.5 V) Oscillator Main Crystal Main Ceramic External Clock (Main System) Oscillator Stabilization Wait Time f OSC > 400 kHz; Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) tWAIT when released by a reset (1) Test Condition Min – – 25 – Typ – – – 216/fOSC Max 20 10 500 – Unit ms ms ns ms tWAIT when released by an interrupt (2) – – – ms NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 19-6 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-7. Data Retention Supply Voltage in Stop Mode (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter Data Retention Supply Voltage Data Retention Supply Current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 – Typ – – Max 5.5 5 Unit V µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. RESET occurs Stop Mode Data Retention Mode Oscillation Stabilzation Time ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT Normal Operating Mode NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. Figure 19-3. Stop Mode Release Timing When Initiated by a Reset 19-7 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-8. Serial I/O Timing Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Parameter SCK Cycle Time SCK High, Low Width SI Setup Time to SCK Low SI Hold Time to SCK High Output Delay for SCK to SO Symbol tCKY tKH, tKL tSIK tKSI tKSO Conditions External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source Min 1000 1000 500 tKCY/2 – 50 250 250 400 400 – – 300 250 – – – – – – Typ – Max – Unit ns NOTE: "SCK" means serial I/O clock frequency, "SI" means serial data input, and "SO" means serial data output. tKCY tKL SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO tKH SO Output Data Figure 19-4. Serial Data Transfer Timing 19-8 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-9. UART Timing Characteristics in Mode 0 (10 MHz) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, Load capacitance = 80 pF) Parameter Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge Serial port clock High, Low level width Symbol tSCK tS1 tS2 tH1 tH2 tHIGH, tLOW Min 500 300 – tCPU – 50 0 200 Typ tCPU × 6 tCPU × 5 – tCPU – tCPU × 3 Max 700 – 300 – – 400 Unit ns NOTES: 1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency. 2. The unit tCPU means one CPU clock period. tSCK tHIGH tLOW 0.8 VDD 0.2 VDD Figure 19-5. Waveform for UART Timing Characteristics 19-9 S3C8465/C8469/P8469 tSCK Shift Clock tH1 tS1 Data Out D0 D1 D2 D3 D4 D5 D6 D7 tS2 Data In VALID VALID tH2 VALID VALID VALID VALID VALID VALID NOTE: The symbols shown in this diagram are defined as follows: fSCK tS1 tS2 tH1 tH2 Serial port clock cycle time Output data setup to clock rising edge Clock rising edge to input data valid Output data hold after clock rising edge Input data hold after clock rising edge ELECTRICAL DATA Figure 19-6. A.C. Timing Waveform for the UART Module 19-10 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-10. A/D Converter Electrical Characteristics (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Symbol Test Conditions VDD = 5.12 V Min – – Typ 10 – – – ±1 ± 0.5 Max – ±3 ±2 ±1 ±3 ±2 – AVREF – VDD Unit bit LSB ILE DLE EOT EOB tCON VIAN RAN AVREF CPU clock = 10 MHz AVREF = 5.12 V AVSS = 0 V 10-bit conversion 50 x 4/fOSC (3), fOSC = 10 MHz – – – 20 AVSS 2 2.5 – – – – µs V MΩ V Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) AVSS IADIN IADC – AVREF = VDD = 5 V conversion time = 20 µs AVREF = VDD = 5 V conversion time = 20 µs AVREF = VDD = 3 V conversion time = 20 µs AVREF = VDD = 5 V when power down mode VSS – – – 1 0.5 100 VSS + 0.3 10 3 1.5 500 V µA mA mA nA NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 19-11 ELECTRICAL DATA S3C8465/C8469/P8469 Table 19-11. Zero Crossing Detector (TA = – 40°C to + 85°C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Zero-crossing detection input frequency Symbol VZC Test Conditions AC connection c = 0.1 µF f ZC = 60 Hz (sine wave) VDD = 5 V f OSC = 10 MHz – Min 1.0 Typ – Max 3.0 Unit Vp-p VAZC – – ± 150 mV f ZC 40 – 200 Hz 1/fzc AC input VAZC VAZ (P-P) ZCINT Figure 19-7. Zero Crossing Waveform Diagram 19-12 S3C8465/C8469/P8469 ELECTRICAL DATA Table 19-12. External Memory Timing Characteristics (8 MHz) (TA = – 40°C to + 85°C, VDD = 2.7 V to 5.5 V) Number 1 2 3 4 5 6a 6b 7 8 9 10 11 12 13 Symbol tdA (AS) tdAS (A) tdAS (DR) twAS tdA (DS) twDS (read) twDS (write) tdDS (DR) thDS (DR) tdDS (A) tdDS (AS) tdDO (DS) tdRW (AS) tdDS (DW) Parameter Address valid to AS ↑ delay AS ↑ to address float delay AS ↑ to read data required valid AS Low width Address float to DS ↓ DS (read) Low width DS (write) Low width DS ↓ to read data required valid Read data to DS ↑ hold time DS ↑ to address active delay DS ↑ to AS ↓ delay Write data valid to DS (write) ↓ delay R/W valid to AS ↑ delay DS ↑ to write data not valid delay Normal Timing (ns) Min 10 35 – 43.75 (35) 0 156.25 (125) 81.25 (65) – 0 20 30 10 20 20 Max – – 140 – – – – 80 – – – – – – NOTES: 1. All times are in nanoseconds (ns) and assume an 8-MHz input frequency. 2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7. 3. The values for twAS and twDS that are shown in parentheses "( )" assume a 10-MHz input clock. 19-13 ELECTRICAL DATA S3C8465/C8469/P8469 R/W (P2.2) 12 Port 0 DM (P2.3) 3 A8-A15, DM 9 Port 1 1 A0-A7 2 11 5 4 D0-D7 Out D0-D7 In Out 10 AS (P2.0) 8 7 DS (P2.1) 6 13 Figure 19-8. External Memory Read and Write Timing (See Table 19-10 for a description of each timing point.) 19-14 S3C8465/C8469/P8469 MECHANICAL DATA 20 OVERVIEW #64 17.00 ± 0.20 MECHANICAL DATA The S3C8465/C8469/P8469 microcontrollers are available in a 64-SDIP-750, 64-QFP-1420F package. #33 0-15 #1 #32 4.10 ± 0.20 57.80 ± 0.20 0.45 ± 0.10 (1.34) 1.00 ± 0.10 1.778 NOTE: Dimensions are in millimeters. Figure 20-1. 64-SDIP-750 Package Dimensions 3.30 ± 0.30 0.51 MIN 5.08 MAX 58.20 MAX 0.2 5 +0 - 0 .10 .05 64-SDIP-750 19.05 20-1 MECHANICAL DATA S3C8465/C8469/P8469 23.90 ± 0.30 20.00 ± 0.20 0-8 + 0.10 0.15 - 0.05 17.90 ± 0.30 14.00 ± 0.20 64-QFP-1420F 0.80 ± 0.20 #1 1.00 + 0.10 0.10 MAX #64 0.40 - 0.05 0.15 MAX 0.05 MIN (1.00) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 20-2. 64-QFP-1420F Package Dimensions 20-2 S3C8465/C8469/P8469 KS88P4632 OTP 21 OVERVIEW S3P8469 OTP The S3P8469 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8465/C8469 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8469 is fully compatible with the S3C8465/C8469, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P8469 is ideal as an evaluation chip for the S3C8465/C8469. 21-1 KS88P4632 OTP S3C8465/C8469/P8469 P0.7/A15 P0.6/A14 P0.5/A13 P0.4/A12 P0.3/A11 P0.2/A10 P0.1/A9 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7/CAPA SDAT/P4.2/INT6 SCLK/P4.1/INT5/RxD VDD/VDD VSS/VSS XOUT XIN VPP/EA P4.0/INT4 P3.7/TxD RESET/RESET P3.6/SO P3.5/SI P3.4/SCK P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C8465 S3C8469 (64-SDIP) Top View 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 P6.0 P2.0/AS P2.1/DS P2.2/R/W P2.3/DM P2.4/ZCD P2.5/BUZ NOTE: The bolds indicate an OTP pin name. Figure 21-1. S3P8469 Pin Assignments (64-SDIP Package) 21-2 S3C8465/C8469/P8469 KS88P4632 OTP P0.1/A9 P0.2/A10 P0.3/A11 P0.4/A12 P0.5/A13 P0.6/A14 P0.7/A15 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/AD4 P1.5/AD5 P0.0/A8 P4.7/INT11/TDG P4.6/INT10/TCG P4.5/INT9/TDCK P4.4/INT8/TCCK P4.3/INT7CAPA SDAT/P4.2/INT6 SCLK/P4.1/INT5/RxD VDD/VDD VSS/VSS XOUT XIN VPP/EA P4.0/INT4 P3.7/TxD RESET/RESET P3.6/SO P3.5/SI P3.4/SCK S3C8465 S3C8469 (64-QFP) Top View P1.6/AD6 P1.7/AD7 P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0 AVSS AVREF P6.7 P6.6 P6.5 P6.4 P6.3 P6.2 P6.1 NOTE: Figure 21-2. S3P8469 Pin Assignments (64-QFP Package) P3.3/T0CK P3.2/T0 P3.1/PWM1 P3.0/PWM0 P2.7/INT3 P2.6/INT2 P2.5/BUZ P2.4/ZCD P2.3/DM P2.2/R/W P2.1/DS P2.0/AS P6.0 The bolds indicate an OTP pin name. 21-3 KS88P4632 OTP S3C8465/C8469/P8469 Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P4.2 Pin Name SDAT Pin No. 14(7) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is aplied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming. P4.1 EA SCLK VPP 15(8) 20(13) I I RESET VDD/VSS RESET VDD/VSS 23(16) 16(9)/17(10) I – NOTE: ( ) means 64 QFP package. Table 21-2. Comparison of S3P8469 and S3C8465/C8469 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 2.7 V to 5.5 V VDD = 5 V, VPP (EA) = 12.5 V 64 SDIP/64 QFP User Program 1 time 64 SDIP/64 QFP Programmed at the factory S3P8469 32K-byte EPROM S3C8465/C8469 16/32K-byte mask ROM 2.7 V to 5.5 V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (EA) pin of the S3P8469, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mode Selection Criteria VDD 5V VPP (EA) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 ADDRESS R/W 1 0 1 0 EPROM read MODE (A15–A0) 0000H 0000H 0000H 0E3FH EPROM program EPROM verify EPROM read protection NOTE: "0" means Low level; "1" means High level. 21-4