S3P863A

S3C8639/C863A/P863A PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM8 PRODUCT FAMILY Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C8639/C863A/P863A MICROCONTROLLERS S3C8639/C863A/P863A single-chip 8-bit microcontrollers are based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. S3C8639/C863A/P863A contain 32/48 Kbytes of onchip program ROM. In line with Samsung's modular design approach, the following peripherals are integrated with the SAM8 core: — Four programmable I/O ports (total 27 pins) — One 8-bit basic timer for oscillation stabilization and watchdog functions — One 8-bit general-purpose timer/counter with selectable clock sources — One interval timer OTP S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named, S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its ROM size. — One 12-bit counter with selectable clock sources, including Hsync or Csync input — PWM block with seven 8-bit PWM circuits — Sync processor block (for Vsync and Hsync I/O, Csync input, and Clamp signal output) — DDC Multi-master and slave-only IIC-Bus — 4-channel A/D converter (8-bit resolution) S3C8639/C863A/P863A are a versatile microcontrollers which are ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, A/D converter, and multi-master IIC-bus support with DDC. They are available in a 42-pin SDIP or a 44-pin QFP package. 1-1 PRODUCT OVERVIEW S3C8639/C863A/P863A FEATURES CPU • Low Voltage Reset (LVR) • SAM88RC CPU core LVR level is 2.4 V ± 200 mV Memory • Pulse Width Modulator (PWM) • S3C8639: 32-Kbyte internal program memory (ROM) S3C863A: 48-Kbyte internal program memory (ROM) S3C8639: 784-byte general-purpose register area S3C863A: 1040-byte general-purpose register area 8-bit PWM: 7-CH (6-bit basic frame with 2-bit extension) Sync-Processor Block • • Vsync-I, Hsync-I, Csync-I input and Vsync-O, Hsync-O, Clamp-O output pins Programmable Pseudo sync signal generation Auto SOG detection Auto H-/V-sync polarity detection Composite sync detection • • Instruction Set • • • • 78 instructions IDLE and STOP instructions added for power-down modes DDC Multi-Master IIC-Bus 1-Ch • • Instruction Execution Time • Serial Peripheral Interface Support for Display Data Channel (DDC1/DDC2B/DDC2Bi/DDC2B+) Minimum 333 ns (with 12 MHz CPU clock) Interrupts • • • Slave Only IIC-Bus 1-Ch • Ten interrupt sources/vectors Eight interrupt level Fast interrupt feature Serial Peripheral Interface A/D Converter • 4-channel; 8-bit resolution General I/O • Four I/O Ports (total 27pins) Oscillator Frequency • 8 MHz to 12 MHz crystal operation Internal Max. 12 MHz CPU clock 8-Bit Basic Timer • • Programmable timer for oscillation stabilization interval control or watchdog timer function Three selective internal clock frequencies Operating Temperature Range • • – 40 °C to + 85 °C Timer/Counters • Operating Voltage Range • One 8-bit Timer/Counter with several clock sources (Capture mode) One 12-bit Counter with H-/C-sync and several clock sources One Interval Timer 3.0 V to 5.5 V Package Types • • 42-pin SDIP, 44-pin QFP • 1-2 S3C8639/C863A/P863A PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7/INT0-INT2 P2.0-P2.7 RESET Port 0 Port 2 INT0-INT2 XIN XOUT PWM0 8-Bit PWM (7-Ch) PWM6 Vsync-I Hsync-I Csync-I Vsync-O Hsync-O Clamp-O SAM8 CPU SyncProcessor Main Osc I/O Port and Interrupt Control VDD1, VDD2 VSS1, V SS2 TEST Port 1 P1.0-P1.2 Port 3 P3.0-P3.7 ADC 32/48Kbyte ROM 784/1040Byte Register File AD0-AD3 TM0CAP 8-Bit Counter (Timer M0) Slave Only IIC-Bus SCL1 SDA1 * S3C8639 - 32 Kbyte ROM - 784 Byte RAM * S3C863A - 48 Kbyte ROM - 1040 Byte RAM 12-Bit Counter (Timer M1) Interval Timer (Timer M2) Multi-master IIC-Bus and DDC1/2B/2Bi/2B+ SCL0 SDA0 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8639/C863A/P863A PIN ASSIGNMENTS P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5 P0.6 P0.7 P1.0/SDA1 P1.1/SCL1 VDD1 VSS1 XOUT XIN TEST (GND) SDA0 SCL0 RESET P1.2 P2.0/PWM0 P2.1/PWM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C8639 /C863A (42-SDIP) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 VDD2 VSS2 P2.7/Csync-I (SOG) Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 NOTE: The TEST pin must connect to V SS (GND) in the normal operation mode. Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment 1-4 S3C8639/C863A/P863A PRODUCT OVERVIEW P0.5 P0.6 P0.7 P1.0/SDA1 P1.1/SCL1 VDD1 VSS1 XOUT XIN TEST (GND) SDA0 44 43 42 41 40 39 38 37 36 35 34 P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 N.C. P0.0/INT0 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 1 2 3 4 5 6 7 8 9 10 11 S3C8639 /C863A 44-QFP (Top View) 33 32 31 30 29 28 27 26 25 24 23 P3.2/AD2 P3.1/AD1 P3.0/AD0 VDD2 VSS2 P2.7/Csync-I (SOG) Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O SCL0 NOTE: The TEST pin must connect to V Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment P1.2 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 N.C. P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6 SS (GND) RESET 12 13 14 15 16 17 18 19 20 21 22 in the normal operation mode. 1-5 PRODUCT OVERVIEW S3C8639/C863A/P863A PIN DESCRIPTIONS Table 1-1. S3C8639/C863A Pin Descriptions Pin Names P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0–P3.3 P3.4–P3.7 Pin Type I/O Pin Description General-purpose, 8-bit I/O port. Shared functions include three external interrupt inputs and I/O for timer M0. Selective configuration of port 0 pins to input or output mode is supported. Circuit Type D-1 D-1 D-1 D-1 D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 D-1 D-1 D-1 E-1 E-1 E-1 D-1 E-1 E SDIP Pin Numbers 1 2 3 4 5 6 7 8 9 10 19 20 21 22 23 24 25 26 32 35–38 39–42 Shared Functions INT0 INT1 INT2 TM0CAP I/O General-purpose, 8-bit I/O port. Selective configuration is available for port 1 pins to input, push-pull output, n-channel open-drain mode, or IIC-bus clock and data I/O. General-purpose, 8-bit I/O port Selective configuration of port 2 pins to input or output mode is supported. The port 2 pin circuits are designed to push-pull PWM output and Csync (SOG) signal input. SDA1 SCL1 I/O PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 Csync-I AD0–AD3 I/O General-purpose, 8-bit I/O port Selective configuration port 3 pins to input or output mode is supported. Multiplexed for alternative use as A/D converter inputs AD0–AD3. The pins are sync processor signal I/O and IICbus clock and data I/O. Hsync-I Vsync-I Clamp-O Hsync-O Vsync-O SDA0 SCL0 VDD1, VSS1, VDD2, VSS2 XIN, XOUT RESET I I O O O I/O I/O – – I I A-3 A-3 A A A G-3 G-3 – – – B – 31 30 27 28 29 16 17 11, 12 34, 33 14, 13 18 15 – Power pins System clock I/O pins System RESET pin Factory test pin input 0 V: Normal operation, 5 V: Factory test mode – – – – TEST 1-6 S3C8639/C863A/P863A PRODUCT OVERVIEW PIN CIRCUITS DIAGRAM VDD VDD Input Data Output Output 300 kΩ Typical VSS VSS VSS Figure 1-4. Pin Circuit Type A Figure 1-5. Pin Circuit Type A-3 VDD Data or Other Function VDD Output 280 kΩ RESET Output Disable Noise Filter VSS Digital Input, TTL Input NOTE: The noise filter must be built in the external interrupts. Figure 1-6. Pin Circuit Type B (RESET) Figure 1-7. Pin Circuit Type D-1 1-7 PRODUCT OVERVIEW S3C8639/C863A/P863A VDD Typical 47 kΩ Pull-up Enable VDD Data Output Open Drain Output Disable VSS Input Open Drain Output Disable VSS Digital Input or ADC Input Data Output VDD Figure 1-8. Pin Circuit Type E Figure 1-9. Pin Circuit Type E-1 Output Data VSS Input Figure 1-10. Pin Circuit Type G-3 1-8 S3C8639/C863A/P863A ELECTRICAL DATA 19 OVERVIEW — I/O capacitance ELECTRICAL DATA In this section, S3C8639/C863A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in stop mode — Stop mode release timing when initiated by a reset — A/D Converter electrical characteristics — A.C. electrical characteristics — Input timing measurement points for P0.0–P0.2 and TM0CAP — Oscillation characteristics — Oscillation stabilization time — Clock timing measurement points for XIN — Schmitt trigger characteristics — Power-on reset circuit characteristics 19-1 ELECTRICAL DATA S3C8639/C863A/P863A Table 19-1. Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input voltage Output voltage Output current High Output current Low Symbol VDD VI1 VI2 VO I OH Conditions – Type G-3 (n-channel open drain) All port pins except VI1 All output pins One I/O pin active All I/O pins active I OL One I/O pin active Total pin current except port 3 Sync-processor I/O pins and IIC-bus clock and data pins – – Rating – 0.3 to + 6.5 – 0.3 to + 7.0 – 0.3 to VDD + 0.3 – 0.3 to VDD + 0.3 – 10 – 60 + 30 + 100 + 150 – 40 to + 85 – 65 to + 150 °C Unit V mA Operating temperature Storage temperature TA TSTG Table 19-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Input High voltage Symbol VIH1 VIH2 VIH3 VIH4 Input Low voltage VIL1 VIL2 VIL3 VIL4 Output High voltage VOH1 VOH2 VOH3 VOH4 XIN TTL input (Hsync-I, Vsync-I, and Csync-I) SCL0/SDA0, SCL1/SDA1 All input pins except VIL2 and VIL3 XIN TTL input (Hsync-I, Vsync-I, and Csync-I) SCL0/SDA0, SCL1/SDA1 VDD = 5 V ± 10%; IOH = – 15 mA; Port 3.6–3.7 VDD = 5 V ± 10%; IOH = – 4 mA; Port 1.2, Port 3.0–3.5 VDD = 5 V ± 10%; IOH = – 2 mA; Port 0, 2, Clamp-O, H, and Vsync-O VDD = 5 V ± 10%; IOH = – 6 mA; Port 1.0–P1.1, SCL0 and SDA0 VDD – 1.0 Conditions All input pins except VIH2, VIH3 and VIH4 Min 0.8 VDD VDD–0.5 2.0 0.7VDD – Typ – Max VDD VDD VDD VDD 0.2 VDD 0.4 0.8 0.3VDD – Unit V 19-2 S3C8639/C863A/P863A ELECTRICAL DATA Table 19-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Output Low voltage Symbol VOL1 VOL2 VOL3 VOL4 Input High leakage current ILIH1 ILIH2 ILIH3 Input Low leakage current ILIL1 ILIL2 ILIL3 Output High leakage current Output Low leakage current Pull-up resistor ILOH1 ILOL1 RU1 RU2 Pull-down resistor Supply current (note) Conditions VDD = 5 V ± 10%; IOL = 15 mA Port 3.6–3.7 VDD = 5 V ± 10%; IOL = 4 mA Port 3.0–3.5 and Port 1.2 VDD = 5 V ± 10%; IOL = 2 mA Port 0, 2, Clamp-O, H, and Vsync-O VDD = 5 V ± 10%; IOL = 6 mA Port 1.0–1.1; SCL0 and SDA0 VIN = VDD All input pins except XIN, XOUT VIN = VDD; XOUT only VIN = VDD; XIN only VIN = 0 V; All input pins except XIN, XOUT, RESET , HsyncI & VsyncI VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD VOUT = 0 V VIN = 0 V; VDD = 5 V ± 10% Ports 3.7–3.4 VIN = 0 V; VDD = 5 V ± 10% RESET only VIN = 0 V; VDD = 5 V ± 10% HsyncI & VsyncI VDD = 5 V ± 10% Operation mode; 12 MHz crystal C1 = C2 = 22pF VDD = 5 V ± 10% Idle mode; 12 MHz crystal C1 = C2 = 22pF VDD = 5 V ± 10% Stop mode Min – Typ – Max 0.4 0.4 0.4 0.6 Unit V – – 2.5 – – – 2.5 – – 20 150 150 – – – 6 – – –6 – – 47 280 300 10 3 20 20 –3 – 20 – 20 3 –3 80 480 500 20 µA kΩ RD IDD1 mA IDD2 4 8 IDD3 100 150 µA NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output. 19-3 ELECTRICAL DATA S3C8639/C863A/P863A Table 19-3. Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode, VDDDR = 2.0 V Min 2 – Typ – – Max 5.5 5 Unit V µA NOTES: 1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped. 2. Supply current does not include drawn through internal pull–up resistors and external output current loads. RESET occurs Stop Mode Data Retention Mode Oscillation Stabilzation Time ~ ~ ~ ~ VDD VDDDR Execution of STOP Instrction RESET Normal Operating Mode NOTE: t WAIT is the same as 4096 x 16 x 1/f OSC. tWAIT Figure 19-1. Stop Mode Release Timing When Initiated by a Reset Table 19-4. Input/Output Capacitance (TA = –40 °C to + 85 °C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min – Typ – Max 10 Unit pF 19-4 S3C8639/C863A/P863A ELECTRICAL DATA Table 19-5. A/D Converter Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block Current (2) ILE DLE EOT EOB tCON VIAN RAN AVREF AVSS IADIN IADC 8 bit conversion 40 x n/fOSC (3), n=1,4,8,16 – – – – AVREF = VDD = 5V AVREF = VDD = 5V AVREF = VDD = 3V AVREF = VDD = 5V When power down mode 20 AVSS 2 2.5 VSS – – VDD = 5 V Conversion time = 5 µs AVREF = 5 V AVSS = 0 V Symbol Conditions Min – – Typ 8 – – – ±1 ± 0.5 – – 1000 – – – 1 0.5 100 Max – ±2 ±1 ±1 ±2 ±2 170 AVREF – VDD VSS + 0.3 10 3 1.5 500 µs V MΩ V V µA mA mA nA Unit bit LSB NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during the A/D conversion. 3. fOSC is the main oscillator clock. 19-5 ELECTRICAL DATA S3C8639/C863A/P863A Table 19-6. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5V) Parameter Noise Filter Symbol tNF1H tNF1L tNF2 Conditions INT0–2 and TM0CAP (RC delay) RESET only (RC delay) Min 300 1000 Typ – – Max – – Unit ns tNF1L tNF2 0.8 VDD 0.2 VDD tNF1H Figure 19-2. Input Timing Measurement Points for P0.0–P0.2 and TM0CAP 19-6 S3C8639/C863A/P863A ELECTRICAL DATA Table 19-7. Oscillation Characteristics (TA = – 40 °C + 85 °C) Oscillator Main crystal or ceramic Clock Circuit C1 Conditions VDD = 3.0 V to 5.5 V Min 8 Typ – Max 12 Unit MHz XIN XOUT C2 External clock (main) XIN XOUT VDD = 3.0 V to 5.5 V 8 – 12 MHz NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values. Table 19-8. Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 3.0 V to 5.5 V) Oscillator Crystal Ceramic External clock Test Condition VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5V XIN input high and low level width (tXH, tXL) Min – – 25 Typ – – – Max 20 10 500 ns Unit ms NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is released. 1/fx tXL tXH XIN VDD - 0.5 V 0.4 V Figure 19-3. Clock Timing Measurement Points for XIN 19-7 ELECTRICAL DATA S3C8639/C863A/P863A VOUT VDD A = 0.2 V DD B = 0.4 V DD C = 0.6 V DD D = 0.8 V DD VSS A B C D VIN Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input) Table 19-9. Power-on Reset Circuit Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Power-on reset release voltage Power-on reset detection voltage Power supply voltage rise time Power supply voltage off time Power-on reset circuit consumption current (2) Symbol VODLVD Conditions Min 2.7 Typ – Max 5.5 Unit V VLVD tr toff IDDPR VDD = 5 V ± 10% VDD = 3 V 2.2 10 10 2.4 – – 100 60 2.6 (1) V us ms µA µA – 150 100 NOTES: 1. 216/fOSC (= 5.46 ms at fOSC/12MHz) 2. Current contained when power-on reset circuit is provided internally. 19-8 S3C8639/C863A/P863A ELECTRICAL DATA VDD VDDLVD VLVD toff tr Figure 19-5. Power-on Reset Timing 19-9 S3C8639/C863A/P863A MECHANICAL DATA 20 OVERVIEW #42 14.00 ± 0.2 MECHANICAL DATA The S3C8639/C863A microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP600) and a 44-QFP package (Samsung part number 44-QFP-1010B). #22 0-15 #1 #21 39.10 ± 0.2 (1.77) NOTE: Dimensions are in millimeters. Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600) 3.30 1.00 ± 0.1 1.778 0.51 MIN ± 0.3 0.50 ± 0.1 3.50 ± 0.2 39.50 MAX 5.08 MAX 0.2 5 +0 - 0 .1 .05 42-SDIP-600 15.24 20-1 MECHANICAL DATA S3C8639/C863A/P863A 13.20 ± 0.3 0-8 10.00 ± 0.2 0.15 + 0.10 - 0.05 13.20 ± 0.3 10.00 ± 0.2 44-QFP-1010B 0.80 ± 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 (1.00) 0.05 MIN 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B) 20-2 S3C8639/C863A/P863A S3P863A OTP 21 OVERVIEW S3P863A OTP The S3P863A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8639/C863A microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P863A is fully compatible with the S3C8639/C863A, both in function and in pin configuration. Because of its simple programming requirements, the S3P863A is ideal for use as an evaluation chip for the S3C8639/C863A. P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3 P0.4/TM0CAP P0.5 P0.6 P0.7 SDAT/P1.0/SDA1 SCLK/P1.1/SCL1 VDD1 VSS XOUT XIN VPP/TEST (GND) SDA0 SCL0 RESET /RESET P1.2 P2.0/PWM0 P2.1/PWM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3P863A 42-SDIP (Top View) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P3.2/AD2 P3.1/AD1 P3.0/AD0 VDD2 VSS2 P2.7/Csync-I (SOG) Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O P2.6/PWM6 P2.5/PWM5 P2.4/PWM4 P2.3/PWM3 P2.2/PWM2 NOTE: The bolds indicate an OTP pin name. Figure 21-1. S3P863A Pin Assignments (42-SDIP Package) 21-1 S3P863A OTP S3C8639/C863A/P863A 44 43 42 41 40 39 38 37 36 35 34 P0.4/TM0CAP P0.3 P0.2/INT2 P0.1/INT1 N.C. P0.0/INT0 P3.7 P3.6 P3.5 P3.4 P3.3/AD3 P0.5 P0.6 P0.7 SDAT/P1.0/SDA1 SCLK/P1.1/SCL1 VDD1 VSS1 XOUT XIN VPP/TEST (GND) SDA0 1 2 3 4 5 6 7 8 9 10 11 S3P863A 44-QFP (Top View) 33 32 31 30 29 28 27 26 25 24 23 P3.2/AD2 P3.1/AD1 P3.0/AD0 VDD2 VSS2 P2.7/Csync-I (SOG) Hsync-I Vsync-I Vsync-O Hsync-O Clamp-O SCL0 NOTE: 21-2 The bolds indicate an OTP pin name. Figure 21-2. S3P863A Pin Assignments (44-QFP Package) RESET /RESET P1.2 P2.0/PWM0 P2.1/PWM1 P2.2/PWM2 N.C. P2.3/PWM3 P2.4/PWM4 P2.5/PWM5 P2.6/PWM6 12 13 14 15 16 17 18 19 20 21 22 S3C8639/C863A/P863A S3P863A OTP Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P1.0 Pin Name SDAT Pin No. 9 (4) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming. P1.1 TEST SCLK VPP (TEST) 10 (5) 15 (10) I I RESET RESET 18 (13) 11/12 (6/7) I I VDD1/VSS1 VDD1/VSS1 NOTE: Parentheses indicate 44-QFP OTP pin number. Table 21-2. Comparison of S3P863A and S3C8639/C863A Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 3.0 V to 5.5 V VDD = 5 V, VPP (TEST)=12.5V 42SDIP, 44QFP User Program 1 time 42SDIP, 44QFP Programmed at the factory S3P863A 48-Kbyte EPROM S3C8639/C863A 32/48-Kbyte mask ROM 3.0 V to 5.5V OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P863A, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15–A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 21-3 S3P863A OTP S3C8639/C863A/P863A D.C. ELECTRICAL CHARACTERISTICS Table 21-4. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 3.0 V to 5.5 V) Parameter Input High leakage current Symbol ILIH1 ILIH2 ILIH3 Input Low leakage current ILIL1 ILIL2 ILIL3 Output High leakage current Output Low leakage current Pull-up resistor ILOH1 ILOL1 RU1 RU2 Pull-down resistor Supply current (note) Conditions VIN = VDD All input pins except XIN, XOUT VIN = VDD; XOUT only VIN = VDD; XIN only VIN = 0 V; All input pins except XIN, XOUT, RESET , Hsync-I and Vsync-I VIN = 0 V; XOUT only VIN = 0 V; XIN only VOUT = VDD VOUT = 0 V VIN = 0 V; VDD = 5 V ± 10% Port 3.7–3.4 VIN = 0 V; VDD = 5 V ± 10% RESET only VIN = 0 V; VDD = 5 V ± 10% Hsync-I and Vsync-I VDD = 5 V ± 10% Operation mode; 12 MHz crystal C1 = C2 = 22pF VDD = 5 V ± 10% Idle mode; 12 MHz crystal C1 = C2 = 22pF VDD = 5 V ± 10% Stop mode Min – – 2.5 – – – 2.5 – – 20 150 150 – Typ – – 6 – – –6 – – 47 280 300 10 Max 3 20 20 –3 – 20 – 20 3 –3 80 480 500 20 Unit µA kΩ RD IDD1 mA IDD2 4 8 IDD3 100 150 µA NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output. 21-4