LA6548ND

Ordering number : EN8767A Monolithic Linear IC LA6548ND Overview For CD Players and Recorders Four-Channel Driver IC The LA6548ND is a four-channel driver IC for CD players and recorders (four BTL amplifier channels). Functions • Four BTL connection power amplifier channels • IO max 0.7A • Built-in level shifters • Muting circuit (on/off control of all outputs) (This circuit applies to the BTL amplifier circuits. It does not control operation of the regulator.) • Built-in regulator (provides a 3.3V output using an external pnp transistor) • Thermal protection circuit (thermal shutdown circuit) Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Maximum output current Maximum input voltage Muting pin application voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IO max VIN VMUTE Pd max Topr Tstg For each of the channel 1 to 4 outputs Conditions Ratings 14 0.7 13 13 1.5 -20 to +75 -55 to +150 Unit V A V V W °C °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 42507 TI PC B8-7473 No.8767-1/7 LA6548ND Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage 1 Supply voltage 2 Symbol VCC1 VCC2 Only used by the BTL amplifiers (Not used by the 3.3V regulator circuit) Conditions Ratings 4.6 to 13 3.9 to 13 Unit V V Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 6V, VREF = 1.65V, unless otherwise specified. Parameter Overall Characteristics No-load current drain, on state No-load current drain, off state Thermal shutdown circuit operating temperature Output Amplifier Block Output offset voltage VREF input voltage range Output voltage VOFF VINVREF VO VG SR VMUTE The voltage across the outputs when RL = 8Ω Voltage gain, input to output Slew rate Muting on voltage The voltage gain from an input to the corresponding +/- outputs.*2 (Design guarantee value *1) The voltage at which the output on/off state changes Power Supply Block (Using a 2SB632K) 3.3V power supply voltage Line regulation Load regulation Reset Block RESET pin high-level voltage RESET pin low-level voltage RESET pin threshold voltage RESET pin hysteresis RESET pin output delay time *1 : These parameters are not tested. *2 : The gain from input to output when only the VIN* pins are used. *3 : The MUTE pin voltage when the output changes between the on and off states. When the MUTE pin is high, all the BTL amplifiers will be on, and the when MUTE is low, all the BTL amplifiers will be off. *4 : The 3.3V regulator voltage when the RESET pin goes from high to low. *5 : The 3.3V regulator voltage difference between the RESET pin going from high to low the RESET pin going from low to high. That is, the hysteresis. VORH VORL VRT VHYS td ISRL = 2mA, Cd-GND *4 *5 Cd = 0.1μF 40 3.08 3.25 100 2.8 80 10 160 3.42 200 V mV V mV ms ΔVOLIN ΔVOLOAD IO = 200mA 4.6V ≤ VCC ≤ 12V 5mA ≤ IO ≤ 200mA 3.13 3.3 40 50 3.47 100 150 V mV mV 0.15 1.2 V/μs V 9 dB The voltage difference between each of the + or - outputs. 1.3 2.6 3 VCC-1.5 V V -50 50 mV ICCON ICCOFF TSD All outputs on, MUTE : high All outputs off, MUTE : low (Design guarantee value *1) 150 20 15 175 40 35 200 mA mA °C Symbol Conditions min Ratings typ max Unit No.8767-2/7 LA6548ND Package Dimensions unit : mm (typ) 3307 2.0 Pd max – Ta 27.0 30 16 Allowable power dissipation, Pd max – W 1.5 Independent IC 1.5 10.16 8.6 3.0 3.95 max 0.95 (3.25) 0.25 1 15 1 0.9 0.5 0.51 min 0.48 1.78 (1.04) 0 – 20 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : DIP30SDLF(400mil) Block Diagram VCC1 1 30 VCC2 MUTE 2 11kΩ Mute (output on/off control) 15.4kΩ 15.4kΩ 11kΩ 29 VREF VIN1 3 28 VIN4 VG1 4 27 VG4 Level shifter 5 Level shifter VO1+ 26 VO4+ VO1- 6 25 VO4- GND 7 24 GND GND 8 23 GND GND 9 22 GND Level shifter VO2+ Level shifter VO2- 10 21 VO3- 11 20 VO3+ VG2 12 15.4kΩ 15.4kΩ 11kΩ 11kΩ 13 19 VG3 VIN2 18 VIN3 REG_C 14 Connect to the external pnp transistor collector. 3.3VREG Connect to the external pnp transistor base. RESET 17 CD REG_B 15 16 RESET No.8767-3/7 LA6548ND Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin VCC1 MUTE VIN1 VG1 VO1+ VO1GND GND GND VO2VO2+ VG2 VIN2 REG_C REG_B RESET CD VIN3 VG3 VO3+ VO3GND GND GND VO4VO4+ VG4 VIN4 VREF VCC2 Description Power supply (This pin is shorted to VCC2 (pin 30) Output on/off control Channel 1 input Channel 1 input (Gain setting) Channel 1 output (+) Channel 1 output (-) GND pin GND pin GND pin Channel 2 output (-) Channel 2 output (+) Channel 2 input (Gain setting) Channel 2 input Connect this pin to the external pnp transistor collector. (This is the 3.3V regulator output) Connect this pin to the external pnp transistor base. Reset output Connection for the reset delay time setting capacitor Channel 3 input Channel 3 input (Gain setting) Channel 3 output (+) Channel 3 output (-) GND pin GND pin GND pin Channel 4 output (-) Channel 4 output (+) Channel 4 input (Gain setting) Channel 4 input Reference voltage input Power supply (This pin is shorted to VCC1 (pin 1) Equivalent Circuits Pin No. 3 4 13 12 18 19 28 27 VIN1 VG1 VIN2 VG2 VIN3 VG3 VIN4 VG4 Pin Input pins. Description Equivalent circuit VG* VIN* VCC VCC GND GND Continued on next page No.8767-4/7 LA6548ND Continued from preceding page. Pin No. 5 6 11 10 20 21 26 25 Pin VO1+ VO1VO2+ VO2VO3+ VO3VO4+ VO4Output pins. Description Equivalent circuit VCC 33kΩ VCC VO*-/+ GND GND 2 MUTE Muting control input. The outputs will be on when the MUTE pin is at the high level. The outputs will be off when the MUTE pin is at the low level ; in particular, the outputs go to the high-impedance state at this time. VCC VCC MUTE 40kΩ GND 30kΩ 29 VREF Reference voltage input. VREF VCC VCC GND GND 16 RESET Reset output. When REG C (3.3VREG) is high, RESET will be high. When REG C (3.3VREG) is low, RESET will be low. Details of Operating voltage see section Reset operation. VCC REG_C (3.3VREG) GND RESET GND 17 CD Reset output delay time setting. The delay time until the point the reset output switches from low to high is set by the capacitor connected between this pin and ground. Reference to Reset operation. VCC GND CD GND No.8767-5/7 LA6548ND Application Circuit Example VCC 1 VCC1 VCC2 30 VREF input (Reference voltage) MUTE 2 SPINDLE input 3 VIN1 VIN4 28 MUTE VREF 29 FOCUS input 4 VG1 VG4 27 5 SPINDLE M VO1+ VO4+ 26 FOCUS 6 VO1- VO4- 25 7 GND GND 24 8 GND GND 23 LA6548ND 9 GND GND 22 10 SLED M VO2- VO3- 21 TRACKING 11 VO2+ VO3+ 20 12 VG2 VG3 19 13 SPINDLE input 3.3V input 100μF + 14 VIN2 VIN3 18 TRACKING input 17 Reset delay time setting REG_C CD 15 VCC REG_B RESET 16 No.8767-6/7 LA6548ND Reset Operation REG_C (3.3VREG) 3.3V (2.88V) 2.80V 80mV T RESET td T td *1 : td is the delay time. It is set by an external capacitor connected between the CD pin and ground). *2 : The voltage at which RESET changes state is a typical value (voltage). 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2007. Specifications and information herein are subject to change without notice. PS No.8767-7/7