LA75503V

Ordering number : ENN6804 Monolithic Linear IC LA75503V Adjustment Free VIF/SIF Signal Processing IC for PAL TV/VCR Overview The LA75503V is an adjustment free VIF/SIF signal processing IC for PAL TV/VCR. It supports 38 MHz, 38.9 MHz, and 39.5 MHz as the IF frequencies, as well as PAL sound multi-system (M/N, B/G, I, D/K), and contains an on-chip sound carrier trap and sound carrier BPF. To adjust the VCO circuit, AFT circuit, and sound filter, 4-MHz external crystal or 4-MHz external signal is needed. Package Dimensions unit: mm 3191A-SSOP30 (275 mil) [LA75503V] Functions • VIF amplifier • VCO adjustment free PLL detection circuit • Digital AFT circuit • RF AGC • Buzz canceller • Equalizer amplifier • Internal sound carrier BPF • Internal sound carrier trap • PLL-FM detector • Reference oscillation circuit SANYO: SSOP30 (275 mil) Features • Internal VCO adjustment free circuit eliminating need for VCO coil adjustments. • Internal sound carrier BPF and sound carrier trap enable easy configuration of PAL sound multi-system at low cost. • Considerably reduces the number of required peripheral parts. • Use of digital AFT eliminates problem of AFT tolerance. • Package: SSOP30 (275 mil) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 41301RM (OT) No. 6804-1/15 LA75503V Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Circuit voltage Symbol VCC max V16 V18 I30 Circuit current I17 I6 I4 Allowable power dissipation Operating temperature Storage temperature Note: * Circuit board dimensions: 65 × 72 × 1.6 mm3, Pd max Topr Tstg material: paper phenol. Ta ≤ 70°C (*Mounted on a printed circuit board) Conditions Ratings 7 VCC VCC –1 +0.5 –10 –3 550 –20 to +70 –55 to +150 Unit V V V mA mA mA mA mW °C °C Operating Conditions at Ta = 25°C Parameter Recommended supply voltage Operating voltage range Symbol VCC VCC op Conditions Ratings 5 4.5 to 5.5 Unit V V Electrical Characteristics at Ta = 25°C, VCC = 5.0 V, fp = 38.9 MHz Parameter [VIF Block ] Circuit current Maximum RF AGC voltage Minimum RF AGC voltage Input sensitivity AGC range Maximum allowable input No-signal video output voltage Synchronizing signal tip voltage Video output level Video signal-to-noise ratio C-S beating Differential gain Differential phase Black noise threshold voltage Black noise clamp voltage VIF input resistance VIF input capacitance Maximum AFT voltage Minimum AFT voltage AFT tolerance 1 AFT tolerance 2 AFT tolerance 3 AFT detection sensitivity AFT dead zone APC pull-in range (U) APC pull-in range (L) VCO maximum frequency range (U) VCO maximum frequency range (L) VCO control sensitivity I17 V14H V14L Vi GR Vimax V4 V4tip VO S/N IC-S DG DP VBTH VBCL Ri Ci V13H V13L dfa1 dfa2 dfa3 Sf fda fpu fpl dfu dfl β 1.5 1.5 1.5 1.5 2.0 f = 38.9 MHz f = 38.0 MHz f = 39.5 MHz RL = 100 kΩ//100 kΩ 40 4.3 0 B/G P/S = 10 dB Vin = 80 dBµ 33 58 92 3.3 1.0 1.7 48 26 97 3.6 1.3 2.0 52 32 3 2 0.7 1.8 2.5 3 4.7 0.2 ±35 ±35 ±35 80 30 2.0 2.0 2.0 2.0 4.0 8.0 3.0 6 5.0 0.7 ±70 ±70 ±70 120 60 38 10 10 3.9 1.6 2.3 Collector load 30 kΩ VC2 = 9 V 8.5 64.0 9 0.3 39 73.6 — 0.7 45 mA V V dBµV dB dBµV V V Vpp dB dB % deg V V kΩ PF V V kHz kHz kHz mV/kHz kHz MHz MHz MHz MHz kHz/mV Symbol Conditions Ratings min typ max Unit Continued on next page. No. 6804-2/15 LA75503V Continued from preceding page. Parameter N trap1 (4.75 MHz) N trap2 (5.25 MHz) BG trap1 (5.75 MHz) BG trap2 (6.1 MHz) BG trap3 (5.85 MHz) I trap1 (6.25 MHz) I trap2 (6.8 MHz) DK trap1 (6.75 MHz) Group delay 1 NTSC (3.0 MHz) Group delay 1-1 NTSC (3.5 MHz) Group delay 2 BG (4 MHz) Group delay 2-1 BG (4.4 MHz) Group delay 3 I (4 MHz) Group delay 3-1 I (4.4 MHz) Group delay 4 DK (4 MHz) Group delay 4-1 DK (4.4 MHz) [1st SIF Block] Conversion gain SIF carrier output level First SIF maximum input First SIF input resistance First SIF input capacitance [SIF Block] Limiting sensitivity FM detector output voltage AM rejection ratio Total harmonic distortion FM detector output S/N BPF 3-dB bandwidth PAL de-emphasis NTSC de-emphasis PAL/NT audio voltage gain difference [Others] 4-MHz level (during external input) SIF system SW threshold voltage IF system SW threshold resistance Split/inter SW X4MIN V10, V11 V12 V16 0.5 Terminated 86 1.4 270 dBµ V kΩ V Vi(lim) Vo(FM) AMR THD S/N(FM) BW Pdeem Ndeem GD fm = 3 kHz fm = 2 kHz fp = 5.5 MHz, ∆F = ±30 kHz at 400 Hz AM = 30% at 400 Hz f = 5.5 MHz, ∆F = ±30 kHz 55 46 560 50 52 700 60 0.3 60 ±100 –3 –3 6 1.0 58 850 dBµV mVrms dB % dB kHz dB dB dB Vg So Simax Ris Cis fp = 5.5 MHz, Vi = 500µV Vi = 10 mV So ±2 dB 26 32 100 106 5.0 3 6.0 6 38 dB mVrms dBµV kΩ pF Symbol NT1 NT2 BT1 BT2 BT3 IT1 IT2 DT1 NGD1 NGD1-1 BGD2 BGD2-1 IGD3 IGD3-1 DGD4 DGD4-1 wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz wrt 1 MHz Conditions Ratings min –30 –19 –27 –20 –27 –25 –15 –25 10 70 30 100 0 30 0 0 typ –35 –24 –32 –25 –32 –30 –20 –30 40 120 60 150 30 60 15 30 70 170 90 200 60 90 30 60 max Unit dB dB dB dB dB dB dB dB ns ns ns ns ns ns ns ns No. 6804-3/15 LA75503V System Switching • SIF system switch The SIF system is switched by setting pins A (pin 13) and B (pin 14) to GND or OPEN. A GND GND OPEN OPEN B GND OPEN GND OPEN O O O B/G I D/K M/N O FM DET LEVEL 6 dB 0 dB 0 dB 0 dB De-emphasis 75 µs 50 µs 50 µs 50 µs Note: "O" indicates that the system is selected. • IF system switch 38.9 MHz is selected as the IF frequency by leaving pin 15 (crystal oscillation) open. 38 MHz is selected by adding 220 kΩ between pin 15 and GND. This device can also select 39.5 MHz operation by adding a 220 kΩ resistor between pin 15 and VCC. • Split/inter carrier switch Inter carrier is selected by setting the first SIF input (pin 20) to GND. Sound Trap The trapping point of the sound trap is set approximately 250 kHz above the SIF center frequency of each mode to improve the video S/N. Therefore, design using split specifications is preferable. Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 SIF INPUT FM FILTER NC 1st SIF OUT NC VIDEO DET OUT EQ FILTER SIF AGC FILTER APC FILTER FLL FILTER VCO COIL VCO COIL SYSTEM SW [A] SYSTEM SW [B] REF OSC FM DET OUT FM NOISE FILTER RF AGC VR SIF PLL FILTER NC FILTER CONTROL CAPACITOR VIF INPUT VIF INPUT GND VCC 1st SIF INPUT NC IF AGC FILTER RF AGC OUT AFT OUT LA75503V 23 22 21 20 19 18 17 16 Top view No. 6804-4/15 LA75503V Test Circuit Input Impedance Measuring Circuit (VIF, First SIF input impedance) Impedance analyzer VIF INPUT 1st SIF INPUT + V CC 100 µF 15 kΩ 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LA75503V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 kΩ Top view *: 0.01 µF in case of unspecified capacitor 10 kΩ No. 6804-5/15 LA75503V Pin Functions Pin No. Pin Pin Function Internal Circuit Inputs the SIF signal from the first SIF output. 1 SIF INPUT Set the input level to 90 dBµV or lower because of the dynamic range of the internal filter. This is the FM feedback filter pin. It is composed of a C and R filters. 1 µF is normally used as the capacitance. 2 FM FILTER If the capacitance is a low value, the audio output level is small at low frequencies. Moreover, the audio output level can be made smaller by increasing the resistance connected in series. Use a resistance of 3 kΩ or higher. 3 NC Not connected This is the first SIF output. In case of inter carrier, the chroma carrier is bigger than split carrier applications, so that it is recommended to connect a filter externally. 4 1st SIF OUT Filter example Continued on next page. No. 6804-6/15 LA75503V Continued from preceding page. Pin No. 5 Pin NC Not connected Pin 6 is the video output pin. The EQ amplifier can be thought of as shown below. Pin Function Internal Circuit 6 7 VIDEO-OUT EQ-OUT Therefore, the peak gain of the EQ amplifier is determined by Av = 1 + R/Z. However, note that the LA75503V being an IC with VCC = 5 V, setting too large an amplitude causes distortion in the VCC side. Use so that the white level is 4 V or less. Pin 8 is the SIF AGC filter pin. 8 SIF AGC FILTER Use this pin with a capacitance between 0.01 µF and 0.1 µF. Pin 9 is the PLL detector APC filter pin. Normally the following are used: R = 330 Ω C1 = 0.47 µ to 1 µF C2 = 100 pF C1 = 1 µF is effective for the overmodulation characteristics. When the PLL is locked, the signal passes via the path marked A in the figure, and when PLL is unlocked and in weak signal, the signal passes via the path marked B in the figure. The PLL loop gain can thus be switched in this manner. Pin 10 is a VCO automatic control FLL filter pin. Since it operates always on a small current, using a larger capacitance results in a slower response. Normally, a capacitance between 0.47 µF and 1 µF is used. Moreover, the control range for this pin is between about 3 V to 4.7 V. Since this range is determined when adjusting the VCO tank circuit, set the design center of L and C of VCO so that the voltage of pin 10 is 3.6 V. Time constant switch output 9 10 APC FILTER FLL FILTER output Continued on next page. No. 6804-7/15 LA75503V Continued from preceding page. Pin No. Pin Pin Function Internal Circuit This is the VCO tank circuit for the PLL detector. Use a tuning capacitance of 24 pF. 11 12 VCO COIL Use L and C specifications that are accurate to ±2%. Also, design the L and C values so that the voltage of pin 10 is 3.6 V when PLL is locked while using the IF center frequency. 13 14 This is the system switch pin. SYSTEM SW The transistor turns ON when the pin voltage from the circuit becomes approx. 1.4 V. This pin can be used both as the crystal resonator pin and IF switch. The 38-MHz mode is selected by inserting 220 kΩ between pin 15 and GND, the 38.9 MHz mode by leaving the pin open, and the 39.5-MHz mode by inserting 220 kΩ between pin 15 and VCC. 4-MHz input is possible from this pin. In the case of 4-MHz external input, input 86 dBµ or more. 15 REF OSC Continued on next page. No. 6804-8/15 LA75503V Continued from preceding page. Pin No. Pin Pin Function Pin 16 is the AFT output pin. Use external resistors of 47 k Ω and a filter capacitance 0.1 µF. The AFT circuit generates the AFT voltage by comparing the signal obtained by dividing the 4-MHz reference frequency with the signal obtained by dividing VCO. Since it uses a digital phase comparator, a dead zone exists in the AFT center. 16 AFT OUT waveform Internal Circuit Pin 17 is the RF AGC output. RF AGC max is determined by R1 and R2. RF AGC min is determined by R3 and R4. 17 RF AGC OUT Capacitor C1 prevents oscillation and capacitor C2 Comparator is the RF AGC filter. Normally 30 kΩ is used for R1, but if the tuner's F/E transistor is GaAS, the gate's impedance is lower, so use approx. 10 kΩ. Pin 18 is the IF AGC filter pin. 18 IF AGC FILTER Normally, 0.01 µF to 0.02 µF polyester film capacitor is used. Determine the impedance based on H-SAG and AGC speed. 19 NC Not connected Continued on next page. No. 6804-9/15 LA75503V Continued from preceding page. Pin No. Pin Pin Function Internal Circuit Pin 20 can be used both as the First SIF IN and inter/split switch pins. In the case of inter carrier, connect pin 20 to GND. When a sound saw filter is added, the matching loss can be decreased by inserting L to neutralize the IC input capacitance and saw filter output capacitance. 20 1st SIF INPUT 21 VCC Connect the decoupling capacitor as close as possible. 22 GND Pins 23 and 24 are VIF input pins. To reduce the loss of signal through a saw filter, input registors are set to 2 kΩ. VIF amplifier has three capacitive coupling amplifiers, direct connection from a saw filter is available. 23 24 VIF INPUT Continued on next page. No. 6804-10/15 LA75503V Continued from preceding page. Pin No. Pin Pin Function Internal Circuit 25 FILTER CONTROL CAPACITOR Internal filters (i.e. sound carrier BPF and sound carrier trap) are tuned using the capacitor connected to pin 25. A value between 0.47 µF and 1 µF is considered desirable taking video S/N, and AM and PM noise into consideration. 26 NC Not connected Pin 27 is the SIF PLL filter pin. Normally use the following values. R: 3 kΩ C1: 0.01 µF C2: 1000 pF 27 SIF PLL FILTER A large R value (6 kΩ or lower) results in high-pass FM detection output noise. A smaller R value results in low-pass noise. Continued on next page. No. 6804-11/15 LA75503V Continued from preceding page. Pin No. Pin Pin Function Internal Circuit output Pin 28 is the RF AGC VR pin. 28 RF AGC VR When this pin is connected to GND, no signal is appeared on pin 6 and pin 30. 29 FM FILTER Pin 29 is the FM filter pin. Use a capacitance between 0.01 µF and 1 µF. Pin 30 is the FM output pin. The built-in differential amplifier determines and switches the de-emphasis resistance value. 30 FM DET OUT PAL: 5 k × 0.01µF NT: 7.5 k × 0.01 µF D No. 6804-12/15 LA75503V Sample Application Circuit System Switch AB 00 01 10 11 1: OPEN 0: GND BG I DK MN GAIN 6 dB 0 dB 0 dB 0 dB No. 6804-13/15 LA75503V Test Circuit System Switch No. 6804-14/15 LA75503V Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 2001. Specifications and information herein are subject to change without notice. PS No. 6804-15/15