LB11822

Ordering number : ENN7105 Monolithic Digital IC LB11822 Three-Phase Brushless Motor Driver for OA Products Overview The LB11822 is a three-phase brushless motor driver that is optimal for driving drum and paper feed motors in laser printers and plain paper copiers. This IC adopts a direct PWM drive technique for minimal power loss. Flexible control of motor speed in response to an externally provided clock frequency (corresponding to the FG frequency) can be implemented by using the LB11822 in conjunction with the Sanyo LB11825M. Package Dimensions unit: mm 3147B-DIP28H [LB11822] 28 15 R1.7 12.7 11.2 8.4 Functions and Features • • • • • • • Three-phase bipolar drive (30 V, 3.1 A) Direct PWM drive Built-in low side inductive kickback absorbing diode Speed discriminator + PLL speed control Speed locked state detection output Built-in forward/reverse switching circuit Full complement of built-in protection circuits, including current limiter circuit, thermal protection circuit, and motor lock protection circuit. 1 20.0 27.0 14 1.93 1.78 0.6 1.0 4.0 4.0 SANYO: DIP28H Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg T ≤ 500 ms Independent IC When infinitely large heat sink Conditions Ratings 30 3.1 3 20 –20 to +80 –55 to +150 Unit V A W W °C °C Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N1703SI (OT) No. 7105-1/11 0.4 LB11822 Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage range 1 Voltage output current LD output current Symbol VCC IREG ILD Conditions Ratings 9.5 to 28 0 to – 30 0 to 15 Unit V mA mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24 V Parameter Supply Current 1 Supply Current 2 [Output Block] Output saturation voltage 1 Output saturation voltage 2 Output leakage current Lower side diode forward voltage 1 Lower side diode forward voltage 2 [5 V Voltage Output] Output voltage Voltage regulation Load regulation [Hall Amplifier] Input bias current Common-mode input voltage range Hall input sensitivity Hysteresis Input voltage low→ high Input voltage high→ low [PWM Oscillator Circuit] High-level output voltage Low-level output voltage Oscillator frequency Amplitude [CSD Circuit] Operating voltage External C charging current Operating time [Current Limiter Operation] Limiter [Thermal Shutdown Operation] Thermal shutdown operating temperature Hysteresis [FG Amplifier] Input offset voltage Input bias current Output H level voltage Output L level voltage FG input sensitivity Schmitt amplitude for the next stage Operating frequency range Open-loop gain Note: * These are design target values and are not tested. f(FG) = 2 kHz 45 51 VIO(FG) IB(FG) VOH(FG) VOL(FG) IFGO = –0.2 mA IFGO = 0.2 mA Gain: 100 Design target value* 3 100 180 250 2 –10 –1 VREG–1.2 VREG–0.8 0.8 1.2 +10 +1 mV µA V V mV mV kHz dB TSD ∆TSD Design target value* (junction temperature) Design target value* (junction temperature) 150 180 50 °C °C VRF VCC–VM 0.45 0.5 0.55 V VOH(CSD) ICHG T(CSD) C = 10 µF Design target value* 3.6 –17 3.9 –12 3.3 4.2 –9 V µA s VOH(PWM) VOL(PWM) f(PWM) V(PWM) C = 3900 pF 1.05 2.5 1.2 2.8 1.5 18 1.30 1.55 3.1 1.8 V V kHz VP-P ∆VIN VSLH VSHL IHB VICM –2 1.5 80 15 24 12 –12 42 –0.5 VREG–1.5 µA V mVP-P mV mV mV VREG ∆VREG1 ∆VREG2 IO = –5 mA VCC = 9.5 to 28 V IO = –5 to –20 mA 4.65 5.00 30 20 5.35 100 100 V mV mV VOsat1 VOsat2 IOleak VD1 VD2 ID = –1.0 A ID = –2.0 A 1.2 1.5 IO = 1.0 A, VO (SINK)+ VO (SOURCE) IO = 2.0 A, VO (SINK)+ VO (SOURCE) 2.0 2.6 2.5 3.2 100 1.5 2.0 V V µA V V Symbol ICC1 ICC2 When stopped Conditions Ratings min typ 23 3.5 max 30 5 Unit mA mA Continued on next page. No. 7105-2/11 LB11822 Continued from preceding page. Parameter [Speed Discriminator] Output H level voltage Output L level voltage Number of counts [PLL Output] Output H level voltage Output L level voltage [Lock Detection] Output L level voltage Lock range [Integrator] Input bias current Output H level voltage Output L level voltage Open-loop gain Gain width product Reference voltage [Clock Input Pin] Operating frequency range L level pin voltage H level pin current [Start/Stop Pin] H level input voltage range L level input voltage range Input open voltage Hysteresis H level input current L level input current [Forward/Reverse Pin] H level input voltage range L level input voltage range Input open voltage Hysteresis H level input current L level input current VIH(F/R) VIL(F/R) VIO(F/R) ∆VIN IIH(F/R) IIL(F/R) V(F/R) = VREG V(F/R) = 0 V 3.5 0 VREG–0.5 0.35 –10 –280 0.50 0 –210 VREG 1.5 VREG 0.65 +10 V V V V µA µA VIH(S/S) VIL(S/S) VIO(S/S) ∆VIN IIH(S/S) IIL(S/S) V(S/S) = VREG V(S/S) = 0 V 3.5 0 VREG–0.5 0.35 –10 –280 0.50 0 –210 VREG 1.5 VREG 0.65 10 V V V V µA µA fOSC VOSCL IOSCH IOSC = –0.5 mA VOSC = VOSCL+0.5 V 1.55 0.4 1 MHz V mA IB(INT) VOH(INT) IINTO = –0.2 mA VOL(INT) IINTO = 0.2 mA f(INT) = 1 kHz Design target value* Design target value* –5% 45 –0.4 VREG–1.2 VREG–0.8 0.8 51 450 VREG/2 5% 1.2 +0.4 µA V V dB kHz V VOL(LD) ILD = 10 mA 0.15 6.25 0.5 V % VOH(P) VOL(P) IPO = –0.1 mA IPO = 0.1 mA VREG–1.8 VREG–1.5 1.2 1.5 VREG–1.2 1.8 V V VOH(D) VOL(D) IDO = –0.1 mA IDO = 0.1 mA VREG–1.0 VREG–0.7 0.8 512 1.1 V V Symbol Conditions Ratings min typ max Unit Note: * These are design target values and are not tested. No. 7105-3/11 LB11822 Infinitely large heat sink Allowable power dissipation, Pdmax—W Independent IC Ambient temperature, Ta —°C Truth Table Source Sink 1 2 3 4 5 6 OUT2 → OUT1 OUT3 → OUT1 OUT3 → OUT2 OUT1 → OUT2 OUT1 → OUT3 OUT2 → OUT3 IN1 H H H L L L F/R = "L" IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = "H" IN2 H H L L L H IN3 L H H H L L The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation. fFG(servo) = fCLK/ = fCLK/512 Pin Assignment OUT1 28 F/R 27 IN3+ 26 IN325 IN2+ 24 IN223 IN1+ 22 IN1- GND1 21 20 S/S 19 FGIN+ FGIN- FGOUT LD 18 17 16 15 LB11822 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUT2 OUT3 GND2 VCC VM VREG PWM CSD XI XO INTOUT INTIN POUT DOUT Top view No. 7105-4/11 LB11822 Equivalent Circuit Block Diagram and Peripheral Circuits No. 7105-5/11 LB11822 Pin Function Pin No. 28 1 2 Pin OUT1 OUT2 OUT3 Function Equivalent circuit Motor drive output pin Connect the Schottky diode between the output – VCC. VCC 300 Ω VM 5 3 GND2 Output GND pin 1 Power and output current detection pins of the output. Connect a low resistance (Rf) between this pin and VCC. The output current is limited to the current value set with IOUT = VRF/Rf. 2 28 5 VM 3 4 VCC Power pin (Other than the output) VCC Stabilized power supply output pin (5 V output) 6 VREG Connect a capacitor (about 0.1 µF) between this pin and GND for stabilization 6 VREG Pin to set the PWM oscillation frequency. 7 PWM Connect a capacitor between this pin and GND. This can be set to about 18 kHz with C =3900 pF. 200 Ω 2 kΩ 7 VREG Pin to set the operation time of motor lock protection circuit. 8 CSD Continued on next page. 1 kΩ Connection of a capacitor (about 10 µF) between CSD and GND can set the protection operation time of about 3.3seconds. 300 Ω 8 No. 7105-6/11 LB11822 Continued from preceding page. Pin No. Pin Function VREG Equivalent circuit 9 10 XI XO Clock input pin, which enters the clock signal (1 MHz or less) to the XI pin via resistor (about 5.1 kΩ). Keep the XO pin open. 10 9 VREG 11 INT OUT Integrating amplifier output (speed control pin). 40 kΩ 11 PWM Comparator VREG 12 INT IN Integrating amplifier input pin 300 Ω 12 VREG 300 Ω 13 13 POUT PLL output pin Continued on next page. No. 7105-7/11 LB11822 Continued from preceding page. Pin No. Pin Function Equivalent circuit VREG 14 DOUT Speed discriminator output. Accelerate: high, decelerate: low 300 Ω 14 VREG 15 Speed lock detection output. 15 LD L when the motor speed is within the speed lock range (±6.25%). Voltage resistance 30 Vmax VREG 16 FG OUT FG amplifier output pin 16 40 kΩ FG schmidt comparator VREG 17 FGIN– FG Reset FG amplifier input pin. Connection of a capacitor (about 0.1 µF) between FGIN+ and GND causes initial reset to the logic circuit. 20 kΩ 18 300 Ω 20 kΩ 300 Ω 17 18 FGIN+ VREG Start/stop control pin. Low: 0 V to 1.5 V 19 S/S High: 3.5 V to VREG H level when open. Hysteresis width about 0.5 V 22 kΩ 2 kΩ 19 Continued on next page. No. 7105-8/11 LB11822 Continued from preceding page. Pin No. 20 Pin GND1 Function GND pin (Other than the output) Equivalent circuit VREG 22 21 24 23 26 25 IN1+ IN1– IN2+ IN2– IN3+ IN3– Hall amplifier input. IN+ > IN– is the input high state, and the reverse is the input low state. It is recommended that the Hall signal has an amplitude of 100m Vp-p (differential) or more. Connect a capacitor between the IN+ and IN– inputs if there is noise in the Hall sensor signals. 300 Ω 300 Ω 21 23 25 22 24 26 VREG Forward/reverse control pin Low: 0 V to 1.5 V 27 F/R High: 3.5 V to VREG H level when open Hysteresis width about 0.5 V 22 kΩ 2 kΩ 27 Overview of the LB11822 1. Speed control circuit This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase error signal once for each cycle of FG. As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock frequency. fFG(servo) = fCLK/512 fCLK: Clock frequency This IC achieves variable speed control with ease when combined with LB11825M. 2. Output drive circuit This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky diode externally. 3. Current limiting circuit The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp, Rf: current detector resistance) (that is, this circuit limits the peak current). Limiting operation includes decrease in the output on-duty to suppress the current. No. 7105-9/11 LB11822 4. Power save circuit This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given. 5. Reference clock This is entered from the external signal source (1 MHz max) via a resistor (reference: about 5.1 kΩ) in series with the XI pin. The XO pin is left open. Input signal source levels: Low-level voltage: 0 to 0.8 V High-level voltage: 2.5 to 5.0 V 6. Speed lock range The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive output changes according to the speed error, causing control to keep the motor speed within the lock range. 7. PWM frequency PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin. fPWM ≈ 1/(14,400 × C) It is recommended to keep the PWM frequency at 15 kHz to 25 kHz 8. Hall input signal The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42 mV max). Considering the effect of noise, the input with the amplitude of 100 mV or more is recommended. 9. F/R changeover Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay attention to following points. • For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is necessary to prevent exceeding of the rated voltage (30 V) due to rise of VCC voltage at a time of changeover (because the motor current returns instantaneously to the power supply). When this problem exists, increase the capacity of a capacitor between VCC and GND. • When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (3.1 A). (F/R changeover at high speed is dangerous.) 10. Motor lock protection circuit A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked. When the LD output is “H” (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with the capacity of 10 µF (variance about ±30%). Set time (s) ≈ 0.33 × C (µF) When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time, etc. Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock protection circuit is not to be used, connect the CSD pin to GND. When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to restart in the motor start transient condition.) No. 7105-10/11 LB11822 Stop time (ms) ≥ 15 × C (µF) 11. Power supply stabilization This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is therefore necessary to connect a capacitor with a sufficient capacity between the VCC pin and GND for stabilization. When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power line is particularly readily oscillated. The larger capacity need be selected. 12. Constant of integrating amplifier parts Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange them by keeping the largest possible distance from the motor. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2003. Specifications and information herein are subject to change without notice. PS No. 7105-11/11