LB11826_08

Ordering number : EN7109A Monolithic Digital IC LB11826 Overview For OA Products Three-Phase Brushless Motor Driver The LB11826 is a three-phase brushless motor driver that is optimal for driving drum and paper feed motors in laser printers and plain paper copiers. This IC adopts a direct PWM drive technique for minimal power loss. Flexible control of motor speed in response to an externally provided clock frequency (corresponding to the FG frequency) can be implemented by using the LB11826 in conjunction with the Sanyo LB11825M. Features • Three-phase bipolar drive (30V, 2.5V) • Direct PWM drive • Built-in low side inductive kickback absorbing diode • Speed discriminator + PLL speed control • Speed locked state detection output • Built-in forward/reverse switching circuit • Full complement of built-in protection circuits, including current limiter circuit, thermal protection circuit, and motor constraint protection circuit. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Allowable power dissipation Symbol VCC max IO max Pd max1 Pd max2 Operating temperature Storage temperature Topr Tstg T ≤ 500ms Independent IC When infinitely large heat sink Conditions Ratings 30 2.5 3 20 -20 to +80 -55 to +150 Unit V A W W °C °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 71608 MS PC/O0503AS (OT) No.7109-1/11 LB11826 Allowable Operating Conditions at Ta = 25°C Parameter Supply voltage range 1 Voltage output current LDn output current Symbol VCC IREG ILD Conditions Ratings 9.5 to 28 0 to -30 0 to 15 Unit V mA mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Parameter Supply current 1 Supply current 2 Output block Output saturation voltage 1 Output saturation voltage 2 Output leakage current Lower side diode forward voltage 1 Lower side diode forward voltage 2 5V Voltage output Output voltage Voltage regulation Load regulation Hall Amplifier Input bias current Common-mode input voltage range Hall input sensitivity Hysteresis width Input voltage low → high Input voltage high → low PWM oscillator circuit Output H level voltage Output L level voltage Oscillator frequency Amplitude CSD circuit Operating voltage External C charge current Operating time Current limiter operation Limiter Thermal shutdown operation Thermal shutdown operating temperature Hysteresis width FG amplifier Input offset voltage Input bias current Output H level voltage Output L level voltage FG input sensitivity Schmitt amplitude for the next stage Operation frequency range Open-loop gain f (FG) = 2kHz 45 51 VIO (FG) IB (FG) VOH (FG) VOL (FG) IFGO = -0.2mA IFGO = 0.2mA Gain 100-fold Design target value* 3 100 180 250 2 -10 -1 VREG-1.2 VREG-0.8 0.8 1.2 10 1 mV μA V V mV mV kHz dB ΔTSD Design target value* (junction temperature) 50 °C TSD Design target value* (junction temperature) 150 180 °C VRF VCC-VM 0.45 0.5 0.55 V VOH (CSD) ICHG T (CSD) C = 10μF, Design target value* 3.6 -17 3.9 -12 3.3 4.2 -9 V μA s VOH (PWM) VOL (PWM) f (PWM) V (PWM) C = 3900pF 1.05 2.5 1.2 2.8 1.5 18 1.30 1.55 3.1 1.8 V V kHz Vp-p ΔVIN VSLH VSHL IHB VICM -2 1.5 80 15 24 12 -12 42 -0.5 VREG-1.5 μA V mVp-p mV mV mV VREG ΔVREG1 ΔVREG2 IO = -5mA VCC = 9.5 to 28V IO = -5 to -20mA 4.65 5.00 30 20 5.35 100 100 V mV mV VO sat1 VO sat2 IO leak VD1 VD2 ID = -1.0A ID = -2.0A 1.2 1.5 IO = 1.0A, VO (sink) + (source) IO = 2.0A, VO (sink) + (source) 2.0 2.6 2.5 3.2 100 1.5 2.0 V V μA V V Symbol ICC1 ICC2 Stop mode Conditions min Ratings typ 23 3.5 max 30 5 mA mA Unit Note : * These items are design target values and are not tested. Continued on next page. No.7109-2/11 LB11826 Continued from preceding page. Parameter Speed discriminator Output H level voltage Output L level voltage Number of counts PLL output Output H level voltage Output L level voltage Lock detection Output L level voltage Lock range Integrator Input bias current Output H level voltage Output L level voltage Open-loop gain Gain width product Reference voltage Clock input pin Operating frequency range L level pin voltage H level pin current Start/Stop pin H level input voltage range L level input voltage range Input open voltage Hysteresis width H level input current L level input current Forward/Reverse pin H level input voltage range L level input voltage range Input open voltage Hysteresis width H level input current L level input current VIH (F/R) VIL (F/R) VIO (F/R) ΔVIN IIH (F/R) IIL(F/R) V (F/R) = VREG V (F/R) = 0V 3.5 0 VREG-0.5 0.35 -10 -280 0.50 0 -210 VREG 1.5 VREG 0.65 10 V V V V μA μA VIH (S/S) VIL (S/S) VIO (S/S) ΔVIN IIH (S/S) IIL(S/S) V (S/S) = VREG V (S/S) = 0V 3.5 0 VREG-0.5 0.35 -10 -280 0.50 0 -210 VREG 1.5 VREG 0.65 10 V V V V μA μA fOSC VOSCL IOSCH IOSC = -0.5mA VOSC = VOSCL + 0.5V 1.55 0.4 1 MHz V mA IB (INT) VOH (INT) VOL (INT) IINTO = -0.2mA IINTO = 0.2mA f (INT) = 1kHz Design target value* Design target value* -5% 45 -0.4 VREG-1.2 VREG-0.8 0.8 51 450 VREG/2 5% 1.2 0.4 μA V V dB kHz V VOL (LD) ILD = 10mA 0.15 6.25 0.5 V % VOH (P) VOL (P) IPO = -0.1mA IDO = 0.1mA VREG-1.8 1.2 VREG-1.5 1.5 VREG-1.2 1.8 V V VOH (D) VOL (D) IDO = -0.1mA IDO = 0.1mA VREG-1.0 VREG-0.7 0.8 512 1.1 V V Symbol Conditions min Ratings typ max Unit Note : * These items are design target values and are not tested. No.7109-3/11 LB11826 Package Dimensions unit : mm (typ) 3174C 24 Pd max – Ta Infinitely large heat sink 28 15 Allowable power dissipation, Pd max – W 20 12.7 11.2 8.4 R1.7 16 0.4 12 1 20.0 26.75 14 8 4.0 4 3 With no heat sink 4.0 (1.81) 0 – 20 0 20 40 60 80 100 1.78 0.6 1.0 Ambient temperature, Ta – °C SANYO : DIP28H(500mil) Pin Assignment OUT1 28 F/R 27 IN3+ 26 IN325 IN2+ 24 IN223 IN1+ 22 IN121 GND1 20 S/S 19 FGIN+ FGIN- FGOUT 18 17 16 LD 15 LB11826 Top view 1 2 3 4 VCC 5 VM 6 VREG 7 PWM 8 CSD 9 XI 10 XO 11 12 13 14 OUT2 OUT3 GND2 INTOUT INTIN POUT DOUT Truth Table Source Sink 1 2 3 4 5 6 OUT2 → OUT1 OUT3 →OUT1 OUT3 → OUT2 OUT1 → OUT2 OUT1 → OUT3 OUT2 → OUT3 IN1 H H H L L L F/R= L IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R= H IN2 H H L L L H IN3 L H H H L L The relation between the clock frequency, fCLK, and the FG frequency, fFG, is given by the following equation. fFG (servo) = fCLK/ = fCLK/512 No.7109-4/11 LD + FGINFGOUT FG AMP INT AMP LD POUT DOUT INT.IN INT.OUT CSD VREG/2 TSD SPEED DISCRI CURR LIM FGIN+ + + + VREG LOCK DET PWM OSC CSD CIRCUIT PWM VCC VCC + Rf VM Block Diagram and Peripheral Circuits COMP FG RST PLL VREF LOGIC 1/512 VREF DRIVER BGP HALL HYS AMP Xtal OSC S/S F/R 5VREG OUT3 OUT2 LB11826 GND1 OUT1 XI S/S XO F/R VREG IN1 IN2 IN3 GND2 H H H CLK IN (LB11825MOUT) No.7109-5/11 LB11826 Pin Functions Pin No. 28 1 2 3 5 Pin name OUT1 OUT2 OUT2 GND2 VM Pin function Motor drive output pin. Connect the Schottky diode between the output VCC. Output GND pin. Power and output current detection pins of the output. Connect a low resistance (Rf) between this pin and VCC. The output current is limited to the current value set with IOUT = VRF/Rf. Equivalent circuit VCC 300Ω VM 5 1 2 28 3 4 6 VCC VREG Power pin (Other than the output). Stabilized power supply output pin (5V output). Connect a capacitor (about 0.1μF) between this pin and GND for stabilization. VCC 6 7 PWM Pin to set the PWM oscillation frequency. Connect a capacitor between this pin and GND. This can be set to about 18kHz with C = 3900pF. VREG 200Ω 2kΩ 7 8 CSD Pin to set the operation time of motor lock protection circuit. Connection of a capacitor (about 10μF) between CSD and GND can set the protection operation time of about 3.3seconds. VREG 300Ω 1kΩ 8 Continued on next page. No.7109-6/11 LB11826 Continued from preceding page. Pin No. 9 10 Pin name XI XO Pin function Clock input pin, which enters the clock signal (1MHz or less) to the XI pin via resistor (about 5.1kΩ). Keep the XO pin open. Equivalent circuit VREG 10 9 11 INTOUT Integrating amplifier output (speed control pin). VREG 11 40kΩ PWM Comparator 12 INTIN Integrating amplifier input pin. VREG 300Ω 12 13 POUT PLL output pin. VREG 300Ω 13 Continued on next page. No.7109-7/11 LB11826 Continued from preceding page. Pin No. 14 Pin name DOUT Pin function Speed discriminator output. Accelerate : high, decelerate : low. Equivalent circuit VREG 300Ω 14 15 LD Speed lock detection output. L when the motor speed is within the speed lock range (±6.25%). Voltage resistance 30V max. VREG 15 16 FGOUT FG amplifier output pin. VREG 16 FG schmitt comparator 17 18 FGINFGIN+ FG amplifier input pin. Connection of a capacitor (about 0.1μF) between FGIN and GND causes initial reset to the logic circuit. VREG 20kΩ FG Reset 300Ω 20kΩ 300Ω 18 40kΩ 17 19 S/S Start/stop control pin. Low : 0V to 1.5V High : 3.5V to VREG H level when open. Hysteresis width about 0.5V. VREG 22kΩ 2kΩ 19 20 GND1 GND pin (Other than the output). Continued on next page. No.7109-8/11 LB11826 Continued from preceding page. Pin No. 22 21 24 23 26 25 Pin name IN1+ IN1IN2+ IN2IN3+ IN3Pin function Hall amplifier input. IN+ > IN- is the input high state, and the reverse is the input low state. It is recommended that the Hall signal has an amplitude of 100mVp-p (differential) or more. Connect a capacitor between the IN+ and IN- inputs if there is noise in the Hall sensor signals. Equivalent circuit VREG 21 23 25 300Ω 300Ω 22 24 26 27 F/R Forward/reverse control pin. Low : 0V to 1.5V High : 3.5V to VREG H level when open. Hysteresis width about 0.5V. VREG 22kΩ 2kΩ 27 LB11826 Description 1. Speed control circuit This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase error signal once for each cycle of FG. As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock frequency. fFG (servo) = fCLK/512 fCLK : Clock frequency This IC achieves variable speed control with ease when combined with LB11825M. 2. Output drive circuit This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or schottky diode externally. 3. Current limiting circuit The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5Vtyp, Rf : current detector resistance) (that is, this circuit limits the peak current). Limiting operation includes decrease in the output on-duty to suppress the current. 4. Power save circuit This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given. 5. Reference clock This is entered from the external signal source (1MHz max) via a resistor (reference : about 5.1kΩ) in series with the XI pin. The XO pin is left open. Input signal source levels : Low-level voltage : 0 to 0.8V High-level voltage : 2.5 to 5.0V No.7109-9/11 LB11826 6. Speed lock range The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive output changes according to the speed error, causing control to keep the motor speed within the lock range. 7. PWM frequency PWM frequency is determined from the capacity C (F) of capacitor connected to the PWM pin. fPWM ≈ 1/ (14,400 × C) It is recommended to keep the PWM frequency at 15k - 20kHz. 8. Hall input signal The Hall input requires the signal input with an amplitude exceeding the hysteresis width (42mV max). Considering the effect of noise, the input with the amplitude of 100mV or more is recommended. 9. F/R changeover Motor rotation direction can be changed over with the F/R pin. When changing F/R while the motor is running, pay attention to following points. • For the through current at a time of changeover, the countermeasure is taken using a circuit. However, it is necessary to prevent exceeding of the rated voltage (30V) due to rise of VCC voltage at a time of changeover (because the motor current returns instantaneously to the power supply). When this problem exists, increase the capacity of a capacitor between VCC and GND. • When the motor current exceeds the current limit value after changeover, the lower-side Tr is turned OFF. But, the upper-side Tr enters the short-brake condition and the current determined from the motor counter electromotive voltage and coil resistance flows. It is necessary to prevent this current from exceeding the rated current (2.5A). (F/R changeover at high motor speed is dangerous.) 10. Motor lock protection circuit A motor lock protection circuit is incorporated for protection of IC and motor when the motor is locked. When the LD output is “H” (unlocked) for a certain period in the start condition, the lower-side Tr is turned OFF. This time is set with the capacity of the capacitor connected to the CSD pin. The time can be set to about 3.3 seconds with the capacity of 10μF (variance about ±30%). Set time (s) ≈ 0.33 × C (μF) When the capacitor used has a leak current, due consideration is necessary because it may cause error in the set time, etc. Cancelling requires either the stop condition or re-application of power supply (in the stop condition). When the lock protection circuit is not to be used, connect the CSD pin to GND. When the stop period during which lock protection is to be cancelled is short, the charge of capacitor cannot be discharged completely and the lock protection activation time at restart becomes shorter than the set value. It is necessary to provide the stop time with an allowance while referring to the following equation. (The same applies to restart in the motor start transient condition.) Stop time (ms) ≥ 15 × C (μF) 11. Power supply stabilization This IC has a large output current and is driven by switching, resulting in ready oscillation of the power line. It is therefore necessary to connect a capacitor with a sufficient capacity between the VCC pin and GND for stabilization. When a diode is inserted in the power line to prevent breakdown due to reverse connection of power supply, the power line is particularly readily oscillated. The larger capacity need be selected. 12. Constant of integrating amplifier parts Arrange the integrating amplifier external parts as near as possible to IC to protect them from noise effects. Arrange them by keeping the largest possible distance from the motor. No.7109-10/11 LB11826 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2008. Specifications and information herein are subject to change without notice. PS No.7109-11/11