LB1929_08

Ordering number : EN7099A Monolithic Digital IC LB1929 Overview For Office Automation Equipment 3-phase Brushless Motor Driver The LB1929 is a 3-phase brushless motor driver well suited for drum and paper feed motors in laser printers, plain-paper copiers and other office automation equipment. Direct PWM drive allows control with low power losses. Peripheral circuitry including speed control circuit and FG amplifier is integrated, thus allows drive circuit to be constructed with a single chip. Features • 3-phase bipolar drive (30V, 3.5A) • Direct PWM drive technique • Built-in diode for absorbing output lower-side kickback • Speed discriminator and PLL speed control • Speed lock detection output • Built-in forward/reverse switching circuit • Built-in protection circuitry includes current limiter, overheat protection, motor restraint protection, etc. Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Maximum output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max 1 Pd max 2 Topr Tstg T ≤ 500ms Independent IC With an arbitrary large heat sink Conditions Ratings 30 3.5 3 20 -20 to +80 -55 to +150 Unit V A W W °C °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D0308 MS JM/71202RM(OT) No.7099-1/11 LB1929 Allowable Operating Ranges at Ta = 25°C Parameter Power supply voltage range 1 Regulator voltage output current LD output current Symbol VCC IREG ILD Conditions Ratings 9.5 to 28 0 to -30 0 to 15 Unit V mA mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Ratings Parameter Power supply current 1 Power supply current 2 Output Output saturation voltage 1 Output saturation voltage 2 Output leak current Lower-side diode forward voltage 1 Lower-side diode forward voltage 2 5V regulator voltage output Output voltage Voltage fluctuation Load fluctuation Hall amplifier Input bias current Common mode input voltage range Hall input sensitivity Hysteresis width Input voltage L→H Input voltage H→L PWM oscillator Output High level voltage Output Low level voltage Oscillator frequency Amplitude CSD circuit Operating voltage External capacitance charge current Operating time Current limiter operation Limiter Thermal shutdown operation Thermal shutdown operating temperature Hysteresis width FG amplifier Input offset voltage Input bias current Output High level voltage Output Low level voltage FG input sensitivity Next-stage Schmitt comparator width Operation frequency range Open-loop gain f (FG) = 2kHz 45 51 2 kHz dB VIO (FG) IB (FG) VOH (FG) VOL (FG) IFGO = -0.2mA IFGO = 0.2mA GAIN 100 times Design target value* 3 100 180 250 -10 -1 VREG-1.2 VREG-0.8 0.8 1.2 +10 +1 mV µA V V mV mV ∆TSD Design target value (junction temperature) 50 °C TSD Design target value (junction temperature) 150 180 °C VRF VCC-VM 0.45 0.5 0.55 V T (CSD) C = 10µF Design target value 3.3 s VOH (CSD) ICHG 3.6 -17 3.9 -12 4.2 -9 V µA VOH (PWM) VOL (PWM) F (PWM) V (PWM) C = 3900pF 1.05 2.5 1.2 2.8 1.5 18 1.30 1.55 3.1 1.8 V V kHz Vp-p ∆VIN VSLH VSHL IHB VICM -2 1.5 80 15 24 12 -12 42 -0.5 VREG-1.5 µA V mVp-p mV mV mV VREG ∆VREG1 ∆VREG2 IO = -5mA VCC = 9.5 to 28V IO = -5 to -20mA 4.65 5.00 30 20 5.35 100 100 V mV mV VOsat1 VOsat2 IOleak VD1 VD2 ID = -1.0A ID = -2.0A 1.2 1.5 IO = 1.0A, VO (SINK) +VO (SOURCE) IO = 2.0A, VO (SINK) +VO (SOURCE) 2.0 2.6 2.5 3.2 100 1.5 2.0 V V µA V V Symbol ICC1 ICC2 In STOP mode Conditions min typ 23 3.5 max 30 5.0 Unit mA mA Note*: These items are design target values and are not tested. Continued on next page. No.6197-2/11 LB1929 Continued from preceding page. Ratings Parameter Speed discriminator Output High level voltage Output Low level voltage Count number PLL output Output High level voltage Output Low level voltage Lock detection Output Low level voltage Lock range Integrator Input bias current Output High level voltage Output Low level voltage Open-loop gain Gain bandwidth product Reference voltage Crystal oscillator Operating frequency range Low level pin voltage High level pin current Start/stop pin High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current Forward/reverse pin High level input voltage range Low level input voltage range Input open voltage Hysteresis width High level input current Low level input current VIH (F/R) VIL (F/R) VIO (F/R) ∆VIN IIH (F/R) IIL (F/R) V (F/R) = VREG V (F/R) = 0V 3.5 0 VREG-0.5 0.35 -10 -280 0.50 0 -210 VREG 1.5 VREG 0.65 +10 V V V V µA µA VIH (S/S) VIL (S/S) VIO (S/S) ∆VIN IIH (S/S) IIL (S/S) V (S/S) = VREG V (S/S) = 0V 3.5 0 VREG-0.5 0.35 -10 -280 0.50 0 -210 VREG 1.5 VREG 0.65 10 V V V V µA µA fOSC VOSCL IOSCH IOSC = -0.5mA VOSC = VOSCL+0.3V 3 1.65 0.4 10 MHz V mA IB (INT) VOH (INT) VOL (INT) IINTO = -0.2mA IINTO = 0.2mA f (INT) = 1kHZ Design target value* Design target value* -5% 45 -0.4 VREG-1.2 VREG-0.8 0.8 51 450 VREG/2 5% 1.2 0.4 µA V V dB kHz V VOL (LD) ILD = 10mA 0.15 6.25 0.5 V % VOH (P) VOL (P) IPO = -0.1mA IPO = 0.1mA VREG-1.8 1.2 VREG-1.5 1.5 VREG-1.2 1.8 V V VOH (D) VOL (D) IDO = -0.1mA IDO = 0.1mA VREG-1.0 VREG-0.7 0.8 512 1.1 V V Symbol Conditions min typ max Unit Note*: These items are design target values and are not tested. No.6197-3/11 LB1929 Package Dimensions unit : mm (typ) 3147C 24 Pd max -- Ta Allowable power dissipation, Pd max -- W With an arbitrary large heat sink 20 16 12 8 4 3 Without heat sink 0 -20 0 20 40 60 80 100 Ambient temperature, Ta -- °C Pin Assignment OUT1 28 F/R 27 IN3+ 26 IN325 IN2+ 24 IN223 IN1+ 22 IN121 GND1 20 S/S 19 FGIN+ FGIN- FGOUT 18 17 16 LD 15 LB1929 1 2 3 4 VCC 5 VM 6 7 8 CSD 9 XI 10 11 12 13 14 OUT2 OUT3 GND2 VREG PWM XO INTOUT INTIN POUT DOUT Top view Relationship between crystal oscillator frequency fOSC and FG frequency fFG is as follows. fFG (servo) = fOSC/ (ECL divide-by-16×count number) = fOSC/8192 Truth Table Source Sink 1 2 3 4 5 6 OUT2→OUT1 OUT3→OUT1 OUT3→OUT2 OUT1→OUT2 OUT1→OUT3 OUT2→OUT3 IN1 H H H L L L F/R = “L” IN2 L L H H H L IN3 H L L L H H IN1 L L L H H H F/R = “H” IN2 H H L L L H IN3 L H H H L L No.6197-4/11 LB1929 Block Diagram and Sample Application Circuit LD + FGINFG AMP – FGIN+ + FGOUT LD POUT DOUT INTIN – INT AMP INTOUT CSD LOCK DET – + VREG VREG/2 + CSD CIRCUIT TSD PWM OSC PWM SPEED DISCRI CURR LIM VCC VCC + Rf VM COMP FG RST VREF GND1 ECL 1/16 1/512 PLL OUT1 VREF BGP HALL HYS AMP LOGIC DRIVER OUT2 Xtal OSC S/S F/R 5VREG OUT3 XI XO S/S F/R VREG IN1 IN2 IN3 GND2 H H H No.6197-5/11 LB1929 Pin Description Pin No. 28 1 2 3 5 Pin name OUT1 OUT2 OUT3 GND2 VM Output ground pin. Output block power supply and output current detection pin. Connect a resistor (Rf) between this pin and VCC to detect the output current as a voltage. The output current is limited according to the equation IOUT = VRF/Rf. Motor drive output pins. Connect a Schottky diode between these outputs and VCC. Pin function Equivalent circuit 4 6 VCC VREG Power supply pin (except for output block). Regulated power supply output pin (5V output). Connect a capacitor (approx. 0.1µF) between this pin and ground to stabilize the output. 7 PWM PWM frequency setting pin. Connect a capacitor between this pin and ground. C = 3900pF results in a frequency of about 18kHz. 8 CSD Lock protection circuit operation time setting pin. Connecting a capacitor of about 10µF between this pin and ground results in a protection circuit operation time of about 3.3 seconds. 9 10 XI XO Crystal oscillator pins. Connect to quartz oscillator to generate the reference clock. When an external clock (of several MHz) is used, the clock signal should be input via a resistor of about 5.1kΩ connected in series with the XI pin. In this case, the XO pin must be left open. Continued on next page. No.6197-6/11 LB1929 Continued from preceding page. Pin No. 11 Pin name INTOUT Pin function Integrator output pin (speed control pin). Equivalent circuit 12 INTIN Integrator input pin. 13 POUT PLL output pin. 14 DOUT Speed discriminator output pin. Acceleration : High, Deceleration : Low 15 LD Speed lock detection pin. When motor rotation is within lock range (±6.25%) : Low Withstand voltage : 30V max. Continued on next page. No.6197-7/11 LB1929 Continued from preceding page. Pin No. 16 Pin name FGOUT Pin function FG amplifier output pin. Equivalent circuit 17 18 FGINFGIN+ FG amplifier input pin. By connecting a capacitor (approx. 0.1µF) between FGIN+ and ground, the logic circuitry is reset. 19 S/S Start/stop control pin. Start (Low) : 0V to 1.5V Stop (High) : 3.5V to VREG High when open. Hysteresis width : approx. 0.5V. 20 22 21 24 23 26 25 GND1 IN1+ IN1IN2+ IN2IN3+ IN3- Ground pin (except for output block). Hall input pins. High when IN+ > IN-, Low when IN+ < IN-. Hall signal should have an amplitude of at least 100mVp-p (differential operation). When Hall signal noise is a problem, connect a capacitor between IN+ and IN-. 27 F/R Forward/reverse control pin. Forward (Low) : 0V to 1.5V Reverse (High) : 3.5V to VREG High when open. Hysteresis width : approx. 0.5V. No.6197-8/11 LB1929 Description of the LB1927 1. Speed control circuit The IC performs speed control through combined use of a speed discrimination circuit and PLL circuit. The speed control circuit counts FG cycles and outputs a deviation signal every 2FG cycles. The PLL circuit outputs a phase deviation signal every FG cycle. The FG servo frequency is determined by the following equation. The motor rotation speed is set by the number of FG pulses and the crystal oscillator frequency. fFG (servo) = fOSC/8192 fOSC : Crystal oscillator frequency 2. Output drive circuit In order to reduce power loss at the output, the LB1929 uses the PWM drive technique. While ON, the output transistors are always saturated, and motor drive power is adjusted by varying the output ON duty ratio. Because output PWM switching is performed by the lower-side output transistor, a Schottky diode must be connected between OUT and VCC. (If the reverse recovery time of the diode is too long, a feedthrough current will flow at the instant when the lower-side transistor goes ON.) An internal diode is provided between OUT and GND. If large output current causes a problem (waveform distortion during lower-side kickback, etc.), an external rectifying diode or Schottky diode should be connected. The output diode is integrated only on the lower side. 3. Current limiting circuit The current limiting circuit limits the peak current to the value I = VRF/Rf (VRF = 0.5V typ., Rf : current detector resistance). Current limiting is achieved by reducing the ON duty ratio of the output, which reduces the current. 4. Power save circuit In order to reduce current drain in the STOP condition, the IC goes into power save mode. In this condition, bias current to most circuits is cut off, but the 5V regulator output remains active. 5. Reference clock The reference clock for speed control can be input using one of the following two methods. (1) Using a crystal oscillator When a crystal is used for oscillation, connect the crystal, capacitors, and a resistor as shown in the figure below. XI C3 XO C4 C1 R1 C2 C1, R1 : For stable oscillation C3 : For oscillator coupling C2 : For stabilization and to prevent oscillation at upper harmonic frequencies C4 : Prevents oscillation at upper harmonic frequencies VREG (Reference values) Oscillator frequency (MHz) 3 to 5 5 to 8 8 to 10 C1 (µF) 0.1 0.1 0.1 C2 (pF) 15 10 10 C3 (pF) 47 47 22 C4 (pF) 10 None None R1 (Ω) 330k 330k 330k The circuit configuration and values are for reference only. The crystal oscillator’s characteristics as well as the possibility of floating capacitance and noise due to layout factors must be taken into consideration when designing an actual application. No.6197-9/11 LB1929 [Precautions for wiring layout design] Since the crystal oscillator circuit operates at high frequencies, it is susceptible to the influence of floating capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept narrow. When designing the external circuitry, pay special attention to the wiring layout between the oscillator and C3 (C2), to minimize the influence of floating capacitance. The capacitor C4 is quite effective at reducing the negative resistance (gain) at high frequencies. However, care is required to avoid excessive reduction in the negative resistance at the fundamental frequency. (2) External clock input (equivalent to crystal oscillator, several MHz) When using an external signal source instead of a crystal oscillator, the clock signal should be input from the XI pin through a resistor of about 5.1kΩ connected to the pin in series. The XO pin should be left open. Signal input level Low : 0 to 0.8V High : 2.5 to 5.0V 6. Speed lock range The speed clock range is ±6.25% of the rated speed. When the motor rotation is within the lock range, the LD pin becomes Low (open collector output). When the motor rotation goes out of the lock range, the ON duty ratio of the motor drive output is varied according to the amount of deviation to bring the rotation back into the lock range. 7. PWM frequency The PWM frequency is determined by the capacitance connected to the PWM pin. f PWM ≈ 1/ (14400×C) PWM frequency in the range 15 to 25kHz is desirable. The ground side of the connected capacitor must be connected to the GND1 pin with a lead that is as short as possible. 8. Hall input signal The Hall input requires a signal with an amplitude of at least the hysteresis width (42mV max.). Taking possible noise influences into consideration, an amplitude of at least 100mV is desirable. If noise during output phase switching disrupts the output waveform, insert capacitors across the Hall signal inputs (between the + and - inputs), and position those capacitors as close as possible to the pins. 9. Forward/reverse switching Forward/reverse switching of motor rotation is carried out with the F/R pin. If this is performed while the motor is running, the following points must be observed : • Feedthrough current during switching is handled by proper circuit design. However, the VCC voltage rise during switching (caused by momentary return of motor current to power supply) must not exceed the rated voltage (30V). If problems occur, the capacitance between VCC and GND must be increased. • If the motor current after switching exceeds the current limiter value, the lower-side transistors go OFF but the upper-side transistors go into the short brake state, which causes a current flow. The magnitude of the current is determined by the motor counterelectromotive voltage and the coil resistance. This current may not exceed the rated current (3.5A). (Forward/reverse switching at high speed therefore is not safe.) 10. Motor restraint protection circuit To protect the IC and the motor itself when rotation is inhibited, a restraint protection circuit is provided. If the LD output is High (unlocked) for a certain interval in the start condition, the lower-side transistors are turned off. The length of the interval is determined by the capacitance at the CSD pin. A capacitance of 10µF results in a set interval of about 3.3 seconds. (Tolerance approx. ±30%) Set interval (s) ≈ 0.33×C (µF) If the capacitor arrangement is subject to leak current, possible adverse effects such as setting time tolerances must be taken into consideration. When the restraint protection circuit has been activated, the condition can only be canceled by setting the system to the stop condition or by turning the power off and on again (in the stop condition). When wishing not to use the restraint protection circuit, connect the CSD pin to ground. If the stop time when releasing the restraint protection is short, the capacitor charge will not be fully dissipated. This in turn will cause a shorter restraint protection activation time after the motor has been restarted. The stop time should therefore be designed to be sufficiently long, using the equation shown below (also when restarting in the motor start transient state). Stop time (ms) ≥ 15×C (µF) No.6197-10/11 LB1929 11. Power supply stabilization Because this IC provides a high output current and uses a switching drive technique, power supply line fluctuations can occur easily. Therefore, a capacitor of sufficient capacitance (several ten µF or higher) must be connected between the VCC pin and ground to assure stable operation. The ground connection of this capacitor must be connected to the GND2 pin, which is the power block ground, at a point as close as possible to the IC. If, due to problems associated with the heat sink, the (electrolytic) capacitor cannot be connected near the this pin, a ceramic capacitor of about 0.1µF must be connected near the pin. Since the likelihood of power line fluctuation increases if diodes are inserted in the power supply lines to prevent destruction of the IC if power is connected with reverse polarity, a larger capacitance will be required. 12. VREG stabilization A capacitor (about 0.1µF) must be connected to the VREG pin (the 5V regulator output), which functions as the control circuit power supply, for stabilization. The ground side of this capacitor must be connected to the GND1 pin with a lead that is as short as possible. 13. Integrating amplifier related component values The external components used in the integrating amplifier must be located as close as possible to the IC to minimize the circuit’s susceptibility to noise. These components must be located as far as possible from the motor. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice. PS No.6197-11/11