LC35256D-10

Ordering number : EN5823 CMOS IC LC35256D-10, LC35256DM, DT-70/10 Dual Control Pins: OE and CE 256K (32768-word × 8-bit) SRAM Overview The LC35256D, LC35256DM, and LC35256DT are 32768-word × 8-bit asynchronous silicon gate CMOS static RAMs. These devices use a 6-transistor full CMOS memory cell, and feature low-voltage operation, low current drain, and an ultralow standby current. They provide two control signal inputs: an OE input for highspeed access and a chip select (CE) input for device selection and low power operating mode. This makes these devices optimal for systems that require low power or battery backup, and they allow memory to be expanded easily. Their ultralow standby current allows capacitorbased backup to be used as well. Since they support 3-V operation, they are appropriate for use in portable systems that operate from batteries. Package Dimensions unit: mm 3012A-DIP28 [LC35256D] SANYO: DIP28 unit: mm 3187-SOP28D [LC35256DM] Features • Supply voltage range: 2.7 to 5.5 V — 5-V operation: 5.0 V±10% — 3-V operation: 2.7 to 3.6 V • Access times — 5-V operation LC35256DM, DT-70: 70 ns (max) LC35256D, DM, DT-10: 100 ns (max) — 3-V operation LC35256DM, DT-70: 200 ns (max) LC35256D, DM, DT-10: 500 ns (max) • Standby current — 5-V operation: 1.0 µA (Ta ≤ 60°C), 5.0 µA (Ta ≤ 85°C) — 3-V operation: 0.8 µA (Ta ≤ 60°C), 4.0 µA (Ta ≤ 85°C) • Operating temperature range: –40 to +85°C • Data retention supply voltage: 2.0 to 5.5 V • All I/O levels — 5-V operation: TTL compatible — 3-V operation: VCC – 0.2 V/0.2 V • Shared I/O pins and 3-state outputs • No clock signal required. • Packages — 28-pin DIP (600 mil) plastic package: LC35256D — 28-pin SOP (450 mil) plastic package: LC35256DM — 28-pin TSOP (8 × 13.4 mm) plastic package: LC35256DT SANYO: SOP28D unit: mm 3221-TSOP28(type-I) [LC35256DT] SANYO: TSOP28(type-I) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 51398RM (OT) No. 5823-1/8 LC35256D-10, LC35256DM, DT-70/10 Pin Assignment Block Diagram Address buffer Row decoder Memory cell array Input data buffer Input data control circuit Column I/O circuit Column decoder Output data buffer Address buffer Pin Functions A0 to A14 WE OE CE I/O1 to I/O8 VCC, GND Address inputs Read/write control input Output enable input Chip enable input Data I/O Power supply, ground No. 5823-2/8 LC35256D-10, LC35256DM, DT-70/10 Function Table Mode Read cycle Write cycle Output disable Unselected X : H or L CE L L L H OE L X H X WE H L H X I/O Data output Data input High-impedance High-impedance Supply current ICCA ICCA ICCA ICCS Specifications Absolute Maximum Ratings Parameter Maximum supply voltage Input pin voltage I/O pin voltage Operating temperature Storage temperature Note *: –3.0 V for pulse widths of up to 30 ns. Symbol VCC max VIN VI/O Topr Tstg Conditions Ratings 7.0 –0.3* to VCC + 0.3 –0.3 to VCC + 0.3 –40 to +85 –55 to +125 Unit V V V °C °C I/O Capacitances at Ta = 25°C, f = 1 MHz Parameter I/O pin capacitance Input pin capacitance Symbol CI/O CIN VI/O = 0 V VIN = 0 V Conditions Ratings min typ 6 6 max 10 10 Unit pF pF Note: These parameters are not measured in all units, but rather are only measured in sampled units. [5-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Supply voltage Input voltages Symbol VCC VIH VIL Conditions Ratings min 4.5 2.2 –0.3* typ 5.0 max 5.5 VCC + 0.3 +0.8 Unit V V V Note *: –3.0 V for pulse widths of up to 30 ns. DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V Parameter Input leakage current Output leakage current High-level output voltage Low-level output voltage Symbol ILI ILO VOH VOL ICCA2 Operating current drain TTL inputs ICCA3 VCE = VIL, VIN = VIH or VIL, II/O = 0 mA, Duty 100% VCE ≥ VCC – 0.2 V, VIN = 0 to VCC VCE = VIH, VIN = 0 to VCC VIN = 0 to VCC VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC IOH = –1.0 mA IOL = 2.0 mA VCE = VIL, II/O = 0 mA, VIN = VIH or VIL min LC35256DM, DT-70 35 25 3.5 Ta ≤ 25°C Ta ≤ 60°C Ta ≤ 85°C 0.01 1.0 5.0 1.0 cycle LC35256D, DM, DT-10 1 µs cycle Conditions Ratings min –1.0 –1.0 2.4 0.4 5.0 40 30 6.0 typ* max +1.0 +1.0 Unit µA µA V V mA mA mA mA µA µA µA mA Standby mode current drain VCC – 0.2 V/ 0.2 V inputs TTL inputs ICCS1 ICCS2 Note *: Reference value at Ta = 25°C, VCC = 5 V. No. 5823-3/8 LC35256D-10, LC35256DM, DT-70/10 AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 4.5 to 5.5 V AC test conditions Input pulse voltage level Input rise and fall times Input and output timing level Output load LC35256DM, DT-70 LC35256D, DM, DT-10 VIH = 2.4 V, VIL = 0.6 V 5 ns 1.5 V One TTL gate + 30 pF (Including jig capacitances.) One TTL gate + 100 pF (Including jig capacitances.) Read Cycle LC35256D, DM, DT Parameter Symbol min Read cycle time Address access time CE access time OE access time Output hold time CE output enable time OE output enable time CE output disable time OE output disable time tRC tAA tCA tOA tOH tCOE tOOE tCOD tOOD 10 10 5 30 25 70 70 70 35 10 10 5 30 25 -70* max min 100 100 100 50 -10 max ns ns ns ns ns ns ns ns ns Unit Note *: Specification values for the LC35256DM and LC35256DT. Write Cycle LC35256D, DM, DT Parameter Symbol min Write cycle time Address setup time Write pulse width CE setup time Write recovery time CE write recovery time Data setup time Data hold time CE data hold time WE output enable time WE output disable time tWC tAS tWP tCW tWR tWR1 tDS tDH tDH1 tWOE tWOD 70 0 55 60 0 0 35 0 0 5 30 -70* max min 100 0 60 70 0 0 40 0 0 5 30 -10 max ns ns ns ns ns ns ns ns ns ns ns Unit Note *: Specification values for the LC35256DM and LC35256DT. [3-V Operation] DC Allowable Operating Ranges at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V Parameter Supply voltage Input voltages Symbol VCC VIH VIL Conditions Ratings min 2.7 VCC – 0.2 –0.3* typ 3.0 max 3.6 VCC + 0.3 +0.2 Unit V V V Note *: –2.0 V for pulse widths of up to 30 ns. No. 5823-4/8 LC35256D-10, LC35256DM, DT-70/10 DC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V Parameter Input leakage current Output leakage current High-level output voltage Low-level output voltage Operating current drain VCC – 0.2 V/ 0.2 V inputs Symbol ILI ILO VOH VOL ICCA4 VIN = 0 to VCC VCE = VIH or VOE = VIH or VWE = VIL, VI/O = 0 to VCC IOH = –0.5 mA IOL = 1.0 mA min VCE = VIL, VIN = VIH or VIL, II/O = 0 mA, Duty 100% VCE ≥ VCC – 0.2 V, VIN = 0 to VCC LC35256DM, DT-70 7 3 1.5 Ta ≤ 25°C Ta ≤ 60°C Ta ≤ 85°C 0.01 0.8 4.0 cycle LC35256D, DM, DT-10 1 µs cycle Conditions Ratings min –1.0 –1.0 VCC – 0.2 0.2 10 5 2.5 typ* max +1.0 +1.0 Unit µA µA V V mA mA mA µA µA µA Standby mode current drain VCC – 0.2 V/ 0.2 V inputs ICCS1 Note *: Reference value at Ta = 25°C, VCC = 3 V. AC Electrical Characteristics at Ta = –40 to +85°C, VCC = 2.7 to 3.6 V AC test conditions Input pulse voltage level Input rise and fall times Input and output timing level Output load LC35256DM, DT-70 LC35256D, DM, DT-10 VIH = VCC – 0.2 V, VIL = 0.2 V 10 ns 1.5 V 30 pF (Including jig capacitances.) 100 pF (Including jig capacitances.) Read Cycle LC35256D, DM, DT Parameter Symbol min Read cycle time Address access time CE access time OE access time Output hold time CE output enable time OE output enable time CE output disable time OE output disable time tRC tAA tCA tOA tOH tCOE tOOE tCOD tOOD 20 20 10 60 50 200 200 200 100 20 20 10 120 100 -70* max min 500 500 500 250 -10 max ns ns ns ns ns ns ns ns ns Unit Note *: Specification values for the LC35256DM and LC35256DT. No. 5823-5/8 LC35256D-10, LC35256DM, DT-70/10 Write Cycle LC35256D, DM, DT Parameter Symbol min Write cycle time Address setup time Write pulse width CE setup time Write recovery time CE write recovery time Data setup time Data hold time CE data hold time WE output enable time WE output disable time tWC tAS tWP tCW tWR tWR1 tDS tDH tDH1 tWOE tWOD 200 0 140 150 0 0 130 0 0 10 60 -70* max min 500 0 200 250 0 0 180 0 0 10 120 -10 max ns ns ns ns ns ns ns ns ns ns ns Unit Note *: Specification values for the LC35256DM and LC35256DT. Timing Charts Read Cycle *1 *5 No. 5823-6/8 LC35256D-10, LC35256DM, DT-70/10 Write Cycle 1 (WE write) *6 *5 Write Cycle 2 (CE write) *6 *5 Notes: 1. Applications must set WE high during the read cycle. 2. External circuits in the application must not apply reverse phase signals to the DOUT pins when those pins are in the output state. 3. The time tWP is the period when CE and WE are both low. It is defined as the time from the fall of WE to the rise of CE or the rise of WE, whichever occurs first. 4. The time tCW is the period when CE and WE are both low. It is defined as the time from the fall of CE to the rise of CE or the rise of WE, whichever occurs first. 5. The data outputs (DOUT) go to the high-impedance state if any one of the following conditions hold: OE is high, CE is high, or WE is low. 6. OE must be held either high or low during the write cycle. 7. The DOUT pins have the same phase as the write cycle write data. No. 5823-7/8 LC35256D-10, LC35256DM, DT-70/10 Notes on Circuit Design Take the following operations into account when designing circuits that use these products to assure that none of the items in the maximum ratings are exceeded. • Supply voltage variations and fluctuations • Manufacturing variations in the electrical characteristics of the electrical components, including semiconductor devices, resistors, and capacitors. • Ambient temperature • Variations and fluctuations in the input and clock signals • Possible application of abnormal pulses Parameters listed in the allowable operating ranges must never exceed their stipulated ranges. If input pins to a CMOS IC are left open, through currents may occur in internal circuits to which intermediate potentials are input and result in incorrect circuit operation. Always verify that any unused pins are set up in appropriate states. Data Retention Characteristics at Ta = –40 to +85°C Parameter Data retention supply voltage Symbol VDR ICCDR tCDR tR VCE ≥ VCC – 0.2 V VCC = 3.0 V, VCE ≥ VCC – 0.2 V Ta ≤ 25°C Ta ≤ 60°C Ta ≤ 85°C 0 tRC*2 Conditions Ratings min 2.0 0.01 0.7 3.5 typ*1 max 5.5 Unit V µA µA µA ns ns Data retention current drain Chip enable setup time Chip enable hold time Notes: 1. Reference value at Ta = 25°C, VCC = 3 V. 2. tRC: Read cycle time Data Retention Waveforms Data retention mode Note *: VCCL 5-V operation: 4.5 V 3-V operation: 2.7 V s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5823-8/8