LC72121MA

Ordering number : ENA2009 CMOS IC LC72121MA Overview PLL Frequency Synthesizers for Electronic Tuning The LC72121MA are high input sensitivity (20mVrms at 130MHz) PLL frequency synthesizers for 3V systems. These ICs are serial data (CCB) compatible with the LC72131K/KMA, and feature the improved input sensitivity and lower spurious radiation (provided by a redesigned ground system) required in high-performance AM/FM tuners. Features • High-speed programmable divider • FMIN: 10 to 160MHz ·················· Pulse swallower technique (With built-in divide-by-2 prescaler) • AMIN: 2 to 40MHz ····················· Pulse swallower technique 0.5 to 10MHz ·················· Direct division technique • IF counter • IFIN: 0.4 to 15MHz ····················· For AM and FM IF counting • Reference frequency • One of 12 reference frequencies can be selected (using a 4.5 or 7.2MHz crystal element) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100kHz • Phase comparator • Supports dead zone control. • Built-in unlocked state detection circuit • Built-in deadlock clear circuit • An MOS transistor for an active low-pass filter is built in. • I/O ports • Output-only ports: 4 pins • I/O ports: 2 pins • Supports the output of a clock time base signal. • Serial data I/O • Support CCB format communication with the system controller. • Operating ranges • Supply voltage: 2.7 to 3.6V • Operating temperature: -40 to +85°C • Package • MFP24SJ • • CCB is a registered trademark of SANYO Semiconductor Co., Ltd. CCB is SANYO Semiconductor's original bus format. All bus addresses are managed by SANYO Semiconductor for this format. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. 30712HKPC 20120124-S00002 No.A2009-1/24 LC72121MA Specifications Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = VSSX = 0V Parameter Maximum supply voltage Maximum input voltage Symbol VDD max VIN1 max VIN2 max VIN3 max Maximum output voltage VO1 max VO2 max VO3 max Maximum output current IO1 max IO2 max Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD CE, CL, DI, AIN XIN, FMIN, AMIN, IFIN IO1, IO2 DO XOUT, PD BO1 to BO4, IO1, IO2, AOUT DO, AOUT BO1 to BO4, IO1, IO2 (Ta ≤ 85°C) Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +15 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +15 0 to 6.0 0 to 10 200 -40 to +85 -55 to +125 Unit V V V V V V V mA mA mW °C °C Note 1: Power pins VDD and VSS: Insert a capacitor with a capacitance of 2,000pF or higher between these pins when using the IC. Allowable Operating Ranges at Ta = -40 to +85°C, VSSd = VSSa = VSSX = 0V Parameter Supply voltage Input high-level voltage Symbol VDD VIH1 VIH2 Input low-level voltage Output voltage VIL VO1 VO2 Input frequency fIN1 fIN2 fIN3 fIN4 fIN5 Guaranteed crystal oscillator frequency Input amplitude VIN1 VIN2-1 VIN2-2 VIN3 VIN4 VIN5 VIN6 Data setup time Data hold time Clock low level time Clock high level time CE wait time CE setup time CE hold time Data latch change time Data output time tSU tHD tCL tCH tEL tES tEH tLC tDC tDH DO, CL DO, CE XIN FMIN FMIN AMIN AMIN IFIN IFIN DI, CL DI, CL CL CL CE, CL CE, CL CE, CL fIN1 f=10 to 130MHz f=130 to 160MHz fIN3(SNS=1) fIN4(SNS=0) fIN5(IFS=1) fIN5(IFS=0) Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Differs depending on the value of the pull-up resistor. Note 3 0.35 μs X’tal VDD CE, CL, DI IO1, IO2 CE, CL, DI, IO1, IO2 DO BO1 to BO4, IO1, IO2, AOUT XIN FMIN AMIN AMIN IFIN XIN, XOUT VIN1 VIN2 VIN3(SNS=1) VIN4(SNS=0) VIN5 Note 2 Pin Conditions Ratings min 2.7 0.7VDD 0.7VDD 0 0 0 1.0 10 2.0 0.5 0.4 4.0 200 20 40 40 40 40 70 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75 typ max 3.6 6.5 13 0.3VDD 6.5 13 8.0 160 40 10 15 8.0 800 800 800 800 800 800 800 Unit V V V V V V MHz MHz MHz MHz MHz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms μs μs μs μs μs μs μs μs No.A2009-2/24 LC72121MA Note 2: Recommended crystal oscillator CI values: CI ≤ 120Ω (For a 4.5MHz crystal) CI ≤ 70Ω (For a 7.2MHz crystal) The characteristics of the oscillation circuit depends on the printed circuit board, circuit constants, and other factors. Therefore we recommend consulting with the anufacturer of the crystal for evaluation and reliability. Note 3: Refer to "Serial Data Timing". Electrical Characteristics in the Allowable Operating Ranges Parameter Internal feedback resistance Symbol Rf1 Rf2 Rf3 Rf4 Internal pull-down resistance Rpd1 Rpd2 Hysteresis Output high-level voltage Output low-level voltage VHIS VOH VOL1 VOL2 VOL3 VOL4 Input high-level current IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 Input low-level current IIL1 IIL2 IIL3 IIL4 IIL5 IIL6 Output off leakage current IOFF1 IOFF2 High-level 3-state off leakage current Low-level 3-state off leakage current Input capacitance Supply current CIN IDD1 FMIN VDD X’tal=7.2MHz fIN2=130MHz IDD2 VDD VIN2=20mVrms PLL block stopped (PLL INHIBIT mode) Crystal oscillator operating (crystal frequency: 7.2 MHz) IDD3 VDD PLL block stopped. Crystal oscillator stopped. 10 μA 0.3 mA 2.5 6 mA 6 pF IOFFL PD VO=0V 0.01 200 nA IOFFH XIN FMIN AMIN IFIN FMIN AMIN CE, CL, DI PD PD BO1 to BO4, IO1, IO2 IO=-1mA IO=1mA IO=1mA IO=8mA DO IO=1mA IO=5mA AOUT CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN CE, CL, DI IO1, IO2 XIN FMIN, AMIN IFIN AIN BO1 to BO4, AOUT, IO1, IO2 DO PD IO=1mA, AIN=1.3V VI=6.5V VI=13V VI=VDD VI=VDD VI=VDD VI=6.5V VI=0V VI=0V VI=0V VI=0V VI=0V VI=0V VO=13V VO=6.5V VO=VDD 0.01 1.3 2.5 5.0 1.3 2.5 5.0 VDD-1.0 1.0 0.2 1.6 0.2 1.0 0.5 5.0 5.0 8 15 30 200 5.0 5.0 8 15 30 200 5.0 5.0 200 100 100 Pin Conditions Ratings min typ 1.0 500 500 250 200 200 0.1VDD 400 400 max Unit MΩ kΩ kΩ kΩ kΩ kΩ V V V V V V V V μA μA μA μA μA nA μA μA μA μA μA nA μA μA nA No.A2009-3/24 LC72121MA Package Dimensions unit : mm (typ) 3419 13.0 24 6.0 8.0 12 (1.0) 1.0 0.4 1.9 MAX 0.15 SANYO : MFP24SJ(300mil) Pin Assignment XOUT 0.1 (1.5) AOUT 0.45 VSSa AMIN FMIN VDD VSSd 24 23 22 21 20 19 18 17 16 15 14 13 LC72121MA 1 XIN 2 VSSX 3 CE 4 DI 5 CL 6 DO 7 BO1 8 BO2 9 BO3 10 BO4 11 IO1 12 NC Top view IFIN AIN IO2 NC PD No.A2009-4/24 LC72121MA Block Diagram VSSX XIN XOUT AIN AOUT VSSa AMIN 12bits PROGRAMMABLE DIVIDER REFERENCE DIVIDER PHASE DETECTOR CHARGE PUMP PD FMIN 1/2 SWALLOW COUNTER 1/16,1/17 4bits UNLOCK DETECTOR CE DI CL DO VDD VSSd POWER ON RESET CCB I/F DATA SHIFT REGISTER LATCH UNIVERSAL COUNTER IFIN BO1 BO2 BO3 BO4 IO1 IO2 No.A2009-5/24 LC72121MA Pin Descriptions Pin name Pin No. Type Function Equivalent circuit XIN XOUT 1 24 X’tal OSC • Crystal oscillator element connections (4.5 or 7.2 MHz) • FMIN is selected when DVS in the serial data is set to 1. • Input frequency: 10 to 160MHz FMIN 17 Local oscillator signal input • The signal is passed through an internal divide-by-two prescaler and then input to the swallow counter. • The divisor can be set to a value in the range 272 to 65535. Since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value. • AMIN is selected when DVS in the serial data is set to 0. • When SNS in the serial data is set to 1: • Input frequency: 2 to 40MHz • The signal is input to the swallow counter directly. AMIN 16 Local oscillator signal input • The divisor can be set to a value in the range 272 to 65535. The set value becomes the actual divisor. • When SNS in the serial data is set to 0: • Input frequency: 0.5 to 10MHz • The signal is input to a 12-bit programmable divider directly. • The divisor can be set to a value in the range 4 to 4095. The set value becomes the actual divisor. CE DI CL 3 4 5 Chip enable Input data Clock • This pin must be set high to enable serial data input (DI) or serial data output (DO). • Input for serial data transferred from the controller • Clock used for data synchronization for serial data input (DI) and serial data output (DO). • Output for serial data transmitted to the controller. The content of the data transmitted is determined by DOC0 through DOC2. • LC72121MA power supply (VDD 2.7 to 3.6V) • The power on reset circuit operates when power is first applied. • Ground for the crystal oscillator circuit • Ground for the LC72121MA digital systems other than those that use VSSa or VSSX. • Output-only ports • The output state is determined by BO1 through BO4 in the serial data. When the data value is 0: The output state will be the open circuit Output port state. When the data value is 1: The output state will be a low level. • A time base signal (8Hz) is output from BO1 when TBC in the serial data is set to 1. • Shared function I/O ports • The pin function is determined by IOC1 and IOC2 in the serial data. When the data value 0: Input port When the data value 1: Output port • When specified to function as an input port: The input pin state is reported to the controller through the DO pin. IO1 IO2 11 14 I/O port When the input state is low: The data will be 0: When the input state is high: The data will be 1: • When specified to function as an output port: The output state is determined by IO1 and IO2 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level. • These pins are set to input mode after a power on reset. S S S DO 6 Output data VDD VSSX VSSd 18 2 15 Power supply Ground Ground - BO1 BO2 BO3 BO4 7 8 9 10 Continued on next page. No.A2009-6/24 LC72121MA Continued from preceding page. Pin name Pin No. Type • PLL charge pump output PD 19 Charge pump output A high level is output when the frequency of the local oscillator signal divided by N is higher than the reference frequency, and a low level is output when that frequency is lower. This pin goes to the highimpedance state when the frequencies match. AIN AOUT 20 21 Low-pass filter amplifier transistor Ground • Connections for the MOS transistor used for the PLL active low-pass filter. Function Equivalent circuit VSSa 22 • Ground for the low-pass filter MOS transistor • The input frequency range is 0.4 to 15MHz IFIN 13 IF counter • The signal is passed directly to the IF counter. • The result is output, MSB first, through the DO pin. • Four measurement periods are supported: 4, 8, 32, and 64ms. 12 23 NC NC pin • No connection - No.A2009-7/24 LC72121MA Procedures for Input and Output of Serial Data This product uses the CCB (Computer Control Bus), which is Sanyo’s audio product serial bus format, for data input and output. This product adopts an 8-bit address CCB format. I/O mode Address B0 B1 B2 B3 A0 A1 A2 A3 • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. • Control data input (serial data input) mode [2] IN2(92) 1 0 0 1 0 1 0 0 • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. • Data output (serial data output) mode [3] OUT(A2) 0 1 0 1 0 1 0 0 • The number of bits output is equal to the number of clock cycles. • See the “DO output Data (serial data output)” section for details on the content of the output data. Function • Control data input (serial data input) mode [1] IN1(82) 0 0 0 1 0 1 0 0 I/O mode determined CE (1) CL DI B0 B1 B2 B3 A0 A1 A2 A3 First data IN1/2 (1) DO (2) First data OUT (1) CL:Normally high (2) CL:Normally low First data OUT ∼∼∼∼∼∼∼ ∼∼∼∼∼∼∼ No.A2009-8/24 (2) ∼ ∼ ∼ ∼ [2] IN2 mode [1] IN1 mode DI 1 0 DI (4) IO-C 0 0 IOC2 0 0 IO1 1 IO2 0 (5) O-PORT 1 BO2 P5 P6 P7 (1) P-CTR P8 P9 P10 P11 P12 P13 P14 P15 SNS DVS (3) IF-CTR CTE XS R0 (2) R-CTR R1 R2 R3 0 BO3 0 BO4 (13) Don’t care DNC DOC0 (6) DO-C DOC1 DOC2 (7) UNLOCK UL1 DZ0 DZ1 GT0 GT1 TBC DLC IFS TEST0 (12) TEST TEST1 TEST2 UL0 BO1 P4 P3 P2 P1 IOC1 P0 1 0 Address Address Structure of the DI Control Data (serial data input) First data IN2 First data IN1 1 0 0 LC72121MA (8) DZ-C (3) IF-CTR (9) TIME (10) PD-C (11) IFS No.A2009-9/24 LC72121MA Control Data No. Control block/data Function • Specifies the divisor for the programmable divider. This is a binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (* : don’t care) DVS 1 Programmable divider data (1) P0 to P15 DVS, SNS 0 0 SNS * 1 0 LSB P0 P0 P4 Set divisior (N) 272 to 65535 272 to 65535 4 to 4095 Actual divisior Twice the set value The set value The set value Related data * LSB : When P4 is the LSB, P0 to P3 are ignored. • These pins select the signal input to the programmable divider (FMIN or AMIN) and switch the input frequency range. (* : don’t care) DVS 1 0 0 SNS * 1 0 Input pin FMIN AMIN AMIN Frequency range accepted by the input pin 10 to 160MHz 2 to 40MHz 0.5 to 10MHz * See the “Structure of the Programmable Divider” section for details. • Reference frequency selection R3 0 0 0 0 0 0 0 0 Reference divider data (2) R0 to R3 XS 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency 100 kHz 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1 3 15 * PLL INHIBIT+X’tal OSC STOP * PLL INHIBIT * PLL INHIBIT mode In this mode, the programmable divider and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are pulled down to ground, and the charge pump output goes to the highimpedance state. • Crystal oscillator element selection data XS = 0: 4.5MHz XS = 1: 7.2MHz Note that 7.2 MHz is selected after a power on reset. • IF counter measurement start command data CTE = 1 : Starts the counter IF counter control data (3) CTE GT0, GT1 CTE = 0 : Resets the counter • IF counter measurement time. GT1 0 0 1 1 GT0 0 1 0 1 Measurement time 4 ms 8 32 64 Wait time 3 to 4 ms 3 to 4 7 to 8 7 to 8 IFS * See the “Structure of the IF Counter” section for details. (4) I/O port setup data IOC1,IOC2 Output port data (5) BO1 to BO4 IO1,IO2 • Specifies input or output for the shared function I/O pins (IO1 and IO2). Data = 0: Input port Data = 1: Output port • Determines the output state of the BO1 through BO4, IO1, and IO2 output ports. Data = 0: Open Data = 1: Low level • The data is reset to 0, setting the pins to the open state, after a power on reset. IOC1 IOC2 Continued on next page. No.A2009-10/24 LC72121MA Continued from preceding page. No. Control block/data • Determines the DO pin output. DOC2 0 0 0 0 1 1 1 1 DOC1 0 0 1 1 0 0 1 1 DOC0 0 1 0 1 0 1 0 1 DO pin state Open Low when the PLL is unlocked end-UC *1 Open Open The IO1 pin state *2 The IO2 pin state *2 Open Function Related data The open state is selected after a power on reset. *1. end-UC: IF counter measurement end check DO pin control data DO pin (6) DOC0 DOC1 DOC2 (1) Count start (2) Count end UL0, UL1 CTE ∼ ∼ ∼ ∼ CE:high IOC1 IOC2 (1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin automatically goes to the open state. (2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing applications to test for the completion of the count period. (3)The DO pin is set to the open state by performing a serial data input or output operation (when the CE pin is set high). *2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port. Note) During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data output period (the period that CE is high in OUT mode) the DO pin state reflects the internal DO serial data in synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2). • Selects the width of the phase error (φE) detected for PLL lock state discrimination. The state is taken to be unlocked if a phase error in excess of the detection width occurs. Unlocked state (7) detection data UL0, UL1 UL1 0 0 1 1 UL0 0 1 0 1 φE detection width Stop 0 ±0.55μs ±1.11μs Detection output Open φE is output directly φE is extended by 1 to 2ms ↑ DOC0 DOC1 DOC2 * When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0. • Controls the phase comparator dead zone Phase comparator (8) control data DZ0, DZ1 DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Dead zone width: DZA < DZB < DZC < DZD (9) Clock time base TBC • Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the BO1 pin. (The BO1 data will be ignored.) • Forcibly controls the charge pump output. Charge pump (10) control data DLC DLC 0 1 Charge pump output Normal operation Forced Low BO1 * If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped, applications can get out of the deadlocked state by setting the charge pump output to low and setting Vtune to VCC. (Deadlock clear circuit) • This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in which the sensitivity is reduced by about 10 to 30mV rms. * See the “IF Counter Operation” section for details. • Test data TEST0 TEST1 TEST2 All these bits are set to 0 after a power on reset. • This bit must be set to 0. All these bits must be set to 0. IF counter control (11) data IFS (12) Test data TEST0 to 2 (13) DNC No.A2009-11/24 LC72121MA Structure of the DO Output Data (serial data output) [3] OUT mode Address DI 0 1 0 1 0 1 0 0 Fist data OUT C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 UL C9 C8 C7 C6 C5 C4 C3 C2 C1 (1) IN-PORT (2) UNLOCK (3) IF-CTR *: Data with the value 0 Control Data Functions No. Control block/data I/O port data (1) I2, I1 PLL unlocked state (2) data UL IF counter (3) binary counter C19 to C0 Function • Data latched from the I/O port IO1 or IO2 pin states. • These bits reflect the pin states regardless of the I/O port mode (input or output). The data is latched at the point the circuit enters data output mode (OUT mode). I1 ← The IO1 pin state I2 ← The IO2 pin state High : 1 Low : 0 UL0 UL1 CTE GT0 GT1 IOC1 IOC2 Related data • Indicates the state of the unlocked state detection circuit. UL ← 0: When the PLL is unlocked. UL ← 1: When the PLL is locked or in the detection disabled mode. • Indicates the value of the IF counter (20-bit binary counter). C19 ← MSB of the binary counter C0 ← LSB of the binary counter C0 No.A2009-12/24 I2 I1 DO * LC72121MA 1.Serial Data Input (IN1/IN2) tSU, tHD, tES, tEH, ≥ 0.75μs tLC < 0.75μs (1) CL: Normally high tEL CE CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC tES tEH (2) CL: Normally low tEL CE CL tSU DI Internal data B0 tHD B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3 tLC tES tEH 2.Serial Data Output (Out) tSU, tHD, tEL, tES, tEH, ≥ 0.75μs tDC, tDH < 0.35μs (1) CL: Normally high tEL tES tEH CE CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC I2 DO tDC I1 tDH UL C3 CE C1 C0 (2) CL: Normally low tEL CE CL tSU DI DO B0 tHD B1 B2 B3 A0 A1 A2 A3 tDC I2 tDC I1 UL C3 C2 C1 tDH C0 tES tEH Note: The data conversion times (tDC and tDH) depend on the value of the pull-up resistor and the printed circuit board capacitance since the DO pin is an n-channel open-drain circuit. No.A2009-13/24 LC72121MA Serial Data Timing CE tCH CL VIH DI VIL DO tSU tHD VIL VIH VIL VIH tCL VIL VIH VIL VIH VIH tEH VIL tEL tES tDC tDC tDH Internal data latch tLC Old New When CL is Stopped at the Low Level CE tCL CL VIH VIL VIH DI VIL DO tSU tHD VIL VIH tCH VIH VIH VIL VIH tEH VIL tEL tES tDC tDH Internal data latch tLC Old New When CL is Stopped at the High Level No.A2009-14/24 LC72121MA Structure of the Programmable Divider 4bits FMIN 1/2 (A) Swallow counter (B) AMIN fvco/N PD fref DVS SNS fvco = fref × N φE Programmable divider 12bits (C) DVS (A) (B) (C) 1 0 0 SNS * 1 0 Input pin FMIN AMIN AMIN Set divisor 272 to 65535 272 to 65535 4 to 4095 Actual divisor Twice the set value The set value The set value Input frequency range 10 to 160MHz 2 to 40MHz 0.5 to 10MHz *: Don’t care Sample Programmable Divider Divisor Calculations (1) For FM with a step size of 50kHz (DVS = 1, SNS = *: FMIN selected) FM RF = 90.0MHz (IF +10.7MHz) FM VCO = 100.7MHz PLL fref = 25kHz (R0 to R1 = 1, R2 to R3 = 0) 100.7MHz (FM VCO) ÷ 25kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) = 2014 → 07DE (hexadecimal) E 0 P0 1 P1 1 P2 1 P3 1 P4 0 P5 D 1 P6 1 P7 1 P8 1 P9 7 1 P10 0 P11 0 P12 0 P13 0 0 P14 0 P15 * SNS 1 DVS CTE XS 1 R0 1 R1 0 R2 0 R2 0 R2 0 R3 1 R3 1 R3 (2) For SW with a step size of 5kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected) SW RF = 21.75 MHz (IF +450kHz) SW VCO = 22.20MHz PLL fref = 5kHz (R0 = R2 = 0, R1 = R3 = 1) 22.2MHz (SW VCO) ÷ 5kHz (fref) = 4440 → 1158 (hexadecimal) 8 0 P0 0 P1 0 P2 1 P3 1 P4 0 P5 5 1 P6 0 P7 1 P8 0 P9 1 0 P10 0 P11 1 P12 0 P13 1 0 P14 0 P15 1 SNS 0 DVS CTE XS 0 R0 1 CTE XS R0 1 R1 0 R1 (3) For MW with a step size of 9kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected) MW RF = 1008kHz (IF +450kHz) WM VCO = 1458kHz PLL fref =9kHz (R0 = R3 = 1, R1 = R2 = 0) 1458 (MW VCO) ÷ 9kHz (fref) = 162 → 0A2 (hexadecimal) 2 * P0 * P1 * P2 * P3 0 P4 1 P5 0 P6 0 P7 0 P8 1 P9 A 0 P10 1 P11 0 P12 0 P13 0 0 P14 0 P15 0 SNS 0 DVS No.A2009-15/24 LC72121MA Structure of the IF Counter The LC72121MA IF counter is a 20-bit binary counter, and takes the IF signal from the IFIN pin as its input. The result of the count can be read out serially, MSB first, from the DO pin. IF counter (20-bits binary counter) IFIN (Fc) L S B 0 to 3 (GT) CTE GT0 GT1 C = Fc × GT M S B 4 to 7 8 to 11 12 to 15 16 to 19 DO pin (C) 4/8/32/64 ms GT1 0 0 1 1 GT0 0 1 0 1 Measurement time Measurement time (GT) 4 ms 8 32 64 Wait time (tWU) 3 to 4 ms 3 to 4 7 to 8 7 to 8 The IF frequency (Fc) is measured by determining how many pulses were input to the IF counter in the stipulated measurement time, GT. C Fc = GT (C=Fc × GT) C: Counted value (the number of pulses) IF Counter Frequency Measurement Examples (1) When the measurement time (GT) is 32ms and the counted value (C) is 53980 (hexadecimal) or 342,400 (decimal). IF frequency (Fc) = 342400 ÷ 32ms = 10.7MHz 5 0 C19 UL I2 I1 1 C18 0 C17 1 C16 0 C15 0 C14 3 1 C13 1 C12 1 C11 0 C10 9 0 C9 1 C8 1 C7 0 C6 8 0 C5 0 C4 0 C3 0 C2 0 0 C1 0 0 C5 1 C4 0 C3 0 C2 0 C1 0 C0 No.A2009-16/24 0 C0 (2) When the measurement time (GT) is 8ms and the counted value (C) is E10 (hexadecimal) or 3600 (decimal). IF frequency (FC) = 3600 ÷ 8ms = 450kHz 0 0 C19 UL I2 I1 0 C18 0 C17 0 C16 0 C15 0 C14 0 0 C13 0 C12 1 C11 1 C10 E 1 C9 0 C8 0 C7 0 C6 1 LC72121MA IF Counter Operation CE Frequency measurement time Wait time IFIN Count start Count end (end-UC) Data with CTE 1 Measurement time GT Applications must first, before starting an IF count operation reset the IF counter by setting CTE in the serial data to 0. The IF counter operation is started setting CTE in the serial data from 0 to 1. Although the serial data is latched by dropping the CE pin from high to low, the IF signal input to the IFIN pin must be provided within the wait time from the point CE goes low. Next, the readout of the IF counter after measurement is complete must be performed while CTE is still 1, since the counter will be reset if CTE is set to 0. Note: If IF counting is used, applications must determine whether or not the IF IC SD (station detect) signal is present in the microcontroller software, and perform the IF count only if that signal is asserted. This is because autosearch techniques that use IF counting only are subject to incorrect stopping at points where there is no station due to IF buffer leakage. Note that the LC72121MA input sensitivity can be controlled with the IFS bit in the serial data. Reduced sensitivity mode (IFS = 0) must be selected when this IC is used in conjunction with an IF IC that does not provide an SD output and auto-search is implemented using only IF counting. IFIN Minimum Sensitivity Standard Input frequency : f [MHz] IFS data 1 (Normal mode) 0 (Degraded sensitivity mode) 0.4 ≤ f < 0.5 40mVrms (0.1 to 3mVrms) 70mVrms(5 to 10mVrms) 0.5 ≤ f < 8 40mVrms 70mVrms 8 ≤ f ≤ 15 40mVrms(1 to 15mVrms) 70mVrms(30 to 40mVrms) Note: Values in parentheses are actual performance values that are provided for reference purposes. No.A2009-17/24 LC72121MA Unlocked State Detection 1. Unlocked state detection timing Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However, applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N) before checking the locked/unlocked state. CE Data latch VCO/N Ncounter fref φError (Unlock) Do not change the divisor N in the first period. * After changing the value of the divisor, the φ error signal will be output following the second period of the fref signal. ▼ Old data New data Old divisor N New divisor N Figure 1 Unlocked State Detection Timing For example, if fref is 1kHz (a period of 1ms) applications must wait at least 2 ms after the divisor N is changed before performing a locked/unlocked check. Unlocked state detection circuit Unlock ÷R fref VCO/N Preset Phase comparator φError VCO ÷N L.P.F Data latch Figure 2 Circuit Structure No.A2009-18/24 LC72121MA 2. Combining with Software Data input CE Data output (1) Data output (2) Divisor N VCO frequency Old data New data φError Unlocked state output in the serial data Unlocked detection pin output Locked Unlocked Locked Figure 3 Combining with Software 3. Outputting the unlocked state data in the serial data At the point of data output 1 in figure 3, the unlocked state data will indicate the unlocked state, since the VCO frequency is not stable (locked) yet. In cases such as this, the application should wait at least one whole period and then check again whether or not the frequency has stabilized with the data output 2 operation in the figure. Applications can implement even more reliable recognition of the locked state by performing several more checks of the state and requiring that the locked state be detected sequentially. Divisor N changed (data input) Wait at least 2 reference frequency periods. Data output (1) Valid output data is acquired by using an interval of at least one reference frequency period. Data output (2) *: Even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. Locked state check * YES NO 4. Directly outputting the unlocked state to the DO pin Since the unlocked state (high level when locked, low when unlocked) is output from the DO pin, applications can check for the locked state by waiting at least two reference frequency periods after changing the divisor N. However, in this case also, even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. No.A2009-19/24 LC72121MA Clock Time Base Usage Notes When using the clock time base output function, the output pin (BO1) pull-up resistor must have a value of over 100kΩ. The use of a Schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. This is to prevent degradation of the VCO C/N characteristics when combining with a loop filter that uses the internal transistor provided to form a low-pass filter. Although the ground for the clock time base output pin (VSSd) and the ground for the transistor (VSSa) are isolated internally on the chip, applications must take care to avoid ground loops and minimize current fluctuations in the time base pin to prevent degradation of the low-pass filter characteristics. VDD LC72121MA BO1 Rt ≥ 100kΩ Time base output Microcontroller S Schmitt input VSSd PD VCC VSSd AOUT AIN Loop filter VSSa VCO Vt Other Items (1) Notes on the phase comparator dead zone DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone --0s -0s +0s ++0s When the charge pump is used with one of the ON/ON modes, correction pulses are generated from the charge pump even if the PLL is locked. As a result, it is easy for the loop to become unstable, and special care is required in application design. The following problems can occur if an ON/ON mode is used. (1) Sidebands may be created by reference frequency leakage. (2) Sidebands may be created by low-frequency leakage due to the correction pulse envelope. Although the loop is more stable when a dead zone is present (i.e. when an OFF/OFF mode is used), a dead zone makes it more difficult to achieve excellent C/N characteristics. On the other hand, while it is easy to achieve good C/N characteristics when there is no dead zone, achieving good loop stability is difficult. Accordingly, the DZA and DZB settings, in which there is no dead zone, can be effective in situations where a signal-to-noise ratio of 90 to 100dB or higher is required in FM reception, or where it is desirable to increase the pilot margin in AM stereo reception. However, if such a high signal-to-noise ratio is not required for FM reception, if an adequate pilot margin can be acquired in AM stereo reception, or if AM stereo is not required, then either DZC or DZD, in which there is a dead zone, should be chosen. No.A2009-20/24 LC72121MA Dead Zone As shown in figure 1, the phase comparator compares a reference frequency (fr) with fp. As shown in figure 2, the phase comparator's characteristics consist of an output voltage (V) that is proportional to the phase difference φ. However, due to internal circuit delay and other factors, an actual circuit has a region (the dead zone, B) where the circuit cannot actually compare the phases. To implement a receiver with a high S/N ratio, it is desirable that this region be as small as possible. However, it is often desirable to have the dead zone be slightly wider in popularly-priced models. This is because in certain cases, such as when there is a strong RF input, popularly-priced models can suffer from mixer to VCO RF leakage that modulates the VCO. When the dead zone is small, the circuit outputs signals to correct this modulation and this output further modulates the VCO. This further modulation may then generate beats and the RF signal. RF MIX Reference divider fr Phase fp LPF Detector VCO Leakage V (A) (B) φ(ns) Dead zone Programmable divider Figure 1 Figure 2 (2) Notes on the FMIN, AMIN, and IFIN pins Coupling capacitors should be placed as close to their pin as possible. A capacitance of about 100pF is desirable for these capacitors. In particular, if the IFIN pin coupling capacitor is not held under 1000pF, the time to reach the bias level may become excessive and incorrect counts may result due to the relationship with the wait time. (3) Notes on IF counting → Use the SD signal in conjunction with IF counting When counting the IF frequency, the microcontroller must determine the presence or absence of the IF IC SD (station detect) signal and turn on the IF counter buffer output and execute the IF count only if there is an SD signal. Autosearch techniques that only use the IF counter are subject to incorrect stopping at points where there is no station due to IF buffer leakage. (4) DO pin usage The DO pin can be used for IF counter count completion checking and as an unlock detection output in addition to its use in data output mode. It is also possible to have the DO pin reflect the state of an input pin to input that state to the microcontroller. (5) Power supply pins Capacitors must be inserted between the power supply VDD and VSS pins for noise exclusion. These capacitors must be placed as close as possible to the VDD and VSS pins. (6) VCO setup Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes to 0V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily force Vtune to VCC to prevent deadlock from occurring. (Deadlock clear circuit) No.A2009-21/24 LC72121MA (7) Front end connection example Since this product is designed with the relatively high resistance of 200kΩ for the pulldown (on) resistors built in to the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit. FMIN FM OSC OSC buffer out On resistance: 200kΩ AM OSC AMIN On resistance: 200kΩ FE PLL (8) PD pin Note that the charge pump output voltage is reduced when this IC, which is a 3-V system, is used to replace the LC72131K/KMA, which is a 5-V system. This means that since the loop gain is reduced, the loop filter constants, the lock time (SD wait time), and other related parameters must be reevaluated in the end product design. Pin States after a Power on Reset XIN VSSX CE DI XOUT NC VSSa AOUT LC72121MA CL Open Open Open Open Open Input port DO BO1 BO2 BO3 BO4 IO1 NC AIN PD VDD FMIN AMIN VSSd IO2 IFIN Input port No.A2009-22/24 LC72121MA Sample Applications Circuit XIN 1 VSSX 2 CE DI CL Unlock SD end-UC IFcount ST-indic DO CE 3 DI 4 CL 5 DO 6 BO1 7 BO2 8 BO3 9 BO4 10 IO1 11 NC 12 24 XOUT 23 NC μ-COM S S S 22 VSSa 21 AOUT 20 AIN VCC FMVCO LC72121MA 19 PD 18 VDD 17 FMIN 16 AMIN 15 VSSd 14 IO2 13 IFIN SD TUNER-System AM/FM-IF AMVCO IF-Request FM/AM MONO/ST ST-Indicate No.A2009-23/24 LC72121MA SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2012. Specifications and information herein are subject to change without notice. PS No.A2009-24/24