LC723461W

Ordering number : ENN*7275 CMOS IC LC723461W, 723462W Ultralow-Voltage ETR Controller with On-Chip LCD Driver Preliminary Overview The LC723461W and LC723462W are ultralow-voltage electronic tuning microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This IC includes an on-chip DC-DC converter that can easily create the power supply voltages needed for electronic tuning and contribute to reducing end product costs. This IC is optimal for portable audio equipment that must operate from a single battery. • • • switched for use as serial I/O ports) Can be switched for CMOS output/open-drain outputs. Serial I/O: One system (LC723462) PLL: Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz Input frequencies: FM band: 10 to 250 MHz AM band (high): 2 to 20 MHz AM band (low): 0.5 to 10 MHz Input sensitivity: FM band: 35 mVrms (10 mVrms at 130 MHz), 50 mVrms (130 to 250 MHz) AM band (high, low): 35 mVrms IF count: HCTR input pin: 0.4 to 12 MHz (HCTR can be switched to function as a general-purpose input port.) Continued on next page. • Function • Program memory (ROM): — 4096 × 16 bits (8K bytes) : LC723461 — 6144 × 16 bits (12K bytes): LC723462 • Data memory (RAM): — 256 × 4 bits: LC723461 — 512 × 4 bits: LC723462 • Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation • Stack: 8 levels • LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) • Interrupts: Two external interrupts Timer interrupts (1, 5, 10, and 50 ms) • A/D converter: Four input channels (8-bit chopper A/D converter. The reference voltage can be switched using the ADCHG instruction.) • Input ports: 8 ports (of which three can be switched for use as A/D converter input and one can be switched for use as IF counter input.) • Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are open-drain ports) • I/O ports: 19 ports (of which 8 can be switched for use as LCD ports and as mask options, of which 3 can be • Package Dimensions unit: mm 3190A-SQFP64 [LC723461W, 723462W] 0.5 12.0 10.0 48 49 33 32 64 1 (0.5) (1.25) (1.5) 17 16 0.18 0.15 1.7max 0.1 10.0 12.0 SANYO: SQFP64 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 12503RM (OT) No. 7275-1/13 LC723461W, 723462W Continued from preceding page. • External reset input: During CPU and PLL operations, instruction execution is started from location 0. • Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. • Halt mode: The controller-operating clock is stopped. • Backup mode: The crystal oscillator is stopped. • Static power-on function: Backup state is cleared with the PF port • Beep tone: 1.5 and 3.1 kHz • Built-in DC-DC converter: For LCD and A/D converter use (3 V) Pin Assignment • • • • • Can also be used for TU + B creation by using a secondary coil. (The DC-DC converter voltage step-up operation can be stopped with the DCDCC instruction.) Built-in remaining battery life verification function: Converts the VDD pin level through AD converter. Memory retention voltage: 0.5 V or higher Dedicated memory power supply: The RAM retention time has been increased by the provision of a dedicated memory power supply. Package: SQFP-64 (0.5-mm pitch) VDD power supply: 0.9 to 1.8 V XOUT PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2 IN T1/P D 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 4 5 6 7 8 9 10 11 12 13 14 15 XIN TEST1 EO VSS AM IN FMIN VDD HCTR /PM0 BRES COMC COM1 COM2 COM3 COM4 S1 S2 I I 46 45 44 43 42 O LC723461W/3462W SQFP-64 I/O 41 40 39 38 37 36 35 I/O I I/O I/O 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 INT0/PD0 DAC/PD1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 SI1/PK3 SI0/PK2 SCK1/PK1 VREF VSS VDDRAM VDC3 VDC1 S20/PG3 S19/PG2 I/O O S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13/PH 0 S14/PH 1 S15/PH 2 S16/PH 3 S17/PG0 S18/PG1 *: The VDD pin can also function as ADI2 A/D converter input. No. 7275-2/13 LC723461W, 723462W Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol VDD1 max Maximum supply voltage VDD2 max VDD3 max Input voltage VIN1 VIN2 VOUT1 Output voltage VOUT2 VOUT3 VOUT4 IOUT1 IOUT2 Output current IOUT3 IOUT4 IOUT5 Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg VDD VDDRAM VDC3 FMIN, AMIN PA, PC, PD, PF, PK, PG, PH, BRES PE PB, PC, PD, PG, PH VDC1, EO COM1 to COM4, S1 to S20 PC, PD, PG, PH, EO PB PE S1 to S20 COM1 to COM4 Ta = –10 to +60°C Conditions Ratings –0.3 to +3.0 –0.3 to +4.0 –0.3 to +4.0 –0.3 to VDD1 +0.3 –0.3 to VDD1 +0.3 –0.3 to +7 –0.3 to VDD1 +0.3 –0.3 to VDD4 +0.3 –0.3 to VDD4 +0.3 0 to 3 0 to 1 0 to 2 300 3 100 –10 to +60 –45 to +125 Unit V V V V V V V V V mA mA mA µA mA mW °C °C Allowable Operating Ranges at Ta = –10 to +60°C, VDD = 0.9 to 1.8 V Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VDD4 VREF input voltage VREF1 VIH1 Input high-level voltage VIH2 VIH3 VIH4 VIL1 Input low-level voltage VIL2 VIL3 VIL4 VIN1 Input amplitude VIN2 VIN3 VIN4 Input voltage range VIN4 FIN1 FIN2 Input frequency FIN3 FIN4 FIN5 FIN6 Note: VDD3 R = 240 kΩ VREF When 0.66 V DZD2.0X Conditions Voltage applied to the VDD pin Voltage applied to the VDDRAM pin Voltage applied to the VDC3 pin (See note.) Memory retention voltage The voltage input to the VREF pin (See note.) Ports PC, PD, PG, PH, and PK Port PA Port PF Port BRES Ports PC, PD, PG, PH, and PK Port PA Port PF Port BRES XIN FMIN, AMIN: VDD1 = 0.9 to 1.8 V FMIN: VDD1 = 0.9 to 1.8 V ADI0, ADI1, VDD, ADI3 ADI0, ADI1, ADI3, VDD1 XIN: CI ≤ 35 kΩ FMIN: VIN2, VDD1 = 0.9 to 1.8 V FMIN: VIN3, VDD1 = 0.9 to 1.8 V AMIN(L): VIN2, VDD1 = 0.9 to 1.8 V AMIN(H): VIN2, VDD1 = 0.9 to 1.8 V HCTR: VIN4, VDD1 = 0.9 to 1.8 V 0.7 VDD1 0.8 VDD1 0.8 VDD1 0.6 VDD1 0 0 0 0 0.5 0.035 0.05 0.035 0 70 10 130 2 0.5 0.4 75 0.5 0.66 VDD1 VDD1 VDD1 VDD1 0.3 VDD1 0.2 VDD1 0.2 VDD1 0.2 VDD1 0.6 0.35 0.35 0.35 VDD3 80 130 250 20 10 12 V V V V V V V V V Vrms Vrms Vrms Vrms V kHz MHz MHz MHz MHz MHz Ratings min 0.9 2.7 typ 1.3 3.0 2.7 max 1.8 3.3 V Unit No. 7275-3/13 LC723461W, 723462W Electrical Characteristics within allowable operating conditions Parameter Symbol IIH1 IIH2 Input high-level current IIH3 IIH4 IIL1 IIL2 Input low-level current IIL3 IIL4 Input floating voltage VIF RPD1 Pull-down resistor values Hysteresis RPD2 VH VOH1 VOH2 VOH3 Output high-level voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 VOL4 Output low-level voltage VOL5 VOL6 VOL7 VOL8 Output off leakage current IOFF1 IOFF2 XOUT: IO = 200 µA S1 to S20: IO = 20 µA COM1, COM2, COM3, COM4: IO = 100 µA VDC1: IO = 1 mA PB: IO = –50 µA PC, PD, PG, PH: IO = –1 mA EO: IO = –500 µA XOUT: IO = –200 µA S1 to S20: IO = –20 µA COM1, COM2, COM3, COM4: IO = –100 µA PE: IO = 2 mA VDC1: IO = 1 mA Ports PB, PC, PD, PG and EO Port PE When the reference voltage is 2.7 V: ADI0, ADI1, VDD1, ADI3. Ta = 25°C A/D converter error When the reference voltage is 2.0 V: ADI0, ADI1, VDD1, ADI3. Ta = 25°C Note: Linearity is maintained in the converted data. IDD1 Current drain IDD3 IDD4 VDC3 current IDC31 VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25°C VDD1 = 1.3 V: In HALT mode, Ta = 25°C *1 VDD1 = 1.8 V, with the oscillator stopped, Ta = 25°C *2 Vdd3 = 2.7 V: Halt mode, Ta = 25°C –3 –100 –1 Conditions XIN: VDD1 = 1.3 V FMIN, AMIN, HCTR: VDD1 = 1.3 V Port PF: VDD1 = 1.3 V PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = 1.3 V XIN: VDD1 = VSS FMIN, AMIN, HCTR: VDD1 = VSS Port PF: VDD1 = VSS PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = VSS PA (with pull-down resistors) PA (with pull-down resistors), VDD1 = 1.3 V TEST1 (with pull-down resistor), VDD1 = 1.3 V BRES PB: IO = 1 mA PC, PD, PG and PH: IO = 1 mA EO: IO = 500 µA 0.1 VDD1 VDD1 – 0.7 VDD VDD1 – 0.3 VDD1 VDD3 – 0.3 VDD3 VDD1 – 0.3 VDD1 VDD3 –1 VDD3 –1 VDD3 –1 0.3 VDD1 0.7 VDD1 0.3 VDD1 0.3 VDD3 0.3 VDD1 VDD3 –2 VDD3 –2 0.6 VDD1 1 +3 +100 +1 75 100 10 0.2 VDD1 VDD1 – 0.3 VDD –3 –8 3 8 Ratings min typ max 3 20 4 3 –3 –20 –4 –3 0.05 VDD1 200 Unit µA µA µA µA µA µA µA µA V kΩ kΩ V V V V V V V V V V V V V V V V µA nA LSB –1 2 0.1 1 100 +1 LSB mA mA µA µA Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms. No. 7275-4/13 LC723461W, 723462W *1. Halt and PLL STOP mode current test circuit 7 pF 75 kHz XOUT XIN 7 pF PA, PF VDC3 VSS FMIN AMIN HCTR TEST1 COMC VSS FMIN AMIN HCTR TEST1 7 pF VDC3 COMC 3V VDD RES A *2. Backup mode current test circuit 7 pF 75 kHz XOUT XIN VDD RES A With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter halt mode by software command. The state where CPU operation is stopped with the crystal oscillator unstopped. With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter backup mode by software command. The state where the crystal oscillator is stopped. No. 7275-5/13 LC723461W, 723462W Block Diagram XIN XOUT FMIN AMIN 1/2 1/8 DIVIDER SYSTEM CLOCK GENERATOR 1/2 1/16,1/17 REFERENCE DIVIDER PHASE DETECTOR EO PROGRAMMBLE DIVIDER VSS VDC3 VADJ VDC1 HCTR Clock Control PLL DATA LATCH PLL CONTROL LCDA/B S1 SEG 4 LA 7 UNIVERSAL COUNTER (20bits) LCPA/B 1/2 LCD 80 PORT DRIVER RES COMC * P-ON RESET RAM 256×4bits (LC723461) 512×4bits (LC723462) S12 S13/PH0 S14/PH1 S15/PH2 S16/PH3 S17/PG0 S18/PG1 S19/PG2 S20/PG3 TEST1 ADDRESS DECODER BANK DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER / / PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT0/PD0 INT1/PD1 PD2 PD3 SCK1/PK1 SO1/PK2 SI1/PK3 * BUS DRIVER DATA LATCH BUS DRIVER / ROM 4k×16bits (LC723461) 6K×16bits (LC723462) BUS CONTROL INSTRUCTION DECODER SKIP JMP CAL RETURN INTERRUPT RESET BANK CF ADDRESS DECODER DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER / / / 14 ADDRESS COUNTER 14 STACK BEEP TONE DATA LATCH BUS DRIVER / PE0/BEEP MPX MPX PE1/DAC LATCH A ALU LATCH B TIMER 0 JUDGE DAC VDD MPX MPX (6bits) SIO DATA LATCH BUS DRIVER / DATA BUS PF0/ADI0 PF1/ADI1 PF2/ADI3 No. 7275-6/13 LC723461W, 723462W Pin Functions Pin No. Pin I/O Function I/O circuit 64 1 XIN XOUT I O 75 kHz oscillator connections 63 TEST1 I IC testing. This pin must be connected to ground. — 5 4 3 2 PA0 PA1 PA2 PA3 I Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction. This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset. Input with built-in pull-down resistor Unbalanced CMOS push-pull 9 8 7 6 PB0 PB1 PB2 PB3 O Unbalanced CMOS outputs. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. 13 12 11 18 17 16 15 14 PC0 PC1 PC2 PC3 INT1/PD0 INT0/PD1 PD2 PD3 I/O General-purpose I/O ports. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) In backup mode they go to the input disabled high-impedance state. After a reset, they switch to the general-purpose input port function. CMOS push-pull/ N-ch open-drain 19 18 BEEP/PE0 DAC/PE1 O General-purpose output ports. Note that PE0 has a shared function as the BEEP output, and that PE1 has a shared function as a D/A converter output port. Since these ports are open drain ports, a resistor must be inserted between each port and VDD. At reset, they are set to the general-purpose output port function .The BEEP instruction is used to switch the BEEP/PE0 port between the general-purpose output port and the BEEP output functions. A BEEP instruction with b2 = 0 will set the BEEP/PE0 port to function as a general-purpose output port. If b2 is set to 1, the instruction will select the BEEP output function. Bits b0 and b1 switch the frequency of the BEEP output. This IC supports two BEEP frequencies. *: When the PE0 port is set to function as the BEEP output, executing an output instruction for PE0 will only change the value of the internal output latch; it will have no effect on the output. The DAC instruction is used to switch the DAC/PE1 port between the general-purpose output port and DAC output functions. These ports go to the high-impedance state in backup mode. That state is maintained until an output instruction, a BEEP instruction, or a DAC instruction is executed. N-ch open-drain 25 24 23 SCK1/PK1 SO1/PK2 SI1/PK3 I/O Shared function pins used as either general-purpose I/O ports or a serial I/O port. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. When used as general-purpose I/O ports, the I/O direction can be switched in single pin units with the IOS instruction. The IOS instruction is used to switch the function between the general-purpose I/O port and the serial I/O port function. In backup mode, these pins go to the input disabled high-impedance state. After a reset, the general-purpose input port function is selected. CMOS push-pull/ N-ch open-drain Continued on next page. No. 7275-7/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function General-purpose input and A/D converter input shared function ports. The IOS instruction is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 8-bit successive approximation type converter, and features a conversion time of 0.64 ms. Note that the full-scale A/D converter voltage (FFH) is VDC3/2.0 V. LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction is used for switching between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port function. • When used as segment output ports The segment output port is selected with the IOS instruction (Pwn = 8). b0 to b3 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The segment output port is selected with the IOS instruction (Pwn = 9). b0 to b3 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) • When used as general-purpose I/O ports The IOS instruction is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output CMOS push-pull I/O circuit CMOS input/analog input 22 21 20 PF0/ADI0 PF1/ADI1 PF2/ADI3 I 31 32 33 34 PG3/S20 PG2/S19 PG1/S18 PG0/S17 O 35 36 37 38 PH3/S16 PH2/S15 PH1/S14 PH0/S13 *2 Note that there is a mask option that allows these pins to be used as n-channel open drain ports. In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull LCD driver segment output pins. 39 to 50 A 1/4-duty 1/2-bias drive technique is used. S12 to S1 O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. 51 52 53 54 COM4 COM3 COM2 COM1 O LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. Continued on next page. No. 7275-8/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O System reset input. 56 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Function I/O circuit 28 VDDRAMVADJ I RAM backup power supply. Connected to the VDC3 voltage through a diode. Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception mode. Voltage stepped up by the DC-DC converter (3 V) May also be used to input an equivalent voltage. VDC3 reference voltage input. 30 VDC1 O 29 VDC3 I 26 VREF I When 0.7 V is input, the VDC3 voltage will be 3 V. The VDC3 sample-to-sample variations can be held to ±3% by attaching an external metal-film resistor and a zener diode. LCD driver intermediate potential output. 55 COMC O The COM waveform must be stabilized by attaching an external capacitor of about 0.1 µF. CMOS amplifier input FM VCO (local oscillator) input. 59 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. 60 AMIN I CW1 b1, b0 1 1 Input pins FMIN (L) Bandwidth 0.5 to 10 MHz (MW, LW) CMOS amplifier input The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. General-purpose input and universal counter input shared-function port. The IOS instruction is used to switch between the general-purpose input port and the universal counter input functions. • When performing frequency measurements, select the HCTR frequency measurement mode and the measurement time with the UCS instruction (b3 = 0, b2 = 0), and start the count with the UCC instruction. UCS b3, b2 0 0 1 57 HCTR I 0 1 0 Input pins HCTR — — Measurement time 1 ms 4 ms 8 ms 32 ms Measurement mode Frequency measurement CMOS amplifier input UCS b1, b0 0 0 1 1 0 1 0 1 The CNTEND flag is set when the count completes. Since this circuit operates as an AC amplifier in this mode, the input signal must be capacitor coupled. When used as a general-purpose input, the input data is acquired with the INR instruction. Input is disabled in backup mode, halt mode, during a reset, and in PLL stop mode. Note that after a reset, the universal counter input port function will be selected. Continued on next page. No. 7275-9/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit CMOS push-pull Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output,and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 62 EO O 61 27 58 VSS VSS VDD — Power supply pin. This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. Supports A/D converter. — Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction. No. 7275-10/13 LC723461W, 723462W LC723461W/723462W Series Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL Instruction group Mnemonic AD ADS Operand 1st r r r r M M M M r r r r M M M M r M M r M M 2nd M M M M I I I I M M M M I I I I M I I M I I Add M to r Function Operations function r ← (r) + (M) r ← (r) + (M), skip if carry r ← (r) + (M) + C r ← (r) + (M) + C skip if carry M ← (M) + I M ← (M) + I, skip if carry M ← (M) + I + C M ← (M) + I + C, skip if carry r ← (r) – (M) r ← (r) – (M), skip if borrow r ← (r) – (M) – b r ← (r) – (M) – b, skip if borrow M ← (M) – I M ← (M) – I, skip if borrow M ← (M) – I – b M ← (M) – I – b, skip if borrow (r) – (M), skip if zero (M) – I, skip if zero (M) – I, skip if not zero (r) – (M), skip if not borrow (M) – I, skip if not borrow (M) – I, skip if borrow Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 c 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 0 b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 9 8 7 6 5 4 3 2 r r r r I I I I r r r r I I I I r I I r I I 1 0 DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if M is greater than equal to I Skip if M is less than I Addition instructions AC ACS AI AIS AIC AICS SU SUS Subtraction instructions SB SBS SI SIS SIB SIBS Comparison instructions SEQ SEQI SNEI SGE SGEI SLEI Continued on next page. No. 7275-11/13 LC723461W, 723462W Continued from preceding page. Instruction group Mnemonic AND ANDI OR ORI EXL EXLI SHR LD Operand 1st r M r M r M r r M r M M1 M M M M r M r M2 I N N 2nd M I M I M I Function AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift r right with carry Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt Operations function r ← (r) AND (M) M ← (M) AND I r ← (r) OR (M) M ← (M) OR I r ← (r) XOR (M) M ← (M) XOR I carry (r) r ← (M) M ← (r) [DH, Rn] ← (M) M ← [DH, Rn] [DH, DL1] ← [DH, DL2] M←I if M (N) = all 1, then skip if M (N) = all 0, then skip PC ← ADDR PC ← ADDR Stack ← (PC) + 1 PC ← Stack PC ← Stack, BANK ← Stack, CARRY ← Stack (Status W-reg) N ← 1 (Status W-reg) N ← 0 Instruction format f 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 e 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 d 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 1 0 c 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 b 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 a 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r I r I r I 0 r r r r r DL2 I N N 1 0 Logic operation instructions DH DH DH DH DH DH 0 0 1 DL DL DL DL DL DL 1 1 DH DH DH DH DH DH DH DH DL DL DL DL DL1 DL DL DL Transfer instructions ST MVRD MVRS MVSR MVI Bit test instructions TMT TMF JMP CAL RT RTI SS Jump and subroutine call instructions ADDR ADDR ADDR (13 bits) ADDR (13 bits) 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 N N N N N r I2 0 1 1 1 0 1 0 0 1 0 I I I I I N 1 I Pn Pn Pn N N N N SWR SWR SRR SRR N M I1 I I I I I PWn I M M M P1n P1n P1n P1n N N N N Set status register Reset status register Test status register true Test status register false Test Unlock F/F Load M to PLL register 0 SWR 1 SWR SRR SRR 0 1 Status register instructions RS TST TSF TUL If (Status R-reg) N = all 1, 1 then skip If (Status R-reg) N = all 0, 1 then skip If Unlock F/F (N) = All 0, then skip PLL reg ← PLL data SIO reg ← I1, I2 UCCW1 ← I UCCW2 ← I BEEP reg ← I DZC reg ← I Timer reg ← I IOS reg PWn ← N DAC reg ← DAC data M ← (Pn) P1n ← M M ← (Pn) (Pn)N ← 1 (Pn)N ← 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 Hardware control instructions PLL SIO UCS UCC BEEP DZC TMS IOS DAC IN OUT DH 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 DL I1 0 0 1 0 1 Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register N Set port control word DA converter control Pn Pn Pn N N N N Input port data to M Output contents of M to port Input register/port data to M Set port1 bits Reset port1 bits PWn 0 1 DH DH DH 1 1 0 0 0 1 0 1 DL DL DL Pn Pn Pn Pn I/O instructions INR SPB RPB TPT TPF Test port1 bits, then skip if all bits If (Pn)N = all 1, then skip specified are true Test port1 bits, then skip if all bits If (Pn)N = all 0, then skip specified are false BANK ← I Bank switching instructions BANK I Select Bank 0 0 0 0 0 0 0 0 0 1 1 1 I Continued on next page. No. 7275-12/13 LC723461W, 723462W Continued from preceding page. Instruction group Mnemonic LCDA LCDB LCPA LCPB ADCHG DCDCC HALT CKSTP NOP Operand 1st M M M M I I I 2nd I I I I Function Output segment pattern to LCD digit direct Output segment pattern to LCD digit through LA AD converter reference voltage change DC/DC clock control Halt mode control Clock stop No operation Operations function LCD (DIGIT) ← M LCD (DIGIT) ← LA ← M Instruction format f 1 1 1 1 1 0 e 1 1 1 1 1 0 0 0 0 d 0 0 0 0 1 0 0 0 0 c 0 0 0 0 1 0 0 0 0 b 0 0 1 1 1 0 0 0 0 a 0 1 0 1 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 LCD instructions DH DH DH DH 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 DL DL DL DL 1 1 1 1 0 1 1 0 0 0 0 1 0 1 0 DIGIT DIGIT DIGIT DIGIT I I I Other instructions HALT reg ← I, then CPU clock stop Stop x’tal OSC No operation 0 0 0 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2003. Specifications and information herein are subject to change without notice. PS No. 7275-13/13