LC74411

Ordering number : EN*5519A CMOS LSI LC74411N, LC74411NE PIP Controller Preliminary Overview The LC74411N and LC74411NE are digital processing controllers for PIP (picture-in-picture) systems in TV sets and VCRs. These ICs incorporate three circuits, a multiplexed A/D converter, field memory, and a D/A converter, to implement the PIP digital processing block in a single chip. Package Dimensions unit: mm 3071-DIP64S [LC74411N] Features • Horizontal resolution: 450 pixels* • Single-chip implementation of the three circuits required in a PIP digital processing block: A/D converter, field memory, and D/A converter circuits • High image quality provided by vertical filtering • I2C bus adopted • Built-in PLL circuit (requires an external low-pass filter) • Supports NTSC and PAL, TV and VCR applications, and multi-format (NTSC and PAL) applications. • External control function • 8-bit D/A converter (PWM type): 6 pins • General-purpose ports: 8 pins • Sub-screen specifications • Display on/off, frame/no frame, frame color switching, wipe function • Display position - Specifiable as an 8-bit value for each of the horizontal and vertical directions. • Size Vertical reduction: 1/3, 1/4 Horizontal reduction: 1/3, 1/4 – The horizontal size can be adjusted by adjusting the PLL divisor – The display area vertical and horizontal positions can be varied independently. • Horizontal resolution (Y signal): about 190 dots • Quantization: 6 bits • Operating supply voltage LC74411NE : 5 V ±5% LC74411N : 5 V ±10% • Package LC74411NE : QFP64E LC74411N : DIP64S Note: Y R-Y B-Y D/A clock 11.6 MHz 2.9 MHz 2.9 MHz When the main screen synchronization PLL uses the standard value (PLL4 : 0 = 10110) SANYO: DIP64S unit: mm 3159-QFP64E [LC74411NE] SANYO: QIP64E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93196HA (OT) No. 5519-1/14 LC74411N, LC74411NE Pin Assignments No. 5519-2/14 LC74411N, LC74411NE Block Diagram No. 5519-3/14 LC74411N, LC74411NE LC74411N and LC74411NE Based PIP System Function Overview • Reduction sizes – Vertical : 1/3, 1/4; The vertical filter coefficient can be selected. – Horizontal : 1/3, 1/4; Variable at the PLL. • Still image – Field still image • Display position – Eight bits in each of the vertical and horizontal directions • Frame – Frame or no frame can be selected. – Frame types differ according to the insertion method Pin frame : A pin output that goes high at the frame position (for frame insertion by the application) DAC frame : Frame overlapped onto the image signal. Four bits for each of the Y, R-Y, and B-Y signals. • Wipe – Supports eleven different types of wipe. • Blanking size – The vertical and horizontal directions can be specified independently (6 bits each) – Eleven form specification types • Memory clear – The image data written to memory can be set to a fixed value. – Either 25% white or blue can be selected. • Wide-aspect-ratio TV support – Aspect compensation function • Support for NTSC, PAL, and multi-format systems • External control function using the I2C bus – Incorporates six on-chip 8-bit D/A converter circuits – Provides eight general-purpose port pins. • Wide range of settings and adjustments – Sub-screen displacement, color shifting, and other settings can be adjusted using the I2C bus. No. 5519-4/14 LC74411N, LC74411NE Sub-Screen Size The vertical and horizontal directions can be controlled independently. • Vertical size – 1/3: Three scan lines are compressed to one. – 1/4: Four scan lines are compressed to one. • Horizontal size – 1/3: A/D clock : D/A clock = 1:3 – 1/4: A/D clock : D/A clock = 1:4 When 1/4 compression is used, the output data will be 3/4 of 1/3 of the input data. – Aspect ratio correction function The horizontal size is adjusted by changing the VCO frequency (system clock). This frequency can be changed from –30% to +30%. Wipe Function The WTOP, WBOT, WLEFT, and WRIGHT operations can be specified independently. Display Area Function This function controls an area to be blanked. The vertical and horizontal directions can be set independently. The operating mode is set using the wipe function WTOP, WBOT, WLEFT, and WRIGHT parameters. No. 5519-5/14 LC74411N, LC74411NE Application Examples • Exclusion of the masked area from a letterbox screen • Small display Minimizes the hidden sections of the main screen. Internal Control Registers Bit Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H MSB 7 SBY VP7 HP7 0 RFC5 0 PHP-M 0 0 V-BLK 0 DAC1-7 DAC2-7 DAC3-7 DAC4-7 DAC5-7 DAC6-7 PORT7 6 STL VP6 HP6 SIZE-V RFC4 0 PHP-S 0 0 H-BLK YC-AJ2 DAC1-6 DAC2-6 DAC3-6 DAC4-6 DAC5-6 DAC6-6 PORT6 5 NT/PAL VP5 HP5 SIZE-H RFC3 0 WPE VBS5 HBS5 CL-AJ1 YC-AJ1 DAC1-5 DAC2-5 DAC3-5 DAC4-5 DAC5-5 DAC6-5 PORT5 4 D-BLUE VP4 HP4 DAFRM RFC2 PLL4 WP-MOD VBS4 HBS4 CL-AJ0 YC-AJ0 DAC1-4 DAC2-4 DAC3-4 DAC4-4 DAC5-4 DAC6-4 PORT4 3 D-FIX VP3 HP3 YFC5 BFC5 PLL3 WTOP VBS3 HBS3 WV-AJ1 YCFAJ1 DAC1-3 DAC2-3 DAC3-3 DAC4-3 DAC5-3 DAC6-3 PORT3 2 FILD VP2 HP2 YFC4 BFC4 PLL2 WBOT VBS2 HBS2 WV-AJ0 YCFAJ0 DAC1-2 DAC2-2 DAC3-2 DAC4-2 DAC5-2 DAC6-2 PORT2 1 VDF-C0 VP1 HP1 YFC3 BFC3 PLL1 WLEFT VBS1 HBS1 WH-AJ1 FM-AJ1 DAC1-1 DAC2-1 DAC3-1 DAC4-1 DAC5-1 DAC6-1 PORT1 LSB 0 POUT VP0 HP0 YFC2 BFC2 PLL0 WRIGHT VBS0 HBS0 WH-AJ0 FM-AJ0 DAC1-0 DAC2-0 DAC3-0 DAC4-0 DAC5-0 DAC6-0 PORT0 Function Mode settings Vertical display position Horizontal display position Sub-screen size, frame color Frame color PLL value Wipe Vertical display range Horizontal display range Fine adjustment Fine adjustment PWMDAC PWMDAC PWMDAC PWMDAC PWMDAC PWMDAC General-purpose ports 0: These bits must be set to 0. No. 5519-6/14 LC74411N, LC74411NE Register Data Overview Address Register SBY STL NT/PAL D-BLUE D-FIX FILD VDF-CO POUT VP7 to 0 HP7 to 0 SIZE-V SiZE-H DAFRM YFC5 to 2 RFC5 to 2 BFC5 to 2 PLL4 to 0 PHP-M, S WPE WP-MOD WTOP to WRIGHT VBS5 to 0 HBS5 to 0 V-BLK, H-BLK CL-AJ1, 0 WV-AJ1, 0 WH-AJ1, 0 YC-AJ2 to 0 YCFAJ1, 0 FM-AJ1, 0 DAC1-7 to 0 DAC2-7 to 0 DAC3-7 to 0 DAC4-7 to 0 DAC5-7 to 0 DAC6-7 to 0 PORT7 to 0 Notes Standby mode (The PLL circuit operates.) Still image (Writes to internal memory are stopped.) Format selection (H: NTSC, L:PAL) Memory clear data selection (Valid when D-FIX = 1) (H: blue, L: gray) Memory clear (Holds the data written to memory at a fixed value.) Field display selection Vertical filter coefficient selection Sub-screen display on/off Sub-screen vertical position Sub-screen horizontal position Vertical compression specification H: 1/4, L: 1/3 Horizontal compression specification H: 1/4, L: 1/3 D/A converter frame on/off D/A converter frame color (Y) D/A converter frame color (R-Y) D/A converter frame color (B-Y) PLL divisor value (The standard value is 10110.) Field discrimination inversion/noninversion Wipe or display area function enable Wipe or display area function selection (H: wipe) Wipe or display area function format specification Display area range setting (vertical) Display area range setting (horizontal) D/A converter frame output range specification (Normally set to 00B) A/D converter clamping potential adjustment (Can be monitored from the CLAMP pin.) Write vertical direction adjustment Write horizontal direction adjustment C phase (with respect to Y) adjustment D/A converter frame C phase (with respect to Y) adjustment D/A converter frame left/right width adjustment External control D/A converter (8-bit PWM) data External control D/A converter (8-bit PWM) data External control D/A converter (8-bit PWM) data External control D/A converter (8-bit PWM) data External control D/A converter (8-bit PWM) data External control D/A converter (8-bit PWM) data Data for the general-purpose output ports 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H No. 5519-7/14 LC74411N, LC74411NE Pin Functions Pin No. 64E 64S Pin I/O Connection Function Circuit type 13 21 RES I Initialization circuit Reset 45 44 43 42 53 52 51 50 V-M H-M V-S H-S I I I I Main screen vertical synchronizing signal (negative polarity) Synchronization separation Main screen horizontal synchronizing signal (negative polarity) circuit IC Sub-screen vertical synchronizing signal (negative polarity) Sub-screen horizontal synchronizing signal (negative polarity) 14 22 SCL I Microcontroller Serial clock 15 23 SDA I/O Microcontroller Serial data 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36 35 34 38 39 41 40 64 63 62 61 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 ADDR0 ADDR1 PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 D/A1 D/A2 D/A3 D/A4 D/A5 D/A6 FRAME SOUT SOUT2 NC NC DVDD DVSS YA-IN RA-IN BA-IN LVL-IN I I O O O O O O O O O O O O O O O O O DVSS DVSS Must be connected to VSS in normal operation. General-purpose ports PWM D/A converter outputs 44 43 42 46 47 49 48 8 7 6 5 Analog circuits Analog circuits Frame pulse output Main/sub-screen switching signal No connection No connection Power supply Ground I I I I Analog circuits Analog circuits Analog circuits Digital system power supply Digital system power supply Sub-screen analog input (Y) Sub-screen analog input (R-Y) Sub-screen analog input (B-Y) Preset voltage For use by user monitoring circuits A/D converter clamp pulse 37 45 CLAMP O Notes:The 64E pin numbers refer to the LC74411NE and the 64S pin numbers refer to the LC74411N. The letter "S" in an inverter indicates Schmitt input characteristics. Continued on next page. No. 5519-8/14 LC74411N, LC74411NE Continued from preceding page. Pin No. 64E 60 59 58 57 1 2 54 53 52 51 50 55 56 10 11 8 9 12 5 4 7 6 3 49 48 47 46 33 18 64S 4 3 2 1 9 10 62 61 60 59 58 63 64 18 19 16 17 20 13 12 15 14 11 57 56 55 54 41 26 Pin VRH1 VRH2 VRM VRB ADVDD ADVSS YA-OUT RA-OUT BA-OUT VREF BIAS DAVDD DAVSS CP-M FC-M R-M VDD-M VSS-M CP-S FC-S R-S VDD-S VSS-S TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 O I — O O O I — I/O Connection Power supply or VRH2 Open or VRH1 Capacitor Capacitor and VREF Power supply Ground Analog circuits Analog circuits Analog circuits VRB Capacitor Power supply Ground Low-pass filter Low-pass filter Oscillator range setting resistor Power supply Ground Function Low-pass filter Low-pass filter Oscillator range setting resistor Power supply Ground Sub-screen digital analog output (Y) Sub-screen digital analog output (R-Y) Sub-screen digital analog output (B-Y) D/A converter analog setting pin Analog system power supply (D/A converter) Charge pump output Oscillator control voltage input Circuit type O I — VCO power supply Low-pass filter Charge pump output Low-pass filter Oscillator control voltage input Oscillator range setting resistor Power supply VCO power supply Ground I I I I I I DVSS Testing (These pins must connected to DVSS.) Specifications Absolute Maximum Ratings at Ta = 25 ±2°C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg LC74411NE LC74411N Conditions Ratings –0.3 to +7.0 –0.3 to VDD +0.3 –0.3 to VDD +0.3 550 600 –10 to +70 –55 to +125 Unit V V V mW mW °C °C Allowable Operating Ranges at Ta = –10 to +70°C, VSS = 0 V Parameter Supply voltage Digital input high-level voltage Digital input low-level voltage Analog input voltage Reference voltage VREF VDD VIH VIL The YA-IN, RA-IN, and BA-IN pins 2.7 ADVDD-VRB Symbol Conditions LC74411NE LC74411N min 4.75 4.5 0.7VDD typ 5.0 5.0 max 5.25 5.5 Unit V V V 0.3VDD 0.8VDD VDD V Vp-p V No. 5519-9/14 LC74411N, LC74411NE Electrical Characteristics at Ta = 25 ±2°C, VDD = 5 V ±5% (LC74411NE), VDD = 5 V ±10% (LC74411N), VSS = 0 V Parameter Output high-level voltage Symbol VOH1 VOH2 VOL1 Output low-level voltage VOL2 VOL3 Quiescent current drain Reference voltage (M) Reference voltage (B) Input leakage current Output leakage current D/A converter output resistance IDDST VRM VRB ILK IOZ RDA Conditions IOH = –1 mA, the CP-M and CP-S pins IOH = –1 mA, pins other than CP-M and CP-S IOL = 1 mA, the CP-M and CP-S pins IOL = 3 mA, the SDA pin IOL = 2 mA, pins other than the pins mentioned above RES = VSS, DC pin inputs, no output loads When VRH1 is connected to ADVDD When VRH1 is connected to ADVDD VI = VDD, VSS VI = VDD, VSS; the CP-M and CP-S pins –1 –1 300 0.9VDD 0.8VDD +1 +1 min VDD–1 VDD–1 1.0 0.4 0.4 10 typ max Unit V V V V V µA V V µA µA Ω Switching Characteristics at Ta = 25 ±2°C, VDD = 5 V ±5% (LC74411NE), VDD = 5 V ±10% (LC74411N), VSS = 0 V Parameter Vertical synchronizing signal Pulse width Rise time Fall time Horizontal synchronizing signal Pulse width Rise time Fall time I2C timing SCL frequency Bus release time Start/hold SCL low period SCL high period Data hold time Data setup time Rise time Fall time Stop setup time tSCL tBUF tHD STA tLOW tHIGH tHD DAT tSU DAT tR tF tSU STO 4.0 4.7 4.0 4.7 4.0 0 250 1000 300 100 kHz µs µs µs µs µs ns ns ns µs tHW tHR tHF 1 300 300 µs ns ns tVW tVR tVF 1 300 300 µs ns ns Symbol Conditions min typ max Unit No. 5519-10/14 LC74411N, LC74411NE Sub-Screen Digital Processing Specifications Item Order Frequency fT (MHz) Y only A/D converter sampling fTY R-Y only fTR B-Y only fTB Number of bits in quantization Y signal fCY D/A converter clock (MHz)*1 R-Y signal fCR B-Y signal fCB Number of horizontal bits Y only Write R-Y only B-Y only Number of vertical lines Number of horizontal bits Y only Readout display*2 R-Y only B-Y only Number of vertical lines 72 73 268 180 44 44 84 2.895 288 192 48 48 85 2.895 184 fH 2.875 11.58 184 fH 2.875 0.944 6 bits 736 fH 11.50 0.944 60 fH 0.938 3.776 60 fH 0.938 7.552 240 fH 3.750 NTSC (fH = 15734Hz) Y, R–Y, Y, B–Y, Y, –, Y, –, ······ 480 fH 7.500 PAL (fH = 15625Hz) Note: 1. When the PLL divisor has its standard value (PLL4:0 = 10110). 2. Target values are shown. (The number of horizontal bits varies with, for example, the frame width adjustment.) Initialization (1) RES pin: Reset The RES pin must be held low when power is first applied with the timing shown in the figure. (2) Internal control registers After a reset, the chip goes to the standby state (SBY = high). When developing the microcontroller software, that software must be designed so that it transmits data for all registers. Also note that data values of zero (0) must be sent for the control registers that have ‘0’ entries in the control register table. No. 5519-11/14 LC74411N, LC74411NE I2C Control Data format Data 1 is stored at register address A1. Data 2 is stored at register address A1 + 1, i.e., the address given by incrementing A1. If the address exceeds 11H, it wraps to 00H. Slave address: A6 0 A5 0 A4 1 A3 0 A2 0 A1 1 A0 1 R/W 0 Synchronizing Signal Input • Sync separation The LC74411N and LC74411NE require sync separated (including AFC processing) V and H signals for both the main and sub-screen. Since V is used for field discrimination and H is used as the PLL reference signal, these signals must be provided reliably. – The H-M and H-S pin inputs are assumed to be delayed about 1 µs from the video signal’s horizontal synchronizing signal and set to standard values. – Equalizing pulses must be excluded. – Since noise on the synchronizing signal will disrupt the display, these lines should be placed carefully. – If the synchronizing signal is unstable, the sub-screen display may be disrupted. We recommend turning off subscreen display in such cases. • Field discrimination circuit Since the circuit discriminates based on the phase difference between the falling edges of the H and L signals, these signals must be provided with the timing shown in the figure below. No. 5519-12/14 LC74411N, LC74411NE Clamp Pulses • A/D converter clamping Since clamp pulses are output to the built-in A/D converter with the timing shown in the figure below, they are set up to fall in the pedestal range. The clamp pulses can be monitored at the CLAMP pin. On a reset or in standby mode, the H-S input signal becomes positive polarity and is output without change. • D/A converter clamp External Control Output Blanking No. 5519-13/14 LC74411N, LC74411NE s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5519-14/14