LC74950BG

Ordering number : ENA1647 CMOS IC LC74950BG Overview Silicon gate 40/30MSPS Analog Display I/F LSI The LC74950BG is an analog display I/F IC that converts analog video signals into equivalent digital video signals. It incorporates 3 channels of ADC and a PLL circuit. Features • Maximum sampling frequency: 40MSPS • 8-bit output • Supports self-clamp (bottom/center switching) and digital clamp • Input signal: 1.0Vp-p maximum • External clock input • Low jitter PLL • Power down mode • Low power consumption • Input format: Supports RGB and YCbCr • Built-in I2C bus interface LSI Specifications • Supply voltage Core: 1.5±10% I/O: 3.3V±0.3V (40MHz) or 2.4V to 3.6V (30MHz) • Maximum operating frequency: 40MHz • Package: FBGA96 Principal Applications • Small-size monitors Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 31710HKIM 20091215-S00006 No.A1647-1/37 LC74950BG Functions & Overview 1. Input All the inputs listed below can be connected to the analog ports. It is also possible to switch between the inputs of two systems and use the one selected. YCbCr/YPbPr input (480I/576I, 480P/576P): Component input RGB: RGB input External clock supported 2. Output Digital 8-bit/channel output 3. Clamp Analog clamping and digital clamping supported 4. Gain Digital gain adjustment 5. PLL circuit This circuit can be used as the H lock or frequency-multiplied clock. It is also possible to use the PLL circuit and analog-digital converter (ADC) independently. H lock PLL circuit: This makes it possible to generate a clock synchronized with the external H sync signal. Frequency-multiplier PLL circuit: This makes it possible to generate clocks synchronized with an external clock. 6. External interface I2C: This supports the 100kHz mode. It is possible to select slave addresses by establishing pin settings. Slave addresses: 0x98, 0x9A 7. PDOWN Power-down of the whole system can be controlled using the PDOWN pin. Alternatively, the ADC, PLL and other circuits can be powered down separately using register settings. This makes it possible to limit the power as required. Specifications Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter Maximum supply voltage (I/O) Maximum supply voltage (core) Digital input voltage Symbol DVDD33 AVDD33 DVDD15 AVDD15 VI VI (when in low voltage) Digital output voltage Operating temperature Storage temperature VO Topr Tstg Conditions Ratings -0.3 to +3.95 -0.3 to +1.8 -0.3 to +5.5 -0.3 to DVDD33+0.3 -0.3 to DVDD33+0.3 -30 to +70 -55 to +125 Unit V V V V V °C °C Allowable Operating Ranges at Ta = -30 to +70°C Parameter Supply voltage (I/O) Symbol AVDD33 DVDD33 Supply voltage (I/O) Input voltage range (5V withstand voltage pin) Input voltage range (non-5V withstand voltage pin) VIN DVDD15 AVDD15 VIN5 Max 40MHz Max 30MHz Conditions Ratings min 3.00 3.00 2.40 1.35 0 0 typ 3.3 3.3 3.3 1.5 max 3.60 3.60 3.60 1.65 5.5 3.9 unit V V V V V V No.A1647-2/37 LC74950BG DC Characteristics at Ta = -30 to +70°C, DVDD33 = 3.3V±0.3V (other than low-voltage support models), DVDD15= 1.5±10% Parameter Input high-level voltage Symbol VIH Conditions CMOS level inputs (5V withstand voltage pin) CMOS level inputs (2.4V to 3.6V or non-5V withstand voltage pin) CMOS level Schmitt inputs (5V withstand voltage pin) CMOS level Schmitt inputs (2.4V to 3.6V or non-5V withstand voltage pin) Input low-level voltage VIL IIH IIL VOH VOL IOZ RDN IDDOP CMOS level inputs CMOS level Schmitt inputs Input high-level current VI=DVDD VI=DVDD, with pull-down resistance Input low-level current Output high-level voltage Output low-level voltage Output leak current Pull-down resistor VI=VSS CMOS (Pin G/I: IOH=-4mA, Pin F: when set to -6mA) CMOS At output of high-impedance 3.0V to 3.6V 2.4V to 3.6V Dynamic supply current (DVDD33) Dynamic supply current (DVDD15) Dynamic supply current (AVDD33) Dynamic supply current (AVDD15) Static supply current: *1 IDDST tck=27MHz: natural image, Ta=25°C Outputs open, VI=VSS, Ta=25°C Outputs open, tck=27MHz natural image, Ta=25°C tck=27MHz: natural image, Ta=25°C tck=27MHz: natural image, Ta=25°C -10 58 70 13 7 52 0.1 10 -10 DVDD-0.6 0.4 10 100 Ratings min 0.8DVDD33 0.8DVDD33 2.0 0.8DVDD33 0 0 typ max 5.5 DVDD33 5.5 DVDD33 0.2VDD33 0.2VDD33 10 unit V V V V V V μA μA μA V V μA kΩ kΩ mA mA mA mA μA *1: There is an input terminal which builds in pull down resistance. Please note that there is no guarantee about static consumption current depending on circuit composition. A/D Convertor Characteristics at Ta = 25°C, DVSS = 0V, AVSS = 0V Parameter ADC resolution Clock frequency SNR DNL INL External capacitance Analog input coupling capacitance Top level reference fixed capacitance Bottom level reference capacitance Analog input frequency Analog input amplitude ADC stabilization time (time required to restore from standby mode) PLL lock time Analog video pin VRTx pin VRBx pin FAIN 1.0 500 3 0.1 0.01 0.01 10 μF μF μF MHz V ms ms Fclk 5 48 ±0.5 ±1.0 Symbol/pin min typ max 9 40 Unit bit MHz dB LSB LSB No.A1647-3/37 LC74950BG Package Dimensions: FBGA96 unit: mm (typ) 3387 TOP VIEW 6.0 SIDE VIEW 0.5 BOTTOM VIEW 0.75 1 2 3 4 5 6 7 8 9 10 6.0 0.5 0.75 K J H GF E D C B A SIDE VIEW 0.1 1.05 MAX 0.29 SANYO : ISB96(6.0X6.0) Pin Assignment LC74950BG 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Top view No.A1647-4/37 LC74950BG Block Diagram LC74950BG G/Y G/Y B / Cb B / Cb R / Cr R / Cr SW SW Clamp Clamp ADC ADC 9 Clamp Clamp Gain Gain 8 G/Y B / Cb SW Clamp ADC SW Clamp SW Gain R / Cr CLK SW HS / VS SDA SCL IC 2 PLL HS / VS DE CLK Power Down RESET Pin Functions Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Pin symbol ADC2AVSS33 CBOUT0 CBOUT2 CBOUT4 CBOUT6 PDWN AVSS33_PLL CHRGPMP AVDD33_PLL DVDD15 VRT2 ADC2AVSS33 CBOUT1 CBOUT3 CBOUT5 CBOUT7 DVSS AVSS33_PLL DVDD15 HSIN CRIN1 VRB2 ADC2AVDD33A DVSS DVSS DVSS DVDD15 DVDD15 VSIN RESET In/output format I/O P I/O I/O I/O I/O I P O P P I P I/O I/O I/O I/O P P P I I I P P P P P P I I B B B A A 3.3V GND GND GND 1.5V 1.5V 3.3V CMOS 3.3V CMOS I I I I A GND 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS GND GND 1.5V 3.3V CMOS to 1.0Vp-p A 3.3V 1.5V I I I I B Format GND 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS GND Connecting destination Analog Digital Digital Digital Digital Digital Analog Analog Analog Digital Analog Analog Digital Digital Digital Digital Digital Analog Digital Digital Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Vertical synchronizing signal System reset “L” reset It must be treated in the same way as an NC pin. Horizontal synchronizing signal Analog CR or R input (ADC2) Bottom level reference voltage connection pin for ADC2 Video signal output Cb or B Video signal output Cb or B Video signal output Cb or B Video signal output Cb or G (MSB) Top level reference voltage connection pin for ADC2 Filter input PLL power supply Remarks It must be treated in the same way as an NC pin. Video signal output Cb or B (LSB) Video signal output Cb or B Video signal output Cb or B Video signal output Cb or B Power DOWN ”L” Power DOWN Continued on next page. No.A1647-5/37 LC74950BG Continued from preceding page. Pin No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E7 E8 E9 E10 F1 F2 F3 F4 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 Pin symbol VRT1 CRIN0 ADC1AVSS33 DVSS DVSS DVSS DVDD15 DVDD15 CLKOUT2 CLKOUT1 CBIN1 VRB1 ADC1AVDD33A DVSS DVDD15 I2CSEL SCL COAST VRT0 CBIN0 ADC0AVSS33 DVSS DVDD15 TEST SDA CLKIN YGIN1 VRB0 ADC0AVDD33 SCANEN DVDD33 DVDD33 DVDD33 DVDD33 HSOUT VSOUT ATB YGIN0 AVDD15_OSC SCANMOD DVDD33 DVDD33 DVDD33 DVDD33 CROUT7 DEOUT In/output format I/O I I P P P P P P O O I I P P P I I I I I P P P I I/O I I I P I P P P P I/O I/O O I P I P P P P I/O I/O I I H I I A A to 1.0Vp-p 1.5V 3.3V CMOS 3.3V 3.3V 3.3V 3.3V 3.3V CMOS 3.3V CMOS Analog Analog Digital Digital Digital Digital Digital Digital Digital Video signal output Cr or R (MSB) Data enable. It must be held open when not to be used. H H G D A A 3.3V 3.3V CMOS 3.3V 3.3V 3.3V 3.3V 3.3V CMOS 3.3V CMOS 3.3V CMOS to 1.0Vp-p C D B A A to 1.0Vp-p GND GND 1.5V 3.3V CMOS 3.3V CMOS F F A A 3.3V GND 1.5V 3.3V CMOS Digital Digital Analog Analog Analog Digital Digital Digital Digital Digital Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital Horizontal synchronizing signal Vertical synchronizing signal Analog output for testing the ADC. It must be held open when not to be used. Analog Y or G input (ADC0) Power supply for the RC oscillator Test pin (normally, Lo) Test pin (normally, Lo) System clock (Must be connected to GND when not to be used) Analog Y or G input (ADC0) Bottom level reference voltage connection pin for ADC0 Test pin (normally fixed low) Connected to GND Top level reference voltage connection pin for ADC0 Analog CB or B input (ADC1) Analog Digital Digital I2C slave addresses L=0×98, H=0×9A Format A A to 1.0Vp-p GND GND GND GND 1.5V 1.5V 3.3V CMOS 3.3V CMOS to 1.0Vp-p Analog Analog Digital Digital Digital Digital Digital Digital Digital Analog CLKOUT1×2 output or PLL output Datasynchronization clock output Analog CB or B input (ADC1) Bottom level reference voltage connection pin for ADC1 Connecting destination Remarks Top level reference voltage connection pin for ADC1 Analog CR or R input (ADC2) Continued on next page. No.A1647-6/37 LC74950BG Continued from preceding page. Pin No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Pin symbol SVO AVSS_OSC YGOUT1 YGOUT7 YGOUT4 CROUT0 CROUT3 CROUT5 DVDD33 CROUT6 AVSS_OSC YGOUT0 YGOUT2 YGOUT3 YGOUT5 YGOUT6 CROUT1 CROUT2 CROUT4 DVDD33 In/output format I/O O P I/O I/O I/O I/O I/O I/O P I/O P I/O I/O I/O I/O I/O I/O I/O I/O P I I I I I I I I I I I I I I I Format A Connecting destination to 1.0Vp-p GND 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V 3.3V CMOS GND 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V Digital Digital Digital Digital Digital Digital Digital Analog Digital Digital Digital Digital Digital Video signal output Cr or R It must be treated in the same way as an NC pin. Video signal output Y or G (LSB) Video signal output Y or G Video signal output Y or G Video signal output Y or G Video signal output Y or G Video signal output Cr or R Video signal output Cr or R Video signal output Cr or R It must be treated in the same way as an NC pin. Analog Analog Digital Digital Digital Video signal output Y or G Video signal output Y or G (MSB) Video signal output Y or G Video signal output Cr or R (LSB) Video signal output Cr or R Video signal output Cr or R Remarks Test pin. It must be held open when not to be used. No.A1647-7/37 LC74950BG Pin Type In/Output form A Function Analog input/output Equivalent circuit CHRGPMP, CRIN0, CRIN1, VRT2, VRB2, CBIN0, CBIN1, VRT1, VRB1, YGIN0, YGIN1, VRT0, VRB0, SVO, ATB B 5V withstand Schmitt trigger CMOS input * C 5V withstand CMOS input with built-in pull-down resistor * I2CSEL HSIN, PDWN, VSIN, COAST, RESET Application Terminal D 5V withstand CMOS input * CLKIN, SCL F 12mA switching 3-STATE drive CMOS output CKOUT1, CKOUT2 G 8mA 3-STATE drive CMOS input/output * (5V withstand) SDA H CMOS input with built-in pull-down resistor TEST, SCANEN, SCANMOD I 8mA 3-STATE drive CMOS input/output HSOUT, VSOUT, DEOUT, CROUT0, CROUT1, CROUT2, CROUT3, CROUT4, CROUT5, CROUT6, CROUT7, CBOUT4, CBOUT5, CBOUT6, CBOUT7, CBOUT0, CBOUT1, CBOUT2, CBOUT3, YGOUT0, YGOUT1, YGOUT2, YGOUT3, YGOUT4, YGOUT5, YGOUT6, YGOUT7 *: 5V Tolerant No.A1647-8/37 LC74950BG Pin Connection 1) ADC and its peripherals VRTx VRBx 0.1μF VRTx: VRT0, VRT1, VRT2 VRBx: VRB0, VRB1, VRB2 10 μ F 0.1μF 0.1μF 10μF 0.1μF xINx Terminal resistor YGIN0, YGIN1 CRIN0, CRIN1 CBIN0, CBIN1 2) PLL and its pereipherals CHRGPMP 3.3kΩ 3) Output pin (recommended) CBOUT0-3 5pF 0.068μF 0.0039μF 4) Power supplies The analog A** and digital D** power supplies must be supplied separately without fail. In addition, the power supply for the PLL circuit must also be provided separately as it will affect the jitter characteristics of the PLL circuit. For ADC power supply, it is desirable to provide separate power for eachof the ADC channel. AVDD33_PLL : Must be separated by L components, etc. ADC2AVDD33A : Separating by L components, etc. recommended ADC1AVDD33A : Separating by L components, etc. recommended ADC0AVDD33A : Separating by L components, etc. recommended 5) Unused pin treatment YGIN0, 1/CBIN0, 1/CRIN0, 1: Open PDWN: Pull up CHRGPMP: Open (when PLL is not in use) ***OUT* (e.g., YGOUT0): Open HSIN/VSIN: Must always be configured for input. RESET: Must always be configured for input. COAST: Must be connected to DVSS. TEST, SCANEN, SCANMOD: DVSS CLKIN: DVSS HSOUT, VSOUT, DEOUT: Open SVO, ATB: Open * The specified voltage of power must be applied to each of the power supply pin even if it is not to be used (PLL is not to be used, for example). No.A1647-9/37 LC74950BG I/O Data Timing (1) Input data timing tHI CLKIN tSU tHD tLO tCK VDD33/2 Input data VDD33/2 Pin name CLKIN Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 tSU tSU tHD tHD 3.0 3.0 3.0 3.0 % ns ns ns ns Input data setup time (DVDD33=3.0 to 3.6V) Input data setup time HSIN, VSIN (DVDD33=2.4 to 3.6V) Input data hold time (DVDD33=3.0 to 3.6V) Input data hold time (DVDD33=2.4 to 3.6V) *: The recommended duty cycle of input clock is 50% (2) Output data timing tHI CLKOUT1 tAC tHD Output data tLO tCK VDD33/2 VDD33/2 Pin name CLKOUT1 Clock cycle Duty Parameter Symbol tCK min 25 typ max unit ns 50 tAC tAC tHD tHD 0 0 3.0 3.0 2.0 3.0 % ns ns ns ns Output data delay time (3.0 to 3.6V) Output data delay time YGOUT*, CBOUT*, CROUT*, HSOUT ,VSOUT, DEOUT (2.4 to 3.6V) Output data hold time (3.0 to 3.6V) Output data hold time (2.4 to 3.6V) * When CLKOUT1 is set to the forward rotation output. No.A1647-10/37 LC74950BG Timing Chart N Analog input N+1 N+2 CLKIN Output data N-50 N-49 N N+1 Note: For the initial setting of the registers Details of the functions 1. Selection of input pins Registers related to the selection of input pins Name AINSEL Video input select control Analog video input select 0: YGIN0/CBIN0/CRIN0 1: YGIN1/CBIN1/CRIN1 Functions Sub address 0x22 bit width 1 • Video input selector function The video input signal used for actual processing can be selected out of the two systems of video input. AINSEL=0: YGIN0/CBIN0/CRIN0 AINSEL=1: YGIN1/CBIN1/CRIN1 2. Input format Registers related to the selection of the input format Name SELYCRGB SYNCON 0: YCbCr, 1: RGB For YCbCr input, this register, by cutting off the digitally clamped sync component of the Y video signal, sets the applicable gain adjustment function to ON or OFF. This must be set to 0 for the RGB input (SELYCRGB=1). 0: ON, 1: OFF 0x1B 1 Functions This register switches between the YCbCr input and RGB input. Sub address 0x14 bit width 1 All the inputs listed below can be connected to the analog ports. It is also possible to switch between the inputs of two systems and use the one selected. YCbCr/YPbPr input (480I/576I, 480P/576P): Component input RGB: RGB input 3. Operating modes Register related to the selection of operating mode Name CLKSEL Operating mode selection 000: External clock mode (PLL not used) 001: External clock mode (PLL used) 010: H lock PLL mode 011: Panel PLL mode 100: Panel PLL mode Functions Sub address 0x00 bit width 3 No.A1647-11/37 LC74950BG 1) External clock mode (PLL not used: CLKOUT1=CLKIN/2, CLKOUT2=CLKIN) Example: Component input (NTSC) (down sample) LC74950BG 8 G/Y B/Cb R/Cr ADC Analog Selfclamping Digital Clamp Gain Offset 8 B OUT 8 R OUT G OUT CKGEN 1/2 CLK IN (27MHz) HS IN S E L S E L S E L 13.5MHz CLKOUT1 1/2 PLL 27MHz CLKOUT2 VS OUT VS IN PDOWN RESET IC 2 Timing Generator HS OUT DE OUT 2) External clock mode (PLL used: CLKOUT1=CLKIN, CLKOUT2=CLKIN*2) Example: Component input (NTSC) (2× clock generation) LC74950BG 8 G/Y B/Cb R/Cr ADC Analog Selfclamping Digital Clamp Gain Offset 8 B OUT 8 R OUT G OUT CKGEN 1/2 CLK IN (13.5MHz) HS IN S E L S E L S E L 13.5MHz CLKOUT1 1/2 PLL 27MHz CLKOUT2 VS OUT VS IN Timing Generator HS OUT DE OUT PDOWN RESET IC 2 No.A1647-12/37 LC74950BG 3) H-lock PLL mode (PLL used: CLKOUT1=HS/Divide, CLKOUT2=CLKOUT1*2) Example: Component input (NTSC) (2× clock generation) LC74950BG G/Y B/Cb R/Cr ADC Analog Selfclamping Digital Clamp Gain Offset 8 G OUT 8 B OUT 8 R OUT CKGEN 1/2 CLK IN HS IN S E L S E L S E L 13.5MHz CLKOUT1 1/2 PLL 27MHz CLKOUT2 VS IN PDOWN RESET Timing Generator VS OUT HS OUT DE OUT IC 2 4) ADC/PLL independent mode (External clock input, PLL configured independently: CLKOUT1=CLKIN/2, CLKOUT2=CLKIN/In-Divide*OutDivide) Example: Component (ADC down sample), PLL: Generation of separate system clock LC74950BG 8 G/Y B/Cb R/Cr ADC Analog Selfclamping Digital Clamp Gain Offset 8 B OUT 8 R OUT G OUT CKGEN 1/2 CLK IN (27MHz) HS IN S E L 1/2 PLL S E L S E L 13.5MHz CLKOUT1 33MHz CLKOUT2 VS OUT VS IN PDOWN RESET Timing Generator HS OUT DE OUT IC 2 No.A1647-13/37 LC74950BG 5) ADC/PLL independent mode (External clock input, PLL configured separately: CLKOUT1=CLKIN, CLKOUT2=CLKIN/In-Divide*Out-Divide) Example: Component (ADC down sample), PLL: Generation of separate system clock LC74950ADC G/Y B/Cb R/Cr ADC Analog Selfclamping Digital Clamp Gain Offset 8 8 B OUT 8 R OUT G OUT CKGEN 1/2 CLK IN (13.5MHz) HS IN S E L 1/2 PLL S E L S E L 13.5MHz CLKOUT1 33MHz CLKOUT2 VS IN Timing Generator VS OUT HS OUT DE OUT PDOWN RESET IC 2 4. Clock system 1) Clock system diagram CLKIN POWERIN CLKSEL 00h, bit2-0 CLKININV 00h, bit4 HSIN HSINV 03h, bit3 3 CLKSEL 00h, bit2-0 / CLKOUT2INV 00h, bit7 CLKINDIV / 40h, bit5-0 6 1/1 to 1/64 Divider 1/2 Divider CLKSEL 00h, bit2-0 3 / CLKOUT1INV 00h, bit6 CLKOUT *1 CLKOUT1 CLKADC *2 ADC C FIN *2 CLKADCINV 00h, bit3 FOUT *1 PLL FOUTX2 *1 CLKOUTINV 01h, bit7 logic CLKOUT2 *2 *1 Explanation of signals FOUT: A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of FIN and PLL divider value (HPLDIV, 28h-29h, bits 15-0) determine the frequency of FOUT. FOUTX2: A clock generated in the PLL circuit and synchronized with the reference signal (FIN). The frequency of FOUTX2 is two times of the frequency of FOUT. CLKOUT: A clock generated in the ADC. To output the clock it is necessary to adjust the phase of the sampling clock (CLKADC) in order that the rising edge of the clock does not occur near the change point of the ADC sampled data. No.A1647-14/37 LC74950BG Registers related to the control of clock Name CLKININV reference clock to PLL. 0: Uses CLKIN in its original form 1: Uses CLKIN in its inverted form HSINV This register controls the inversion of HSIN input. The HSIN must be used in its inverted form when the polarity of HSIN input is negative. 0: Original form (when HSIN is positive) 1: Inverted form (when HSIN is negative) CLKINDIV This register sets the frequency division ratio of CLKIN to an arbitrary value (1/1 to1/64) when the CLKIN is used as a reference clock to PLL. 1/(CLKINDIV[5:0]+1) division CLKSEL This register selects the operating mode. 000: (External clock mode (PLL not used) 001: (External clock mode (PLL used) 010: H-lock PLL mode 011: Panel PLL mode 100: Panel PLL mode CLKADCINV This register controls the inversion of the ADC sampling clock (CLKADC). 0: Uses CLKADC in its original form 1: Uses CLKADC in its inverted form CLKOUTINV This register controls the inversion of the ADC-generated clock. (CLKOUT). 0: Uses CLKOUT in its original form 1: Uses CLKOUT in its inverted form CLKOUT1INV This register controls the inversion of CLKOUT (video clock output). 0: Original form 1: Inverted form CLKOUT2INV This register controls the inversion of CLKOUT2 (panel clock output). 0: Original form 1: Inverted form 0x00 1 0x00 1 0x01 1 0x00 1 0x00 3 0x40 6 0x02 1 Functions This register controls the inversion of CLKIN when the CLKIN input is used as a Sub address 0x00 bit width 2 *2 Clock control register (CLKSEL, 00h, bits 2-0) specifications CLKSEL (bit2-0) 000 001 010 011 100 CLKADC*3 (ADC sampling clock) CLKIN/2 (13.5MHz) FOUT (PLL output) FOUT (PLL output) CLKIN/2 CLKIN FIN (PLL reference) L fixed (PLL not used) CLKIN *4 HSIN *5 CLKIN *4 CLKIN *4 CLKOUT2 (Clock output) CLKIN(27MHz) FOUTX2 (PLL output X2) FOUTX2 (PLL output X2) FOUT (PLL output) FOUT (PLL output) Remarks External clock mode (PLL not used) External clock mode (PLL used) H-lock PLL mode Panel PLL mode Panel PLL mode *3: Register CLKADCINV (00h, bit 3) allows for clock inversion. *4: Register CLKINDIV (40h, bits 5-0) allows for division of clock frequency (1/1 to 1/64). *5: Register HSINV (03h, bit 3) allows for HSIN inversion. No.A1647-15/37 LC74950BG 2) PLL circuit CLKIN POWERIN CLKSEL 00h, bit2-0 CLKININV 00h, bit4 HSIN HSINV 03h, bit3 FOUTX2 frequency=(FIN frequency)×M×2×N FOUT frequency=(FIN frequency) ×M×N Feedback Divider (N=2 to 4097) CLKINDIV 40h, bit5-0 1/1 to 1/64 Divider / 6 FIN PLL VCO Output Divider (M=1 to 16) 1/2 FOUT×2 FOUT This circuit can be used as the H lock or frequency-multiplied clock. It is also possible to use the PLL circuit and analog-digital converter (ADC) independently. H lock PLL circuit: This makes it possible to generate a clock that is synchronized with the external H sync signal. Frequency-multiplier PLL circuit: This makes it possible to generate clocks that are synchronized with an external clock. Registers related to the setting of PLL circuit Name CLKININV reference clock to PLL. 0: Uses CLKIN in its original form 1: Uses CLKIN in its inverted form HSINV This register controls the inversion of HSIN input. The HSIN must be used in its inverted form when the polarity of HSIN input is negative. 0: Original form (when HSIN is positive) 1: Inverted form (when HSIN is negative) CLKINDIV This register sets the frequency division ratio of CLKIN to an arbitrary value (1/1 to 1/64) when the CLKIN is used as a reference clock to PLL. 1/(CLKINDIV[5:0] 1) division CLKSEL This register selects the PLL reference input. 000: L fixed (PLL not used) 001: External clock input (CLKIN) 010: External Hsync input (HSIN) 011: External clock input (CLKIN) 100: External clock input (CLKIN) HPLDIV15-12 HPLDIV11-0 This register sets the output divider (M-1, NTSC, 480i=3). This register sets the feedback divider (N-2, NTSC, 480i=856). H-lock PLL output frequency (1x)=Hsync frequency×N H-lock PLL output frequency (2x)=Hsync frequency×N×2 * After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get stabilized. 0x28 0x28 0x29 4 12 0x00 3 0x40 6 0x02 1 Functions This register controls the inversion of CLKIN when the CLKIN input is used as a Sub address 0x00 bit width 2 Continued on next page. No.A1647-16/37 LC74950BG Continued from preceding page. Name PLLGAIN Functions This register switches the setting of Fmin, Fmax, and Gain of the H-lock PLL VCO. 000: Fmin=60MHz, Fmax=240MHz, Gain=120MHz/V←Standard setting 001: Fmin=Standard, Fmax=Standard-20%, Gain=Standard-22.5% 010: Fmin=Standard-20%, Fmax=Standard, Gain=Standard+2.5% 011: Fmin=Standard-20%, Fmax=Standard-20%, Gain=Standard-20.0% 100: Fmin=Standard+20%, Fmax=Standard+10%, Gain=Standard+8.75% 101: Fmin=Standard+20%, Fmax=Standard-10%, Gain=Standard-13.75% 110: Fmin=Standard, Fmax=Standard+10%, Gain=Standard+11.25% 111: Fmin=Standard, Fmax=Standard-10%, Gain=Standard-11.25% * After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get stabilized. PLLCTL2 H-lock PLL power down mode 0: Normal operation 1: H-lock PLL power OFF PLLCTL1 H-lock PLL Normal Mode FOUT Disable 0: Normal operation 1: H-lock PLL output= L fixed CPIS_COAST CPIS_ORG These registers set the PLL charge pump constant current (make sure that CPIS_COAST=CPIS_ORG) 0000: 40μA 0001: 60μA 0010: 120μA 0011: 180μA 0100: 200μA 0110: 280μA 0101: 300μA 1000: 360μA 0111: 420μA 1010: 440μA ←Standard setting 1100: 520μA 1001: 540μA 1110: 600μA 1011: 660μA 1101: 780μA 1111: 900μA * After changing the setting, an interval of 3.0ms is required for the H-lock PLL to get stabilized. 0x2A 4 0x27 1 0x27 1 Sub address 0x27 bit width 3 PLL setting example (when using as H-lock PLL) Ref [kHz] NTSC NTSC PAL PAL PAL-N PAL-M QVGA VGA WVGA 15.734 15.734 15.630 15.630 15.630 15.734 15.70 31.5 31.0 CLKSEL [2:0] 2h 2h 2h 2h 2h 2h 2h 2h 2h PLLDIV 15-12 3h 7h 3h 7h 7h 7h Fh 3h 3h PLLDIV 11-0 6B2h 358h 6BEh 35Eh 35Eh 358h 1A6h 31Eh 41Eh FVCO* [MHz] 216 216 216 216 216 216 213 201 262 FOUTX2 [MHz] (54) 27 (54) 27 27 27 13.3 (50.4) (65.4) FOUT [MHz] 27 13.5 27 13.5 13.5 13.5 6.68 25.2 32.7 CPIS [3:0] Ch Ch Ch Ch Ch Ch Ch Ch Dh PLLGAIN [2:0] 0h 0h 0h 0h 0h 0h 0h 0h 0h *20MHz < FVCO < 340MHz No.A1647-17/37 LC74950BG 5. Timing control 1) DEOUT (enable output) setting Registers related to the setting of enable Name HBLKS HBLKE VBLKS VBLKE Set value smaller than HBLKE. This register specifies the 1H end position of DEOUT in dot units. Set the value that is larger than HBLKS and does not overlap the next Hsync. This register specifies the 1V start position of DEOUT in line units. Set the value smaller than VBLKE. This register specifies the 1V end position of DEOUT in line units. Set the value that is larger than VBLKS and does not overlap the next Vsync. Functions This register specifies the 1H start position of DEOUT in dot units. Sub address 0x04 0x05 0x04 0x06 0x07 0x08 0x07 0x09 11 11 12 bit width 12 • Setting of horizontal enable CLKOUT1 HSOUT CROUT7-0 YGOUT7-0 CBOUT7-0 DEOUT HBLKS [11:0] HBLKE [11:0] *1 R0 G0 B0 R1 G1 B1 R2 G2 B2 ... ... ... R1439 G1439 B1439 *1: DEOUT is forcibly disabled at the leading edge of the next HSOUT even if HBLKE[11:0] is set with a value larger than the total pixel count of 1H. • Setting of vertical enable HSOUT VSOUT CROUT7-0 YGOUT7-0 CBOUT7-0 DEOUT Active Line Active Line Active Line VBLKS [10:0] VBLKE [10:0] *2 *2: DEOUT is forced disabled at the leading edge of the next VSOUT even if VBLKE[10:0] is set with a value larger than the total line count of 1V. No.A1647-18/37 LC74950BG 2) SYNC width adjustment (H-lock PLL mode only) of horizontal sync output (HSOUT) Registers related to SYNC width adjustment of HSOUT Name HSPLLSEL 0: HSIN 1: This is the signal that is fed back to the phase detector after dividing the VCO output of the PLL. *: SYNC width adjustment for HSOUT must be turned on when HSPLLSEL is set to 1. CORREN CORRHSS CORRHSE This register turns on and off the SYNC width adjustment for HSOUT. 0: OFF, 1: ON SYNC width adjustment register for HSOUT (to be described below) SYNC width adjustment register for HSOUT (to be described below) 0x2B 0x2C 0x2B 0x2D 12 12 0x27 1 Functions This register selects the horizontal sync signal (SHOUT) in the H-lock PLL mode. Sub address 0x01 bit width 1 When "1" is set for HSPLLSEL in the H lock PLL mode, the horizontal sync output signal is not HSIN but the signal that is fed back to the phase detector after dividing the VCO output of the PLL. The duty ratio of this signal is 50%, which means when it is to be used as the horizontal sync signal, the sync width must be determined. Furthermore, if "0" is set for HSPLLSEL, the horizontal sync input (HSIN) signal can be output in its original form even in the H lock PLL mode. Feedback signal to the phase detector HSOUT (HSOUTINV=0) (CORRHSS [11:0] + 3) clock *1 CORRHSE [11:0] *2 *1: Clock is expressed in units of CLKOUT1. *2: A value equivalent to about three-fourths of one HSOUT period (640 or so with the NTSC system) must be set as the CORRHSE[11:0] value. No.A1647-19/37 LC74950BG 3) Offset adjustment of video output Registers related to video output offset adjustment Name ASYG the video signal and sync signals is off. The Y/G video signal can be shifted by an amount equivalent to (ASYG + 1) locks. ASCRR This register adjusts the offset for the CR/R video signal. It is used when the timing between the video signal and sync signals is off. The CR/R video signal can be shifted by an amount equivalent to (ASCRR + 1) clocks. ASCBB This register adjusts the offset for the CB/B video signal. It is used when the timing between the video signal and sync signals is off. The CB/B video signal can be shifted by an amount equivalent to (ASVBBYG + 1) clocks. ASVS This register adjusts the offset for the VSOUT video signal. It is used when the timing between the video signal and sync signals is off. The vertical sync signal can be shifted by an amount equivalent to (ASVS + 1) clocks. ASHS This register adjusts the offset for the HSOUT. It is used when the timing between the video signal and sync signals is off. The horizontal sync signal can be shifted by an amount equivalent to (ASHS + 1) clocks. 0x03 3 0x03 3 0x02 3 0x02 3 Functions This register adjusts the offset for the Y/G video signal. It is used when the timing between Sub address 0x01 bit width 3 • Offset adjustment method If the following fluctuations are present between the video outputs when ASYG[2:0] = 000b, ASCRR[2:0] = 000b and ASCBB[2:0] = 000b: CLKOUT1 CROUT7-0 YGOUT7-0 CBOUT7-0 B0 B1 B2 R0 R1 R2 G0 ... G1 G2 R1439 ... B1439 G1439 ... Then, by setting ASYG[2:0] = 010b, ASCRR[2:0] = 000b and ASCBB[2:0] = 011b, the video outputs can be aligned as shown below. The maximum shift width of the video signals is 8 clocks. If the ASVS[2:0] and ASHS[2:0] registers are used in line with the video signal shift, the sync signals (VSOUT and HSOUT) can also be shifted in line with the video signals. (DEOUT is also shifted following HSOUT.) CLKOUT1 CROUT7-0 YGOUT7-0 CBOUT7-0 R0 G0 B0 R1 G1 B1 R2 G2 B2 ... ... ... R1439 G1439 B1439 No.A1647-20/37 LC74950BG 6. ADC 1) Analog clamp Registers related to analog clamp control Name STBB Functions This register controls the band gap VREF circuit. 0: Band gap VREF circuit enters standby mode. 1: Band gap VREF circuit enters normal operating mode. * This must be set in line with the operation mode of ADC. STBB_Y STBB_B STBB_R SELFCLPSTBB_Y SELFCLPSTBB_B SELFCLPSTBB_R These registers control the AFE standby mode (Y: STBB_Y, B: STBB_B, R: STBB_R) 0: AFE standby mode 1: AFE normal operating mode * This must be set in line with the operation mode of ADC. These registers control self-clamp. (Y: SELFCLPSTBB_Y, B: SELFCLPSTBB_B, R: SELFCLPSTBB_R) 0: Self-clamp function is OFF 1: Self-clamp function is ON *1: This is disabled when STBB_x=0 (self-clamp function is OFF). *2: The clamp level is set to MAINCLPLVCNT_x[1:0]. MAINCLPLVCNT_Y MAINCLPLVCNT_B MAINCLPLVCNT_R These registers control the clamp level. (Y: MAINCLPLVCNT_Y, B: MAINCLPLVCNT_B, R: MAINCLPLVCNT_R) 00: 0.35V (sink tip clamp) 01: 0.50V (pedestal clamp) 10: 0.85V (center clamp) 11: Inhibited. *: This is enabled when the self-clamp is ON. (STBB_x=1, SELFCLPSTBB_x=1) HPFCLPON_Y HPFCLPON_B HPFCLPON_R These registers control HPF center clamp. (Y: HPFCLPON_Y, B: HPFCLPON_B, R: HPFCLPON_R) 0: HPF center clamp is OFF 1: HPF center clamp is ON *: This must be set OFF unless the center clamp is selected. (MAINCLPLVCNT_x[1:0]=10). CLPLPFON_Y CLPLPFON_B CLPLPFON_R These registers control clamp LPF. (Y: CLPLPFON_Y, B: CLPLPFON_B, R: CLPLPFON_R) 0: LPF function is OFF 1: LPF function is ON *: This is appropriate for rejecting high-frequency noises in a weak electric field (cut-off frequency is 1MHz). This must be set OFF when the video signals equivalent to HD specifications is input. 0x22 0x24 0x26 1 0x22 0x24 0x26 1 0x22 0x24 0x26 2 0x21 0x23 0x25 1 0x21 0x23 0x25 1 Sub address 0x21 bit width 1 No.A1647-21/37 LC74950BG • Analog clamp function This function performs sync tip clamping and pedestal clamping to the video input selected by AINSEL. When the analog clamp function is not used, it can be placed in the standby status using the SELFCLPSTBB_x setting. STBB_x 0 1 1 SELFCLPSTBB_x * 0 1 State Analog clamp function OFF Analog clamp function OFF Analog clamp function ON Clamping Voltage Subjected to the clamp level control • Analog clamp level control When the analog clamp function is ON, sync tip clamp, pedestal clamp and center clamp can be selected using the settings below. MAINCLPLVCNT[1:0] 00 01 10 11 Clamp Level 0.35V 0.50V 0.85V State/Use Sync tip clamp Pedestal clamp Center clamp Inhibited The clamp levels applied to the YCbCr and RGB inputs are given below. AFE CH Y B R YCbCr Sync chip clamp Center clamp Center clamp RGB Pedestal clamp Pedestal clamp Pedestal clamp No.A1647-22/37 LC74950BG • Sync tip clamp specifications Analog input 1.55V 1.35V 1.0Vp-p 0.85V (ADC-input reference) 0.65V 0.35V 0.15V 1.4Vp-p range 73 1 S/H gain setting GAIN=L 1× gain 256 Digital output ADC output code 511 439 The figures represent the set values set under ideal conditions. Clamp settings Self-clamp setting SELFCLPSTBB Main clamp level setting MAINCLPLVCNT [1:0] HPF center clamp setting HPFCLPON S/H gain setting GAIN H: Self-clamp ON 00: Main clamp level set to 0.35V L: HPF clamp OFF L: 1× gain • Center clamp specifications Analog input 1.55V 1.375V 1.20V 0.85V (ADC-input reference) 0.50V 0.325V 0.15V 64 1.4Vp-p range 1 S/H gain setting GAIN=H 1.5× gain 256 Digital output Digital output 511 448 0.7Vp-p *The figures represent the set values set under ideal conditions. Clamp settings Main clamp level setting MAINCLPLVCNT [1:0] Self-clamp setting SELFCLPSTBB HPF center clamp setting HPFCLPON S/H gain setting GAIN 10: Main clamp level set to 0.85V L: Self-clamp OFF H: HPF clamp ON H: 1.5× gain No.A1647-23/37 LC74950BG • Pedestal clamp specifications Analog input 1.55V 1.375V 1.20V 0.85V (ADC-input reference) 0.50V 0.325V 0.15V 1.4Vp-p range 64 1 0.7Vp-p S/H gain setting GAIN=H 1.5× gain Digital output Digital output 511 448 256 * The figures represent the set values set under ideal conditions. Clamp settings Self-clamp setting SELFCLPSTBB Main clamp level setting MAINCLPLVCNT [1:0] HPF center clamp setting HPFCLPON S/H gain setting GAIN H: Self-clamp ON 01: Main clamp level set to 0.50V L: HPF clamp OFF H: 1.5× gain • Clamp LPF function A primary LPF with a 1MHz cutoff frequency has been inserted in the stage before the self-clamp circuit as a measure to deal with the high-frequency noise that is present in weak electrical fields. The clamp LPF function is for minimizing shifts in the clamp levels of the self-clamp and sub-clamp when high-frequency noise components are present in the video signals. The LPF can be set to ON or OFF using the CLPLPFON setting. It must be set to ON when SD standard signals are input, and set to OFF when HD standard signals are input. The cutoff frequency of the LPF is 1MHz. Care must therefore be taken when the LPF is set to ON since the clamp level will drop when HD standard signals are input because it is not possible to track frequencies corresponding to the sync width. Sink tip clamp when LPF is off. Sink tip clamp when LPF is on. Input video signal (SD) High-frequency noise with frequencies of 1MHz and above 0.35V 0V Clamping is performed at the lower limit level of the noise components. Due to the effect of the noise, the clamp level shifts. Clamping is performed at the level at which the noise components are removed. It is clamped at its original position. No.A1647-24/37 LC74950BG 2) ADC Registers related to ADC control Name STBL_Y STBL_B STBL_R 0000: ADC standby mode 1111: ADC normal operating mode *1: Any other settings than above inhibited. *2: This must be set in line with the operating mode of ADC. ICNT_Y ICNT_B ICNT_R These registers control the internal bias current of ADC (Y: ICNT_Y, B: ICNT_B, R: ICNT_R). Bias current generating resistor values: 000: 600Ω (recommended) 001: 540Ω 010: 480Ω 011: 420Ω 100: 360Ω 101: 300Ω 110: 240Ω 111: 180Ω 0x39 0x3A 0x3B 3 Functions These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R). Sub address 0x21 0x23 0x25 bit width 4 7. Digital Clamp 1) Digital clamp pulses Registers related to digital clamp pulse control Name OSEL Functions This register sets the digital clamp pulse output to ON or OFF. It is used to adjust the position of the digital clamp pulses. 000: Normal operation 101: The Y digital clamp pulse is output from the YGOUT7 pin and the C digital clamp pulse is output from the CBOUT7 pin. DCLPYON DCLPCON DCPYSET DCPCSET DCLPYW DCLPCW DCLPYV DCLPCV These registers set the digital clamp pulse to ON and OFF (Y: DCLPYON, C: DCLPCON). 0: OFF, 1: ON These registers set the digital clamp pulse positions (Y: DCPYSET, C: DCPCSET). They are set in 4-clock increments using the trailing edge of Hsync as a reference. Setting range: -32 (00h) to +31 (3Fh), default value: +/-0 (20h) These set the digital clamp pulse width. It can be set in 1 clock increments. 0 specifies a pulse width of 0. (Y: DCLPYW, C: DCLPCW) These registers set the disable function of the digital clamp pulses during the vertical blanking period to ON or OFF. (Y: DCLPYV, C: DCLPCV) 0: OFF, 1: ON DCPYVMS DCPCVMS DCPYVME DCPCVME These specify the start line at which the digital clamp pulses are enabled within 1V. As a basic rule, the same values as the V-enable start line (VBLKS[10:0]) are set. These specify the end line at which the digital clamp pulses are enabled within 1V. As a basic rule, the same values as the V-enable end line (VBLKS[10:0]) are set. 0x0C-0x0D 0x11-0x12 0x0C-0x0E 0x11-0x13 11 11 0x0B 0x10 1 0x0B 0x10 6 0x0A 0x0F 6 0x0A 0x0F 1 Sub address 0x2E bit width 3 Digital clamp pulse settings (how to output the clamp pulses) OSEL[2:0] *1 101 YGOUT7 Digital clamp pulse (Y) CBOUT7 Digital clamp pulse (C) *1: The "000" setting must be used during normal operation. No.A1647-25/37 LC74950BG • Digital clamp pulse settings (how to establish settings in the horizontal direction) CLKOUT1 HSOUT DEOUT YGOUT7 → DCPYSET [5:0] >When 20h DCPYSET [5:0]×4-1 YGOUT7 → When DCPYSET [5:0] When < 20h DCLPYW [5:0] DCLPYW [5:0] DCPYSET [5:0]×4+1 YGOUT7 → DCPYSET [5:0] When = 20h 1clock DCLPYW [5:0] *2: The digital clamp pulse positions must be set so that they come within the horizontal blanking period (DEOUT = L). *3: The digital clamp pulse (C) setting method is the same as that described above. However, DCPCSET[5:0] (0Fh, bit5-0) must be used for the pulse position setting, and DCLPCW[5:0] (10h, bit5-0) must be used for the pulse width setting. • Digital clamp pulse settings (how to establish settings in the vertical direction) HSOUT VSOUT DEOUT YGOUT7 DCPYVMS [10:0] DCPYVME [10:0] *4: By using the digital clamp pulse disable function (Y: DCLPYV = 1, C: DCLPCV = 1), the digital clamp pulse in the vertical blanking period can be set to OFF. The same values as the vertical enable settings (VBLKS[10:0], VBLKE[10:0]) must be used for the mask period settings (DCPYVMS[10:0], DCPYVME[10:0]). *5: The digital clamp pulse (C) setting method is the same as that described above. However, DCPCVMS[10:0] and DCPVME[10:0] must be used for the mask period settings. No.A1647-26/37 LC74950BG 2) Digital clamp Registers related to digital clamp control Name SELYCRGB STDLEVY 0: YCbCr, 1: RGB YG digital clamp levels (SELYCRGB=0: Y, SELYCRGB=1: G) The 9-bit (0-511) YG video signals are clamped by the values determined assuming the pedestal levels (Y: STDLEVY[5:0] + 118, G: STDLEVY[5:0]). Setting range: Y (118-181), G (0-63) STDLEVCB CBB digital clamp levels (SELYCRGB=0: CB, SELYCRGB=1: B) The 9-bit (0-511) CBB video signals are clamped by the value determined assuming the center level (STDLEVCB[5:0] + 225) for CB and the pedestal level (STDLEVCB[5:0]) for B. Setting range: CB (225-288), B (0-63) STDLEVCR CRR digital clamp levels (SELYCRGB=0: CR, SELYCRGB=1: R) The 9-bit (0-511) CRR video signals are clamped by the value determined assuming the center level (STDLEVCR[5:0] + 225) for CR and the pedestal level (STDLEVCR[5:0]) for R. Setting range: CR (225-288), R (0-63) DCLINE FRAMEDC This sets the digital clamp update unit. 0: 1V, 1: 1H (used for testing) [When the digital clamp update unit is 1V (DCLINE=0)] This register sets the number of update frames (FRAMEDC[4:0] + 1). Setting range: 0-31 (1 to 32 frames) TCDIGCLP This register sets the digital clamp time constant. 000: 1/1 010: 1/4 100: 1/16 110: 1/64 001: 1/2 011: 1/8 101: 1/32 111: 1/128 0x17 3 0x17 5 0x15 1 0x16 6 0x15 6 0x14 6 Functions This register switches between the YCbCr input and RGB input. Sub address 0x14 bit width 1 • Digital clamp specifications The 9-bit (0-511) video signals output from the ADC are clamped at the set digital clamp pulse position to the set digital clamp level. 511 Input signal Pedestal level setting value Pedestal level Sync level Sink tip level Digital clamp pulse 0 Digital clamp pulse The digital clamp level setting values are given below. Y=118+STDLEVY[5:0] Cb/Cr=225+(STDLEVCB[5:0]/STDLEVCR[5:0]) R, G, B=STDLEVY[5:0]/STDLEVCB[5:0]/STDLEVCR[5:0] No.A1647-27/37 LC74950BG • Concerning the time constant setting A difference between the pedestal level of the 9-bit (0-511) video signals and set digital clamp level is obtained through digital clamp processing as shown in the figure below. The result of multiplying this difference by the 1/X time constant is added to the input signals and output. In this way, the level is changed gradually to the set digital clamp level. The time constant is set using TCDIGCLP[2:0]. Digital clamp level setting value Input Pedestal level detection - 1/X Output 8. Gain 1) Gain adjustments Registers related to gain adjustments Name SELYCRGB SYNCON 0: YCbCr, 1: RGB This register turns ON and OFF the function to adjust the gain by cutting off the sync component of the digitally clamped Y video signal for YCbCr input. This must be set to 0 for the RGB input (SELYCRGB=1). 0: ON, 1: OFF CNLINE This register sets the nonlinear gain adjustment to ON or OFF. 0: OFF (linear gain adjustment) 1: ON (nonlinear gain adjustment) COFFSET GAINY This register adjusts the nonlinear gain region when the nonlinear gain adjustment is ON (CNLINE=1). Linear gain adjustment (YG) The multipliers for linear gain adjustment are given below. Y (SELYCRGB=0): (32+GAINY[6:0])/64 G (SELYCRGB=1): (48+GAINY[6:0])/64 GAINCB GAINCR Linear gain adjustment (CBB) The multiplier is set to (48+GAINCB[6:0])/64 for linear gain adjustment. Linear gain adjustment (CRR) The multiplier is set to (48+GAINCR[6:0])/64 for linear gain adjustment. 0x1B 7 0x1A 7 0x19 7 0x1C 5 0x19 1 0x1B 1 Functions This register switches between YCbCr input and RGB input. Sub address 0x14 bit width 1 • Gain adjustment specifications The digitally clamped 9-bit video signals are converted into 8-bit video signals as shown in the figure below. In this case, the digital clamp level is shifted to the LSB of the 8 bits, and gain is adjusted in such a way that the components (video signals) above the digital clamp level fit in the 8-bit range. 9 bits 8 bits No.A1647-28/37 LC74950BG • Non-linear gain adjustment When CNLINE = 1, the output obtained in response to the input near the saturation region is made non-linear. When the non-linear gain adjustment parameter (CONPARA), obtained from the formula below, is less than the multiplier (RGB: (32 + GAIN_x[6:0])/64, YCbCr: (48 + 12A_GAIN_x[6:0])/64) that is used when the non-linear gain is adjusted, the input is multiplied by the non-linear gain adjustment parameter, resulting in a non-linear output. The non-linear start position and maximum non-linear output value can be adjusted using COFFSET[4:0]. CONPARA = (1023 − 9-bit video signals) × (64 + COFFSET[4:0])/64 The figure below shows the gain adjustment output when the input is Y and GAIN_Y[6:0] = 63. GAIN_Y=63 (AMP=1.73) 1200 1000 800 OUTPUT(LSB) 600 400 200 INPUT CNLINE=0 CNLINE=1, COFFSET=0 CNLINE=1, COFFSET=4 CNLINE=1, COFFSET=8 CNLINE=1, COFFSET=12 CNLINE=1, COFFSET=15 CNLINE=1, COFFSET=20 0 0 200 400 600 INPUT(LSB) 800 1000 1200 2) DC level adjustment Registers related to DC level adjustment Name SELYCRGB BRADJ 0: YCbCr, 1: RGB This register adjusts the DC level. When the gain adjustment + DC level adjustment output is linear (BNLINE = 0), BRADJ is offset from the video signals produced after the gain adjustment (the Y signal is further offset by 64). Setting range: -64 to +63, default value: ±0 (40h) CNLINE This register sets the applicable non-linear gain adjustment, when the gain adjustment + DC level adjustment is used (BRADJ40h), to ON or OFF. 0: OFF (linear gain adjustment) 1: ON (nonlinear gain adjustment) COFFSET This register adjusts the non-linear gain region when the non-linear gain adjustment is ON (BNLINE = 1) 0x1C 5 0x1A 1 0x19 1 0x1D 7 Functions This register switches between the YCbCr input and RGB input. Sub address 0x14 bit width 1 No.A1647-29/37 LC74950BG • DC level adjustment specifications Input signal AMP Output signal Gain adjustment Digital clamp level DC level adjustment value The DC level is adjusted by adding BRADJ[6:0] to the Y signal or RGB signals subjected to gain adjustment processing. • Non-linear gain adjustment + DC level adjustment When CNLINE = 1 and BRADJ[6:0]0x40 (plus), the output corresponding to the input near the saturation region is made non-linear. When the DC adjustment parameter (BRPARA), obtained from the formula below, is less than BRADJ[6:0], the extent to which the output is to be non-linear is adjusted by adding the DC adjustment parameter to the Y signal or RGB signals subjected to non-linear gain adjustment processing. BRPARA = (127 − non-linear gain output/16) × (64 + COFFSET[4:0])/64 The figure below shows the output obtained when the gain adjustment and DC level adjustment have been performed (when GAIN_Y[6:0] = 63, COFFSET[4:0] = 8). GAIN_Y=63 (AMP=1.73) 1200 1000 800 OUTPUT(LSB) 600 INPUT CNLINE=0 400 CNLINE=0, BNLINE=1, BRADJ=64 CNLINE=0, BNLINE=1, BRADJ=0 CNLINE=0, BNLINE=1, BRADJ=127 0 0 200 400 600 INPUT(LSB) 800 1000 1200 200 No.A1647-30/37 LC74950BG 9. External interface I2C: 100kHz mode is supported. The slave address can be selected using the pin settings. Slave address: 0x98, 0x9A 1) Control specifications Slave operations in the standard mode (100kHz) are supported. These must be used for setting the internal registers and setting the internal status output and γ correction characteristics. The slave addresses are listed in the table below. Two addresses can be selected using the I2CSEL pin. Slave address: Slave address: (I2CSEL=0) (I2CSEL=1) 1 1 0 0 0 0 1 1 1 1 0 0 0 1 R/W R/W 2) Control and timing specifications (1) Receive mode As shown below, the slave address W, sub-address and input data must be set in this sequence after the start condition. The data of each sub-address can be input in auto address increments consecutively from the data of the sub-address specified. The data must be set consecutively with ACK between one data and the next. The stop condition must be set last. SDA Slave address W ACK Sub-address ACK Input data ACK SCL 1 8 9 tH_S tH_D tS_D tR tF tHI tLO tS_P Parameter SCL clock frequency Start condition hold time Data hold time Data setup time SDA and SCL rise time SDA and SCL fall time SCL high level hold time SCL low level hold time Stop condition setup time Symbol fSCL tH_S tH_D tS_D tR tF tHI tLO tS_P min 0 4.0 0 250 max 100 unit kHz μs μs ns 1000 300 ns ns μs μs μs 4.0 4.7 4.7 No.A1647-31/37 LC74950BG (2) Send mode As shown below, slave address W and the sub-address must be set after the start condition. The stop condition must be set last. SDA Slave address W ACK Sub-address ACK SCL Slave address R must then be set after the start condition. The data of each sub-address is output in auto address increments consecutively from the data of the specified sub-address. The stop condition must be set last. SDA Slave address R ACK Input data ACK Input data ACK SCL (3) Register settings The registers can be broadly divided into receive and send registers. Receive registers are setting registers for internal control; send registers are for outputting the internal statuses to an external destination. The receive register settings can also be output to an external destination. No.A1647-32/37 LC74950BG 3) Register map Sub Address bit7 (MSB) bit6 bit5 bit4 Clock I/O control 00H R/W CLKOUT2INV CLKOUT1INV CLKHSYIINV CLKINININV CLKADCIINV CLKSEL[2:0] 08h bit3 bit2 bit1 bit0 (LSB) Initial Value Synchronous I/O control/offset adjustment control 01H 02H 03H R/W R/W R/W CLKOUTINV VSOUTINV HOUTINV ASCRR[2:0] ASVS[2:0] HSPLLSEL VSINV HSINV H/V enable control 04H 05H 06H 07H 08H 09H R/W R/W R/W R/W R/W R/W VBLKS[10: 8] VBLKS[7:0] VBLKE[7:0] Digital clamp 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SELYCRGB DCLINE EXSYNCON TCDIGCLP[2:0] Sub-contrast/brightness 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H R/W R/W R/W R/W R/W R/W R/W R/W CNLINE BNLINE SYNCON AFE/ADC 21H 22H 23H 24H 25H 26H R/W R/W R/W R/W R/W R/W STBB AINSEL SELFCLPSTBB_Y STBB_Y STBL_Y[3:0] HPFCLPON_Y CLPLPFON_Y GAIN_Y BFh 12h 3Fh GAIN_B 12h 3Fh GAIN_R 12h BRADJ[6:0] GAINY[6:0] GAINCB[6:0] GAINCR[6:0] COFFSET[4:0] 20h 20h 20h 08h 40h 40h 00h 00h DCLPCON DCLPCV DCPCVMS[10: 8] DCPCVMS[7:0] DCPCVME[7:0] STDLEVY[5:0] STDLEVCB[5:0] STDLEVCR[5:0] FRAMEDC[4:0] DCLPYON DCLPYV DIGCLPON DCPYVMS[10: 8] DCPYVMS[7:0] DCPYVME[7:0] DCPCSET[5:0] DCLPCW[5:0] DCPCVME[10: 8] DCPYSET[5:0] DCLPYW[5:0] DCPYVME[10: 8] A7h C4h 01h 11h 02h A7h 84h 01h 11h 02h A0h 20h 20h 40h 20h HBLKS[11: 8] HBLKS[7:0] HBLKE[7:0] VBLKE[10: 8] HBLKE[11: 8] 03h 7Ah 4Ah 01h 11h 02h ASYG[2:0] ASCBB[2:0] ASHS[2:0] 88h 08h 08h MAINCLPLVCNT_Y[1:0] SELFCLPSTBB_B STBB_B STBL_B[3:0] HPFCLPON_B CLPLPFON_B MAINCLPLVCNT_B[1:0] SELFCLPSTBB_R STBB_R STBL_R[3:0] HPFCLPON_R CLPLPFON_R MAINCLPLVCNT_R[1:0] Continued on next page. No.A1647-33/37 LC74950BG Continued from preceding page. Sub Address bit7 (MSB) bit6 bit5 bit4 PLL 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W PLL and others 40H FEH R/W R/W CLKINDIV[5:0] 1Fh 80h ICNT_Y[2:0] ICNT_B[2:0] ICNT_R[2:0] OSEL[2:0] CORREN HPLDIV15 HPLDIV7 HPLDIV14 HPLDIV6 HPLDIV13 HPLDIV5 HPLDIV12 HPLDIV4 PLLGAIN[2:0] HPLDIV11 HPLDIV3 HPLDIV10 HPLDIV2 PLLCTL2 HPLDIV9 HPLDIV1 PLLCTL1 HPLDIV8 HPLDIV0 C0h 73h 58h AAh 02h 35h 1Ch 01h 06h 00h 80h 08h 20h 00h 00h 00h 01h 00h 0Ch 0Ch 0Ch 00h 00h 00h 92h bit3 bit2 bit1 bit0 (LSB) Initial Value CPIS_COAST[3:0] CORRHSS[11: 8] CORRHSS[7:0] CORRHSE[7:0] - CPIS_ORG[3:0] CORRHSE[11: 8] No.A1647-34/37 LC74950BG PDOWN Complete power-down can be controlled using the PDWN pin. ADC, PLL and other items can be powered down individually by means of register settings. This makes it possible to limit the power consumption as required. Internal states based on the PDWN pin setting PDWN 0 1 ADC PowerDown Operating PLL PowerDown Operating Logic Clocks stopped Operating Communication Stopped Operating Remarks Registers reset state Power Down control by controlling registers Item ADC PLL Logic Output pin Communication Power-down can be controlled using dedicated registers. See below for the relevant registers. Power-down can be controlled using dedicated registers. See below for the relevant registers. External input is selected and the external clock is stopped. Similarly, the clock is stopped by selecting the PLL mode and power down the PLL circuit. Output-enable (Hi-Z) can be set by using the dedicated registers. Cannot be stopped. Name STBL_Y STBL_B STBL_R 0000: ADC standby mode 1111: ADC normal operating mode Functions These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R). Sub address 0x21 0x23 0x25 bit width 4 *1: Any other setting than above inhibited. *2: These must be set in accordance with the operating mode of AEC. STBB This register controls the band gap VREF circuit. 0: Places the band gap VREF circuit into the standby mode. 1: Places the band gap VREF circuit into the normal operating mode. *: This must be set in accordance with the operating mode of ADC. STBB_Y STBB_B STBB_R PLLCTL2 These registers control the AFE standby mode (Y: STBB_Y, B: STBB_B, R: STBB_R). 0: AFE standby mode 1: AFE normal operating mode *: These must be set in accordance with the operating mode of ADC. This register controls the H-lock PLL power down mode 0: Normal operating mode 1: H-lock PLL power off 0x27 1 0x21 0x23 0x25 1 0x21 1 No.A1647-35/37 LC74950BG Other (usage precautions) 1. Precaution when turning on the power As shown in the figure below, start the transfer of the I2C bus command after factoring in the power-on time (A), PDWN operation time (B), RESET operation time (C) and command transfer start time (D). DVDD33 AVDD33 DVDD15 AVDD15 3.0V 1.35V 2V PDWN 0.2VDD 2V 0.2VDD RESET Command 0.75VDD A B C D A: Power-on time This is the time taken from power-on to when the *VDD15 operating supply voltage has reached the lowest level (1.35V) and operation has stabilized. The power-on-time depends on the characteristics of the power ICs and other components, so it must be checked separately. With regard to *VDD33 and *VDD15, *VDD15 must be turned on after *VDD33 has turned on. B: PDWN operation time This is the time during which the "L" level must be applied continuously for a period of 10ms or more to the PDWN pin after the lowest level (1.35V) of the *VDD15 operating supply voltage has been reached and operation has stabilized. C: RESET operation time This is the time during which the "L" level must be applied continuously for a period of 10ms or more to the RESET pin after the PDWN is released ("H" level). D: Command transfer start time At least an interval of 10ms is required from the time the RESET pin is released ("H" level) to the start of command transfer. No.A1647-36/37 LC74950BG 2. Precaution when turning off the power DVDD33 AVDD33 3.0V DVDD15 AVDD15 1.35V A As a basic rule, power-off must be performed in the reverse sequence of power-on. However, no problems are posed if there is no wait time. A: Power-off time This is the time it takes to reach the IO supply voltage and for operation to stabilize from the lowest level (1.35V) of the *VDD15 operating supply voltage. With regard to *VDD33 and *VDD15, *VDD33 must be turned off after *VDD15 has been turned off or they must be turned off at the same time. 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of March, 2010. Specifications and information herein are subject to change without notice. PS No.A1647-37/37