LC7537AN

Ordering number : EN2169C CMOS LSI LC7537, 7537AN, 7537NE Electronic Volume Control System for Audio Equipment Overview The LC7537N is an electronic control LSI capable of electronically controlling the volume, balance, loudness, fader, bass, and treble functions individually with fewer externally connected component parts. Package Dimensions unit : mm 3025B-DIP42S [LC7573N] Features • Enables controlling the below-listed functions with 3line serial data, including CE, DI, and CLK. Also, due to 0 V to 5 V swing of the serial data input voltage, permits the use of a general purpose microcomputer. Volume : Separately controls the Lch and Rch volume levels across 81 positions over the 0 dB to –79 dB (in 1 dB steps) range and –∞, and consequently also serves balance control purposes. Loudness : By virtue of a center tap provided at the –20 dB position of the volume controlling ladder resistors, permits loudness to be controlled with externally connected CR components. Fader : By varying only the rear or front output level across 16 positions, provides fader functions (in 2 dB steps over the 0 dB to –20 dB range, and 5 dB steps over the –20 dB to –45 dB range, and at –∞, for a total of 16 positions). Bass/Treble : With CR components externally connected, forms an NF type tone control circuit (Baxandall type) to exercise control across 15 positions over both the bass and treble functions in 2 dB steps. • By virtue of its CMOS structure, the LSI operates under a broad power supply voltage range from +4.5 V to +15 V, permitting the use of either a single or a dual ± power supply, whichever is preferred. SANYO: DIP42S unit : mm 3156-QFP48E [LC7537NE] SANYO: QIP48E unit : mm 3052A-QFP48A [LC7537AN] SANYO: QIP48A SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 81096HA(OT)/31293JN/7018YT/6186KI,TS No. 2169-1/11 LC7537N, 7537AN, 7537NE Pin Assignments Equivalent Circuit Block Diagram Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V, VDD = ≥ VCC > VSS ≥ VEE Item Maximum supply voltage Symbol VDD – VEE max VCC max VI1 VI2 Pd max Topr Tstg *3 Condition VDD, VEE : VEE ≥ –8 V VCC : VDD ≥ VCC DI, CLK, CE INIT Ta ≤ 85˚C, (LC7537N, 7537AN) Ta ≤ 85˚C, (LC7537NE) 16 VSS – 0.3 to VSS + 7 VSS – 0.3 to VDD + 0.3 VSS – 0.3 to VDD + 0.3 200 300 –40 to +85 –50 to +125 Rating Unit V V V V mW mW ˚C ˚C Input supply voltage Allowable power dissipation Operating temperature Storage temperature Allowable Operating Conditions at Ta = 25°C, VSS = 0 V, VDD = ≥ VCC > VSS ≥ VEE Item Supply voltage *1 Input high–level voltage Symbol VDD – VEE VCC VIH1 *2 VIH2 VIL1 *2 VIL2 VIN tøW tset up thold fopg DI, CLK, CE INIT DI, CLK, CE INIT VEE ≥ –7.5 V Condition 4.5 to 15 4.5 to 5.5 0.8 VCC to VCC 0.8 (VDD – VEE) + VEE to VDD VSS to 0.2 VCC VEE to 0.2 (VDD – VEE) + VEE VEE to VDD 1 min 1 min 1 min up to 330 Rating Unit V V V V V V VP-P µs µs µs kHz Input low–level voltage Input signal amplitude Input pulse width setup time Hold time Operating frequency Note: 1. A1000 pF or larger capacitor should be added on between each individual power supply terminal and VSS. 2. When the microcomputer side control signals rise faster than VDD for the LC7537, a 2 kΩ or higher resistor should be inserted midway on each of the DI, CLK, and CE lines. 3. When mounting the QIP package on the board, do not dip the entire package in solder. Only the LC7537NE may be dipped directly in solder during mounting. No. 2169-2/11 LC7537N, 7537AN, 7537NE Electrical Characteristics at Ta = 25°C, VDD =+7.5 V, VEE =–7.5 V, VCC =+5 V Item Total harmonic Distortion Crosstalk Maximum attenuation output Symbol THD(1) THD(2) CT Vomin(1) Vomin(2) RVOL(1) RVOL(2) VR resistance voltage RBASS RTREBLE RFADER Output noise VN(1) VN(2) IDD ICC All flat overall (IHF-A) Rg = 1 kΩ Rg = 1 kΩ, VDD = 8 V, VEE = VSS = 0 V VDD – VEE = 15 V VCC = 5 V Condition VIN = 1 V, f = 1kHz, all flat overall VIN = 1 V, f = 20 kHZ, all flat overall VIN = 1 V, f = 1 kHz, all flat, Rg = 1 kΩ VIN = 1 V, f = 1 kHz, MAIN, VR = ∞, FADER VR = ∞ VIN = 1 V, f = 1 kHz, MAIN, VR = ∞, VDD = 8 V, FADER VR = ∞, VEE = VSS = 0 V, C between VSS and GND of L/R = 1000 µF 5 dB-step 1 dB-step 0.006 60 80 70 12 12 12 12 12 Rating min typ 0.005 0.02 95 90 80 20 20 20 20 20 2 2 28 28 28 28 28 10 10 1 1 dB dB kΩ kΩ kΩ kΩ kΩ µV µV mA mA max 0.01 % dB Unit % Current drain Pin Description ( Pin No. 12(8) 31(29) 9(4) 34(33) 10(5) 33(32) 11(6) 32(31) 5(47) 38(38) 4(46) 3(45) 39(39) 40(40) 15(11) 16(9) 14(10) 28(26) 27(28) 29(27) 17(13) 16(12) 18(14) 26(24) 27(25) 25(23) 7(1) 6(48) 36(36) 37(37) Symbol L.IN R.IN L.C1 R.C1 L.C2 R.C2 L.OUT R.OUT L.FIN R.FIN L.FOUT L.ROUT R.ROUT R.ROUT L.B1 L.B2 L.B3 R.B1 R.B2 R.B3 L.T1 L.T2 L.T3 R.T1 R.T2 R.T3 LCT1 LCT2 RCT1 RCT2 ) : LC7537AN, 7537NE Description of Functions Main volume control block 5 dB-step attenuator input terminals. These pins should be driven at a low impedance. Main volume control block 5 dB-step attenuator output terminals. Having been designed to be open, the step positions will develop errors if at low acceptor impedances, so that as high load impedances as possible should be provided. Main volume control block 1 dB-step attenuator input terminals. Theses pins should be driven at alow impedance. Main volume control block 1 dB-step attenuator output terminals. Due to the step positions designed to be open, load impedances as high as possible should be provided to them, similar to those for the LC1 and RC1. Fader functions employing mode input terminals. These pins should be driven at a low impedance. Fader block output terminals. These pins permit the front and rear sides to be faded out independently of each other. Attenuations exercised on Lch will be the same as on Rch. Due to the step positions designed to be open, acceptor impedances as high as possible should be provided to them. VR resistance : 20 kΩ VR resistance : 20 kΩ Remarks VR resistance : 20 kΩ Bass tone control block terminals. A total of 15 positions have been provided in 2 dB steps VR resistance : 20 kΩ Treble tone control block terminals. A total of 15 positions have been provided in 2 dB steps. The VR resistance value is 20 kΩ. VR resistance : 20 kΩ Loudness dedicated terminals. A high-frequency-range correcting C should be put between CT1 and IN, and low-frequency-range correcting C between CT2 and L–V SS (R–VSS). Continued on next page. No. 5190-3/10 LC7537N, 7537AN, 7537NE Continued from preceding page. Pin No. Symbol Description of Functions Remarks 8(2) L-VSS 35(35) R-VSS Main volume control block fader control common terminals. The impedance of pattern connected to these pins should be as low as possible. Since L–VSS (R–VSS) and VSS have not been connected inside the LSI, they should be connected together on the outside in conformance with their individual specifications. Particular attenuation should be paid to the capacitance assigned to the capacitors put between L–VSS (R–VSS) and VSS, which will emerge as a residual resistive component when control is turned down for maximum attenuation. Intra-IC latch resetting terminal 42(42) INIT Control-setting data at the internal latch will be indeterminate when power has just been switched on, so that by engaging the “L” level of this pin at power-on, the fader control may be set at its –∞ position and muting behaviour is engaged (Note: VDD to VEE Level). Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch, activating the various analog switches. When the “H” level is then restored, transfer of the data will be enabled. 22(20) CE 20(16) DI Input terminals for serial data and clock that serve control purposes. 21(17) 1(43) 23(21) 19(15) 24(22) 2(3, 7) 41(18, 30, 34, 41, 44) (19) CLK VDD VCC VSS VEE NC No connect pins. Absolutely nothing should be connected here. These pins are connected to the relevant power supplies. Exercise caution against VCC rising earlier than VDD. VDD(NC) VDD subterminal. Connected to VDD or left open. LC7537AN and LC7537NE only No. 2169-4/11 LC7537N, 7537AN, 7537NE Control Timing Data Format No. 2169-5/11 LC7537N, 7537AN, 7537NE Main Volume Control Block Equivalent Circuit Fader Volume Control Block Equivalent Circuit Tone Control Block Equivalent Circuit No. 2169-6/11 LC7537N, 7537AN, 7537NE Sample Application Circuits Single Power Supply Unit (resistance: Ω, capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated. No. 2169-7/11 LC7537N, 7537AN, 7537NE Dual ± Power Supply Unit (resistance: Ω, capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated. No. 2169-8/11 LC7537N, 7537AN, 7537NE Single Power Supply Unit (resistance: Ω, capacitance: F) Note: Bipolar electrolytic capacitors should preferably be employed where no polarity has been indicated. No. 2169-9/11 LC7537N, 7537AN, 7537NE Caution for Pattern Designing • Space the patterns between L.IN and L.OUT and those between R.IN and R.OUT as far apart as possible. When forced to design them close together, provide shielding patterns between as illustrated. They will be effective at the maximum attenuated level (with 10 kHz and higher frequencies). (DIP42S) • Make the L–VSS and R–VSS as broad as possible. Unit (resistance: Ω, capacitance: F) No. 2169-10/11 LC7537N, 7537AN, 7537NE s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. T his catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 2169-11/11