LC78632

Ordering number : EN*5826 CMOS LSI LC78632RE Compact Disk Player DSP Preliminary Overview The LC78632RE is a compact disc D/A signal-processing LSI for Video-CD players that provides a variable clock error correction (VCEC) mode. The LC78632RE demodulates the EFM signal from the optical pickup and performs de-interleaving, error detection, error correction, digital filtering, and other processing. The LC78632RE includes an on-chip 1-bit D/A converter, and executes commands sent from a control microprocessor. Package Dimensions unit: mm 3174-QFP80E [LC78632RE] Features • VCEC support • Built-in PLL circuit for EFM detection (supports 4× playback) • 18KB RAM on chip • Error detection and correction (corrects two errors in C1 and four errors in C2) • Frame jitter margin: ±8 frames • Frame synchronization signal detection, protection, and insertion • Dual interpolation adopted in the interpolation circuit. • EFM data demodulation • Subcode demodulation • Zero-cross muting adopted • Servo command interface • 2fs digital filter • Digital de-emphasis • Built-in independent left- and right-channel digital attenuators (239 attenuation steps) • Supports the bilingual function • Left/right swap function • Built-in 1-bit D/A converter (third-order ∆ ∑ noise shaper, PWM output) • Built-in digital output circuit • CLV servo • Arbitrary track jumping (of up to 255 tracks) • Variable sled voltage (four levels) • Six extended I/O ports and 2 extended output ports • Built-in oscillator circuit using an external 16.9344 MHz or 33.8688 MHz (for 4× playback) element • Supply voltage: 4.5 to 5.5 V SANYO: QFP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D3097HA (OT) No. 5826-1/9 LC78632RE Equivalent Circuit Block Diagram No. 5826-2/9 LC78632RE Pin Assignment LC78632RE Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 470 –30 to +75 –40 to +125 Unit V V V mW °C °C Allowable Operating Ranges at Ta = 25°C, VSS = 0 V Parameter Supply voltage Symbol VDD VIH1 VIH2 VIL1 VIL2 Data setup time Data hold time tSU tPRS tHD Conditions VDD, AVDD, XVDD, LVDD, RVDD TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI EFMI TEST1 to TEST5, TAI, HFL, TES, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, SBCK, RWC, COIN, CQCK, RES, CS, XIN, DEFI EFMI COIN, RWC: Figures 1 and 4 RWC: Figure 4 COIN, RWC: Figures 1 and 4 min 4.5 0.7 VDD 0.6 VDD 0 0 400 100 400 typ 5.0 max 5.5 VDD VDD 0.3 VDD 0.4 VDD Unit V V V V V ns ns ns Input high-level voltage Input low-level voltage Continued on next page. No. 5826-3/9 LC78632RE Continued from preceding page. Parameter High-level clock pulse width Low-level clock pulse width Data read access time Command transfer time Subcode Q read enable time Subcode read cycle Subcode read enable Port output delay time Input level Symbol tWH tWL tRAC tRWC tSQE tSC tSE tPD VEI VXI Conditions SBCK, CQCK: Figures 1, 2, 3, and 4 SBCK, CQCK: Figures 1, 2, 3, and 4 SQOUT, PW: Figures 2, 3, and 4 RWC: Figures 1 and 4 WRQ: Figure 2, with no RWC signal SFSY: Figure 3 SFSY: Figure 3 CONT1, CONT2, P0 to P5: Figure 5 EFMI XIN: Capacitance coupled input 1.0 1.0 400 1200 min 400 400 0 1000 11.2 136 400 typ max Unit ns ns ns ns ms µs ns ns Vp-p Vp-p Note: Due to the structure of this IC, the identical voltage must be applied to all power-supply pins. Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter Current drain Input high-level current Symbol IDD IIH1 IIH2 Input low-level current IIL VOH1 Conditions Normal-speed playback EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, DEFI: VIN = 5 V TAI, TEST1 to TEST5, CS: VIN = 5 V TAI, EFMI, HFL, TES, SBCK, RWC, COIN, CQCK, RES, TEST1 to TEST5, CS, DEFI: VIN = 0 V EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX IOH = –1 mA MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOH = –0.5 mA VPDO: IOH = –1 mA DOUT: IOH = –12 mA LCHP, RCHP, LCHN, RCHN: IOH = –1 mA EFMO, CLV+, CLV–, V/P, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–, EMPH, EFLG, FSX IOL = 1 mA MUTEL, MUTER, LRCKO, DFLRO, DACKO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, 16M, 4.2M, CONT1, CONT2: IOL = 2 mA VPDO: IOL = 1 mA DOUT: IOL = 12 mA LCHP, RCHP, LCHN, RCHN: IOL = 1 mA PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 5 V PDO1, PDO2, VPDO, P0/DFCK, P1/DFIN, P2, P3/DFLR, P4, P5: VOUT = 0 V PDO1, PDO2: RISET = 68 kΩ PDO1, PDO2: RISET = 68 kΩ –5 –96 64 1.0 2.25 3.5 4.75 –80 80 1.25 2.5 3.75 –64 96 1.5 2.75 4.0 0.5 25 –5 min typ 30 5 75 max Unit mA µA µA µA 4 V Output high-level voltage VOH2 VOH3 VOH4 VOH5 VOL1 4 V 4.5 4.5 3.0 4.5 1 V V V V Output low-level voltage VOL2 VOL3 VOL4 VOL5 IOFF1 0.4 V 0.5 0.5 2.0 5 V V V µA µA µA µA V V V V Output off leakage current IOFF2 Charge pump output current IPDOH IPDOL VSLD1 Sled output voltage VSLD2 VSLD3 VSLD4 No. 5826-4/9 LC78632RE D/A Converter Analog Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V Parameter Total harmonic distortion Dynamic range Signal-to-noise ratio Crosstalk Symbol THD + N DR S/N CT Conditions LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) LCHP, LCHN, RCHP, RCHN; 1 kHz: –60 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using the 20-kHz low-pass filter (A filter (AD725D built in)) LCHP, LCHN, RCHP, RCHN; 1 kHz: 0 dB input, using a 20-kHz low-pass filter (AD725D built in) 98 96 min typ 0.006 90 100 98 max Unit % dB dB dB Note: Measured in normal-speed playback mode in a Sanyo 1-bit D/A converter block reference circuit, with the digital attenuator set to EE (hexadecimal). Figure 1 Command Input Figure 2 Subcode Q Output Figure 3 Subcode Output No. 5826-5/9 LC78632RE Figure 4 General-Purpose Port Read Figure 5 General-Purpose Port Output No. 5826-6/9 LC78632RE One-Bit D/A Converter Output Block Reference Circuit LC78632RE No. 5826-7/9 LC78632RE Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Symbol VPDO PDO2 PDO1 AVSS FR AVDD ISET TAI EFMO VSS EFMI TEST1 CLV+ CLV– V/P TEST2 TEST3 P4 HFL TES PCK FSEQ TOFF TGL THLD TEST4 VDD JP+ JP– SLD+ SLD– EMPH P5 LRCKO DFLRO DACKO CONT1 P0/DFCK P1/DFIN P2 P3/DFLR LRSY CK2 ROMXA C2F MUTEL LVDD LCHP LCHN O O One-bit D/A converter pins O O O O O I/O O O O O I/O I/O I/O I/O O O O O O ROMXA pins Output port I/O port. DF bit clock input in antishock mode. I/O port. DF data input in antishock mode. I/O port. Used as the de-emphasis filter on/off switching pin in antishock mode. The de-emphasis filter is turned on when this pin is high. I/O port output or digital filter LR clock input (when anti-shock mode) LR clock output Bit clock output. The polarity can be inverted with the CK2CON command. Interpolated data output. Data that has not been interpolated can be output by issuing the ROMXA command. C2 flag output Left channel mute output Left channel power supply Left channel P output Left channel N output Digital filter outputs Sled output. This pin can be set to 1 of 4 levels by commands sent from the system control microprocessor. De-emphasis monitor. A high level indicates that a disk requiring de-emphasis is being played. I/O port LR clock output LR data output. The digital filter can be turned off with the DFOFF command. Bit clock output I I O O O I I I/O I I O O O O O I I O I/O O O O Test output Double-speed and quad-speed mode playback PLL charge pump output. Must be left open if unused. Normal-speed mode playback PLL charge pump output Analog system ground. Must be connected to 0 V. Built-in VCO frequency range setting resistor connection Analog system power supply PDO1 and PDO2 output current setting resistor connection Test input. A pull-down resistor is built in. Must be connected to 0 V. EFM signal output Digital system ground. Must be connected to 0 V. EFM signal input Test input. A pull-down resistor is built in. Must be connected to 0 V. Spindle servo control output. CLV+ outputs a high level for acceleration, and CLV– outputs a high level for deceleration. Rough servo/phase control automatic switching monitor output. A high-level output indicates rough servo, and a low-level output indicates phase control. Test input. A pull-down resistor is built in. Must be connected to 0 V. Test input. A pull-down resistor is built in. Must be connected to 0 V. I/O port Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phase is locked in normal-speed mode playback. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal matches the internally generated synchronization signal. Tracking off output Tracking gain switching output. Increase the gain when this pin outputs a low level. Tracking hold output Test input. A pull-down resistor is built in. Must be connected to 0 V. Digital system power supply Track jump output. JP+ outputs a high level both for acceleration during outward direction jumps and for deceleration during inward direction jumps. JP– outputs a high level both for acceleration during inward direction jumps and for deceleration during outward direction jumps. Function 50 LVSS Left channel ground. Must be connected to 0V. Note: Of the general-purpose I/O ports, any unused input ports must be connected to 0 V, or set to be output ports. Continued on next page. No. 5826-8/9 LC78632RE Continued from preceding page. Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Symbol XVSS XOUT XIN XVDD RVSS RCHN RCHP RVDD MUTER SBSY EFLG PW SFSY SBCK DOUT FSX WRQ RWC SQOUT COIN CQCK RES TESTF CONT2 16M 4.2M TEST5 CS DEFI O O O O O I O O O I O I I I O O O O I I I O O One-bit D/A converter pins O I I/O Crystal oscillator ground. Must be connected to 0 V. 16.9344 MHz crystal oscillator connections. Use a 33.8688 MHz crystal oscillator for quad-speed playback. Crystal oscillator power supply Right channel ground. Must be connected to 0 V. Right channel N output Right channel P output Right channel power supply Right channel mute output Subcode block synchronization signal output C1 and C2 error correction state monitor Subcode P, Q, R, S, T, U, V, and W output Subcode frame synchronization signal output. Falls when the subcode output goes to the standby state. Subcode readout clock input. This is a Schmitt input. This pin must be connected to 0 V if unused. Digital output Outputs a 7.35 kHz synchronization signal generated by dividing the crystal oscillator frequency. Subcode Q output standby output Read/write control input Subcode Q output Input for commands from the control microprocessor Command input acquisition clock. Also used as the SQOUT subcode readout clock input. This is a Schmitt input. Chip reset input. This pin must be set low temporarily when power is first applied. Test output Output port 16.9344 MHz output 4.2336 MHz output Test input. A pull-down resistor is built in. Must be connected to 0 V. Chip select input. A pull-down resistor is built in. When control is not used, this pin must be connected to 0 V. Defect detection signal input. Must be connected to 0 V if unused. Function 80 VCOC I Test input. Must be connected to 0 V. Note: Of the general-purpose I/O ports, any unused input ports must be connected to 0 V, or set to be output ports. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of December, 1997. Specifications and information herein are subject to change without notice. No. 5826-9/9