LC79400D

Ordering number : EN4346B CMOS LSI LC79400D Dot Matrix LCD Driver Overview The LC79400D is a large-scale dot matrix LCD segment driver LSI. Display data transferred from the controller (4-bit parallel format) is processed through 80-bit latching and a LCD drive signal is generated. The LC79400D can be used in conjunction with common driver LC7943D (QIP80D) as well as LC79430D (QIP100D) and LC79431D (QIP100D) to drive a widescreen LCD panel. Package Dimensions unit : mm 3180-QFP100D [LC73701M] Features • On-chip LCD drive circuit (80 bits) • Display duty selection ranging from 1/64 to 1/256 • Supports use of chip disable pin for lower large panel power supply dissipation • Supports externally supplied bias voltage • Operating power supply voltage/operating temperature include VDD (logic block) VDD-VEE (LCD block) : 5 V ±10 % / –20 to +75 °C : 12 V to 32 V / –20 to +75°C SANYO: MFP18 • Data transfer clock provides maximum 3.0 MHz and supports bidirectional shift • 4-bit parallel data input • CMOS process • 100-pin flat plastic package Specifications Absolute Maximum Ratings at Ta = 25±2°C, VSS = 0 V Parameter Maximum supply voltage (logic) Maximum supply voltage (LCD) Maximum input voltage Storage temperature range Symbol VDD max VDD - VEE max*1 VI max Tstg Conditions Ratings –0.3 to +7.0 0 to 35 –0.3 to VDD + 0.3 –40 to +125 Unit V V V °C Note:1. The voltages V1, V3, V4, V7, VDD and VEE must obey the relationships: VDD ≥ V1 > V3 > V4 > VEE, VDD – V3 ≤ 7V, V4 – VEE ≤ 7V. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 73096HA (OT)/21593JN A8-9571 No. 4346-1/8 LC79400D Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V Parameter Supply voltage (logic) Supply voltage (LCD) Input high-level voltage Symbol VDD VDD - VEE VIH VIL fCP fWC tWL tSETUP tHOLD tCL1 tCL2 tLC tR Rise/Fall time tF tRL tFL *2, *3 DI1 to 4, CP, LOAD, CDR, CDL R/L, M, DISP OFF DI1 to 4, CP, LOAD, CDR, CDL R/L, M, DISP OFF CP CP LOAD DI1 to 4 → CP DI1 to 4 → CP CP → LOAD CP → LOAD LOAD → CP CP CP LOAD LOAD 100 100 80 80 0 100 63 50 50 50 50 Conditions min 4.5 12 0.8 VDD 0.2 VDD 3.0 typ max 5.5 32 Unit V V V Input low-level voltage CP (shift clock) CP (pulse width) LOAD pulse width Setup time Hold time CP → LOAD LOAD → CP V MHz ns ns ns ns ns ns ns ns ns ns ns Note:2. The voltages V1, V3, V4, V7, VDD and VEE must obey the relationships: VDD ≥ V1 > V3 > V4 > VEE, VDD – V3 ≤ 7V, V4 – VEE ≤ 7V. 3. When applying power, apply power to the LCD drive block after applying power to the logic block or apply power to both the blocks simultaneously. When turning off power, turn off power to the logic block after turning off power to the LCD drive block or turn off power to both the blocks simultaneously. Electrical Characteristics at Ta = 25±2°C, VSS = 0 V, VDD = 5 V±10% Parameter Input high-level current Symbol IIH IIL VOH VOL RON1 Driver on resistor RON2 Standby current dissipation IST ISS*5 Operation current dissipation ISS*6 Input capacity CI Conditions VIN = VDD; LOAD, CP, CDR (CDL), R/L, DI1 to DI4, M, DISP OFF VIN = VSS; LOAD, CP, CDR (CDL), R/L, DI1 to DI4, M, DISP OFF IOH = –400 µA; CDL (CDR) IOL = 400 µA; CDL (CDR) VDD – VEE = 30 V,  VDE – VO  = 0.5 V*4; O1 to O80 VDD – VEE = 20 V,  VDE – VO  = 0.5 V*4; O1 to O80 CDR (CDL) = VDD, VDD – VEE = 30 V CP = 3.0 MHz, no-load output: VSS VDD – VEE = 30 V, CP = 3 MHz, LOAD = 14 kHz, M = 35 Hz; VSS VDD – VEE = 30 V, CP = 3 MHz, LOAD = 14 kHz, M = 35 Hz; VEE f = 3.0 MHz; CP 5 1.5 VDD – 0.4 0.4 3.0 V V kΩ kΩ µA –1 µA min typ max 1 Unit µA Input low-level current Output high-level voltage Output low-level voltage 2.0 3.5 200 4.0 mA 0.1 mA pF Note:4. VDE = V1 or V3 or V4 or VEE, V1 = VDD, V3 = 15/17 (VDD-VEE), V4 = 2/17 (VDD-VEE) 5. ISS current flows from VDD to VSS. 6. IEE current flows from VDD to VEE. Switching Characteristics at Ta = 25±2°C, VSS = 0 V, VDD = 5 V±10% Parameter Output delay time Symbol tD Conditions Load = 15 pF; CDR (CDL) min typ max 200 Unit ns No. 4346-2/8 LC79400D Pin Assignment A00971 Equivalent Circuit Block Diagram A00970 No. 4346-3/8 LC79400D Pin Descriptions Pin No 90 92 83 86 85 84 97 81 100 Pin name VDD VSS VEE V1 V3 V4 CP CDR CDL Input Input/Output Input/Output Power supply Power supply VDD and VEE: Power supply for LCD drive circuit LCD drive level power supply V1 and VEE : Select level V3 and V4 : Nonselect level Display data shift clock (triggering on the trailing edge) Chip disable pin H level : Data not accepted L level : Data accepted Pin Name CDR CDL Input/Output Input Output R/L L Pin Description Control input pin for the IC’s internal disable F/F. Output pin of the IC’s internal disable F/F. Connects to the next stage CDR pin when establishing a cascade connection. Control input pin for the IC’s internal disable F/F. Output pin of the IC’s internal disable F/F. Connects to the next stage CDL pin when establishing a cascade connection. Input/Output Functions VDD and VSS: Power supply for logic section CDL CDR Input Output H 99 LOAD Input Display data latch clock (triggering on the trailing edge). On the trailing edge, output levels switch in response to the particular combination of display data, M and DISP OFF signals. R/L Input data and latch address 93 94 95 96 DI4 DI3 DI2 DI1 Input L H 88 91 1 2 M R/L O1 O2 Input Input Output LCD drive output alternating signal Input pin which performs input/output switching for CDR and CDL pins and directional shift for 4-bit parallel input data. LCD drive output The combination of display data, M signal, and DISP OFF signal can be used to create output levels as shown below. M 79 80 O79 O80 L L H H * 89 DISP OFF Input Q L H L H * DISP OFF H H H H L Output V3 V1 V4 VEE V1 *Don’t care (To be set to either "H" or "L") Input pin which controls output pins O1 to O80. V1 level is output from O1 to O80 pin output during the low level input interval (See logic table). No. 4346-4/8 LC79400D Operation Timing (for R/L = H) A00974 No. 4346-5/8 LC79400D Time Chart (1/200 Duty 1/15 Bias)Switching Characteristics A00975 No. 4346-6/8 Sample Application LC79400D No. 4346-7/8 A00976 LC79400D Switching Characteristics A00973 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 4346-8/8