LC875J56C

Ordering number : EN8302A LC875J64C LC875J56C LC875J48C Overview CMOS IC ROM 64K/56K/48K byte, RAM 2048 byte on-chip 8-bit 1-chip Microcontroller The SANYO LC875J64C/56C/48C are 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 64K/56K/48K byte ROM, 2048 byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 26-source 10-vector interrupt feature. Features ROM • 65536 × 8-bits • 57344 × 8-bits • 49152 × 8-bits RAM • 2048 × 9-bits (LC875J64C) (LC875J56C) (LC875J48C) (LC875J64C/56C/48C) Minimum Bus Cycle • 83.3ns (12MHz) VDD=3.0 to 5.5V • 125ns (8MHz) VDD=2.5 to 5.5V • 500ns (2MHz) VDD=2.2 to 5.5V Note : The bus cycle time here refers to the ROM read speed. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.03 20707HKIM 20060222-S00014 No.8302-1/23 LC875J64C/875J56C/875J48C Minimum Instruction Cycle Time • 250ns (12MHz) VDD=3.0 to 5.5V • 375ns (8MHz) VDD=2.5 to 5.5V • 1.5µs (2MHz) VDD=2.2 to 5.5V Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units • Normal withstand voltage input port • Dedicated oscillator ports • Reset pins • Power pins 46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn, PWM2, PWM3, XT2) 8 (P0n) 1 (XT1) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to 3, VDD1 to 3) Timers • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM) • Timer 4: 8-bit timer with a 6-bit prescaler • Timer 5: 8-bit timer with a 6-bit prescaler • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) • Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler × 2 channels Mode 1: 16-bit timer with an 8-bit prescaler * Timer 8 is not supported in this version of Emulator. Please use on-chip-debugger (only supported in flash-ROM version) for debugging when developing software. • Base Timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO • SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) No.8302-2/23 LC875J64C/875J56C/875J48C UART • Full duplex • 7/8/9 bit data bits selectable • 1 stop bit (2-bit in continuous data transmission) • Built-in baudrate generator AD Converter: 8-bits × 11 channels PWM: Multifrequency 12-bit PWM × 2 channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) • Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock. Interrupts • 26 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/base timer T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/T8L/T8H SIO1/UART1 transmit ADC/T6/T7 Port 0/T4/T5/PWM2, PWM3 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • IFLG (list of interrupt source flag function) 3) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the diagram above). Subroutine Stack Levels: 1024 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions • 16-bits × 8-bits (5 tCYC execution time) • 24-bits × 16-bits (12 tCYC execution time) • 16-bits ÷ 8-bits (8 tCYC execution time) • 24-bits ÷ 16-bits (12 tCYC execution time) No.8302-3/23 LC875J64C/875J56C/875J48C Oscillation Circuits • RC oscillation circuit (internal): • CF oscillation circuit: • Crystal oscillation circuit: • Frequency variable RC oscillation circuit (internal): For system clock For system clock, with internal Rf For low-speed system clock, with internal Rf For system clock System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs (at a main clock rate of 10MHz). Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit ROM Correction Function • Executes the correction program on detection of a match with the program counter value. • Correction program area size : 128 bytes Package Form • QIP64E (14 × 14): • TQFP64J (10 × 10): Development Tools • Evaluation chip: • Emulator: • On-chip debugger: Lead-free type Lead-free type LC87EV690 EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP ICE-B877300 + SUB875800 + POD64QFP or POD64SQFP TCB87-TypeA or TCB87-TypeB + LC87F5JC8A No.8302-4/23 LC875J64C/875J56C/875J48C Package Dimensions unit : mm (typ) 3159A 17.2 14.0 48 49 33 32 Package Dimensions unit : mm (typ) 3310 12.0 0.8 48 49 33 32 10.0 14.0 17.2 64 17 1 0.5 16 0.18 64 1 0.8 (1.0) 0.35 16 17 (1.25) 12.0 0.125 0.15 1.2 MAX (2.7) 3.0max 0.1 (1.0) SANYO : TQFP64J(10X10) 0.1 SANYO : QIP64E(14X14) No.8302-5/23 0.5 10.0 LC875J64C/875J56C/875J48C Pin Assignment P83/AN3 P84/AN4 P85/AN5 P86/AN6 VDD3 VSS3 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P12/SCK0 2 P13/SO1 3 P14/SI1/SB1 4 P15/SCK1 5 P16/T1PWML 6 P17/T1PWMH/BUZ 7 PWM2 8 PWM3 9 10 11 12 13 14 15 16 P05/CKO VDD2 VSS2 P00 P01 P02 P03 P04 32 31 30 29 28 27 PB2 PB3 PB4 PB5 PB6 PB7 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN/INT7/T0HCP1 P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN/INT6/T0LCP1 P07/T7O P06/T6O LC875J64C LC875J56C LC875J48C PB1 26 25 24 23 22 21 20 19 18 17 Top view SANYO: QIP64E(14×14) “Lead-free Type” SANYO: TQFP64J(10×10) “Lead-free Type” No.8302-6/23 LC875J64C/875J56C/875J48C System Block Diagram Interrupt control IR PLA Standby control ROM correct CF RC MRC X’tal Clock generator ROM PC SIO0 Bus interface SIO1 Port 0 ACC Timer 0 Port 1 B register Timer 1 Port 2 C register Timer 4 Port 7 ALU Timer 5 Port 8 Timer 6 ADC PSW Timer 7 INT0 to 7 Noise filter RAR Timer 8 Port B RAM Base timer Port C Stack pointer PWM2/3 UART1 Watchdog timer No.8302-7/23 LC875J64C/875J56C/875J48C Pin Description Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 to P07 I/O • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistors can be turned on and off in 4-bit units. • HOLD reset input • Port 0 interrupt input • Shared pins P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output Port 1 P10 to P17 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 2 P20 to P27 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P24: INT7 input/timer 0H capture 1 input Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising & Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Yes I/O - Power supply pin Description Option No - + Power supply pin No Continued on next page. No.8302-8/23 LC875J64C/875J56C/875J48C Continued from preceding page. Pin Name Port 7 P70 to P73 I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. • Shared pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input port: AN8 (P70), AN9 (P71) Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No Port 8 P80 to P86 I/O • 7-bit I/O port • I/O specifiable in 1-bit units • Shared pins AD converter input port : AN0 (P80) to AN6 (P86) No PWM2, PWM3 Port B PB0 to PB7 Port C PC0 to PC7 RES XT1 I/O I/O • PWM2 and PWM3 output ports • General-purpose I/O available • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. No Yes I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistors can be turned on and off in 1-bit units. Yes Input Input Reset pin • 32.768kHz crystal oscillator input pin • Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. No No XT2 I/O • 32.768kHz crystal oscillator output pin • Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No.8302-9/23 LC875J64C/875J56C/875J48C Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name P00 to P07 Option Selected in Units of 1-bit Option Type 1 2 P10 to P17 1-bit 1 2 P20 to P27 1-bit 1 2 P70 P71 to P73 P80 to P86 PWM2, PWM3 PB0 to PB7 1-bit No No No No 1 2 PC0 to PC7 1-bit 1 2 XT1 XT2 No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS CMOS Nch-open drain CMOS Nch-open drain Input for 32.768kHz crystal oscillator (Input only) Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable Programmable No No Programmable Programmable Programmable Programmable No Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). *1: Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. LSI VDD1 Power supply For backup *2 VDD2 VDD3 VSS1 VSS2 VSS3 *2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. No.8302-10/23 LC875J64C/875J56C/875J48C Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Maximum supply voltage Input voltage Input/output voltage VI(1) VIO(1) XT1, CF1 Ports 0, 1, 2 Ports 7, 8 Ports B, C PWM2, PWM3, XT2 Peak output current IOPH(2) IOPH(3) Mean output High level output current current (Note 1-1) IOMH(2) IOMH(3) Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) Peak output current IOPL(1) IOMH(1) IOPH(1) Ports 0, 1, 2 Ports B, C PWM2, PWM3 P71 to P73 Ports 0, 1, 2 Ports B, C PWM2, PWM3 P71 to P73 P71 to P73 Port 1 PWM2, PWM3 Ports 0, 2 Ports 0, 1, 2 PWM2, PWM3 Port B Port C Ports B, C P02 to P07 Ports 1, 2 Ports B, C PWM2, PWM3 IOPL(2) IOPL(3) Mean output current (Note 1-1) Low level output current IOML(2) IOML(3) Total output current ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) ΣIOAL(7) ΣIOAL(8) ΣIOAL(9) Power dissipation Pd max ΣIOAL(1) IOML(1) P00, P01 Ports 7, 8 XT2 P02 to P07 Ports 1, 2 Ports B, C PWM2, PWM3 P00, P01 Ports 7, 8 XT2 Port 7 P83 to P86, XT2 P80 to P82 Ports 7, 8 XT2 Port 1 PWM2, PWM3 Ports 0, 2 Ports 0, 1, 2 PWM2, PWM3 Port B Port C Ports B, C QIP64E (14 × 14) TQFP64J (10 × 10) Operating ambient temperature Storage ambient temperature Tstg Topr -30 -55 Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta=-30 to +70°C Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin Per 1 applicable pin 20 7.5 15 15 20 45 45 80 45 45 80 355 255 +70 °C +125 mW Per 1 applicable pin 15 Per 1 applicable pin Per 1 applicable pin 30 10 mA Total of all applicable pins Total of all applicable pins Total of all applicable pins Per 1 applicable pin 20 Total of all applicable pins Total of all applicable pins CMOS output select Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin CMOS output select Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins -10 -20 -5 -7.5 -15 -3 -10 -25 -25 -45 -25 -25 -45 -0.3 VDD+0.3 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD [V] VDD1=VDD2=VDD3 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit Note 1-1: The mean output current is a mean value measured over 100ms. No.8302-11/23 LC875J64C/875J56C/875J48C Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD [V] 0.245µs≤tCYC≤200µs 0.367µs≤tCYC≤200µs 1.47µs≤tCYC≤200µs Memory sustaining supply voltage High level input voltage VIH(1) Ports 1, 2 P71 to P73 P70 port input/ interrupt side VIH(2) VIH(3) VIH(4) Low level input voltage VIL(1) Ports 0, 8, B, C PWM2, PWM3 Port 70 watchdog timer side XT1, XT2, CF1 RES Ports 1, 2 P71 to P73 P70 port input/ interrupt side VIL(2) Ports 0, 8, B, C PWM2, PWM3 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 4.0 VIL(3) VIL(4) Instruction cycle time (Note 2-1) External system clock frequency FEXCF(1) CF1 • CF2 pin open • System clock frequency division ratio=1/1 • External system clock duty =50 ± 5% • CF2 pin open • System clock frequency division ratio=1/2 Oscillation frequency range (Note 2-2) FmCF(2) FmCF(3) FmRC FmMRC FsX’tal XT1, XT2 CF1, CF2 CF1, CF2 FmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 8MHz ceramic oscillation See Fig. 1. 4MHz ceramic oscillation See Fig. 1. Internal RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal oscillation See Fig. 2. 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 0.3 0.1 0.2 0.2 0.2 12 8 4 1.0 16 32.768 kHz 2.0 2 24.4 16 4 MHz 2.5 to 5.5 0.1 8 tCYC Port 70 watchdog timer side XT1, XT2, CF1 RES 2.2 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 3.0 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS 0.245 0.367 1.47 0.1 VDD VDD VDD 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 200 12 µs 2.2 to 5.5 0.3VDD +0.7 VDD VHD VDD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 min 3.0 2.5 2.2 Specification typ max 5.5 5.5 5.5 unit V Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. No.8302-12/23 LC875J64C/875J56C/875J48C Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2 Ports 7, 8 Ports B, C RES PWM2, PWM3 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 Conditions VDD [V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) For input port specification VIN=VDD CF1 Ports 0, 1, 2 Ports 7, 8 Ports B, C RES PWM2, PWM3 IIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage Pin capacitance VHYS CP Ports 0, 1, 2, 7 Ports B, C RES Ports 1, 2, 7 All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.2 to 5.5 10 pF Ports 0, 1, 2 Ports B, C PWM2, PWM3 Ports 7, 8 XT2 P00, P01 PWM2, PWM3 P71 to P73 XT1, XT2 VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) For input port specification VIN=VSS CF1 Ports 0, 1, 2 Ports B, C VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA IOL=30mA IOL=5mA IOL=2.5mA VOH=0.9VDD 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 2.2 to 5.5 2.2 to 5.5 15 18 35 50 0.1 VDD -1 -15 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 1.5 0.4 0.4 0.4 0.4 1.5 0.4 0.4 80 150 kΩ V 2.2 to 5.5 -1 2.2 to 5.5 2.2 to 5.5 1 15 µA 2.2 to 5.5 1 min Specification typ max unit V No.8302-13/23 LC875J64C/875J56C/875J48C Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) • Continuous data transmission/reception mode Serial clock • See Fig. 6. • (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.2 to 5.5 0.03 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) 2.2 to 5.5 Output clock tdD0(3) (Note 4-1-3) (1/3)tCYC +0.05 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) See Fig. 6. Conditions VDD[V] min 2 1 1 tCYC Specification typ max unit (1/3)tCYC +0.05 1tCYC +0.05 µs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Serial output No.8302-14/23 LC875J64C/875J56C/875J48C 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) 0.03 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. (1/3)tCYC +0.05 µs • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig. 6. Conditions VDD[V] min 2 1 1 2 1/2 tSCK 1/2 Specification typ max unit tCY C Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.8302-15/23 LC875J64C/875J56C/875J48C Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 RES Resetting is enabled. 2.2 to 5.5 200 µs • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. 2.2 to 5.5 256 • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. 2.2 to 5.5 64 • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. 2.2 to 5.5 2 tCYC Conditions VDD [V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 min Specification typ max unit AD Converter Characteristics / Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P80) to AN6(P86), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions VDD [V] 3.0 to 5.5 3.0 to 5.5 15.68 (tCYC= 0.49µs) 23.52 3.0 to 5.5 AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 (tCYC= 0.735µs) 18.82 (tCYC= 0.294µs) 47.04 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.735µs) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min Specification typ 8 ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 V µA µs max unit bit LSB Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register. No.8302-16/23 LC875J64C/875J56C/875J48C Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD [V] • FmCF=12MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(3) • CF1=24MHz external clock • FmX’tal=32.768kHz crystal oscillation mode • System clock set to CF1 side IDDOP(4) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(5) • FmCF=8MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal IDDOP(6) oscillation mode • System clock set to 8MHz side • Internal RC oscillation stopped IDDOP(7) • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDOP(8) • FmCF=4MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal IDDOP(9) oscillation mode • System clock set to 4MHz side • Internal RC oscillation stopped IDDOP(10) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(11) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(12) • System clock set to internal RC oscillation IDDOP(13) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDOP(14) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal IDDOP(15) oscillation mode • Internal RC oscillation stopped • System clock set to 1MHz with IDDOP(16) frequency variable RC oscillation • 1/2 frequency division ratio IDDOP(17) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode IDDOP(18) • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDOP(19) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio 2.2 to 3.0 7 32 3.0 to 3.6 11 45 µA 4.5 to 5.5 27 65 2.2 to 3.0 0.4 1.6 3.0 to 3.6 0.65 2.2 4.5 to 5.5 1.2 3.5 2.2 to 3.0 0.2 1 3.0 to 3.6 0.3 1.4 4.5 to 5.5 0.55 2.1 2.2 to 3.0 0.7 1.4 3.0 to 3.6 1 2 4.5 to 5.5 2 3.2 2.5 to 3.0 2.2 3.8 mA 3.0 to 3.6 3.1 5.6 4.5 to 5.5 5.5 9 3.0 to 3.6 5.2 8.8 4.5 to 5.5 9.5 16 3.0 to 3.6 4.5 8 4.5 to 5.5 8 13.5 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page. No.8302-17/23 LC875J64C/875J56C/875J48C Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) IDDHALT(2) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 • HALT mode • FmCF=12MHz ceramic oscillation mode • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 12MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDHALT(3) • HALT mode • CF1=24MHz external clock • FmX’tal=32.768kHz crystal oscillation mode IDDHALT(4) • System clock set to CF1 side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(5) • HALT mode • FmCF=8MHz ceramic oscillation mode IDDHALT(6) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 8MHz side • Internal RC oscillation stopped IDDHALT(7) • Frequency variable RC oscillation stopped • 1/1 frequency division ratio IDDHALT(8) • HALT mode • FmCF=4MHz ceramic oscillation mode IDDHALT(9) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 4MHz side • Internal RC oscillation stopped IDDHALT(10) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio IDDHALT(11) IDDHALT(12) IDDHALT(13) IDDHALT(14) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio • HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(15) • FmX’tal=32.768kHz crystal oscillation mode • Internal RC oscillation stopped • System clock set to 1MHz with IDDHALT(16) frequency variable RC oscillation • 1/2 frequency division ratio IDDHALT(17) • HALT mode • FmCF=0Hz (oscillation stopped) IDDHALT(18) • FmX’tal=32.768kHz crystal oscillation mode • System clock set to 32.768kHz side • Internal RC oscillation stopped IDDHALT(19) • Frequency variable RC oscillation stopped • 1/2 frequency division ratio HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(6) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) • Timer HOLD mode • CF1=VDD or open (external clock mode) • FmX’tal=32.768kHz crystal oscillation mode 2.2 to 3.0 VDD1 • HOLD mode • CF1=VDD or open (external clock mode) 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 0.015 0.009 0.006 16 5.5 3 10 7 6 45 25 15 µA 2.2 to 3.0 3.6 20 3.0 to 3.6 6.2 30 4.5 to 5.5 19 50 2.2 to 3.0 0.35 1.4 3.0 to 3.6 0.55 1.8 4.5 to 5.5 1 2.9 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 0.28 0.15 0.1 1 0.7 0.5 2.2 to 3.0 0.3 0.7 3.0 to 3.6 0.5 1.1 4.5 to 5.5 1 2.1 2.5 to 3.0 0.7 1.5 mA 3.0 to 3.6 1.1 2.3 4.5 to 5.5 2 4.2 3.0 to 3.6 1.9 4.1 4.5 to 5.5 3.6 7.4 3.0 to 3.6 1.4 3 4.5 to 5.5 2.7 5.5 Conditions VDD [V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.8302-18/23 LC875J64C/875J56C/875J48C UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P20), URX(P21) 2.2 to 5.5 16/3 8192/3 tCYC Conditions VDD [V] min Specification typ max unit Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1-bit (2-bit in continuous data transmission) Parity bits: None *Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR *Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H) Start bit Start of reception Receive data (LSB first) Stop bit End of reception UBR No.8302-19/23 LC875J64C/875J56C/875J48C Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz MURATA CSTCE12M0G52-R0 CSTCE8M00G52-R0 CSTLS8M00G53-R0 4MHz MURATA CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (15) (15) C2 [pF] (10) (10) (15) (15) (15) Rf [Ω] Open Open Open Open Open Rd1 [Ω] 470 2.2k 680 3.3k 3.3k Operating Voltage Range [V] 3.0 to 5.5 2.7 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 0.1 0.1 0.2 0.2 max [ms] 0.5 0.5 0.5 0.6 0.6 Internal C1, C2 Internal C1, C2 Internal C1, C2 Remarks 8MHz MURATA The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C3 [pF] 32.768kHz SEIKO EPSON MC-306 18 C4 [pF] 18 Rf [Ω] Open Rd2 [Ω] 560k Operating Voltage Range [V] 2.2 to 5.5 typ [s] 1.4 Oscillation Stabilization Time max [s] Applicable 3.0 CL value = 12.5pF Remarks The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. CF1 CF2 XT1 XT2 Rf Rd1 Rf Rd2 C1 CF C2 C3 X’tal C4 Figure 1 CF Oscillator Circuit Figure 2 XT Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.8302-20/23 LC875J64C/875J56C/875J48C VDD Power supply Operating VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilizing Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.8302-21/23 LC875J64C/875J56C/875J48C VDD RRES RES CRES Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC’s operating voltage. Figure 5 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKLA SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.8302-22/23 LC875J64C/875J56C/875J48C SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice. PS No.8302-23/23