LC877C32C

Ordering number : ENA0135 LC877C64C,LC877C56C LC877C48C,LC877C40C LC877C32C,LC877C24C Overview CMOS IC Internal 64K/56K/48K/40K/32K/24K-byte ROM and 2048/1536-byte RAM 8-bit 1-chip Microcontroller The LC877C00 series are an 8-bit single chip microcontroller with the following on-chip functional blocks. : • CPU: operable at a minimum bus cycle time of 83.3ns • On-chip 64K-24K bytes ROM • On-chip RAM: 2048/1536 bytes • LCD controller / driver • 16 bit timer/counters (can be divided into 8-bit units) • 16 bit timer / PWM (can be divided into two 8-bit timers) • Four 8-bit timer with prescalers • Timer for use as date / time clock • Synchronous serial I/O port (with automatic block transmit / receive function) • Asynchronous / synchronous serial I/O port • 2 channel 12bit PWM • 12-channel × 8-bit AD converter • High-speed clock counter • System clock divider • Small signal detector • 20 source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features ROM • 65536 × 8 bits • 57344 × 8 bits • 49152 × 8 bits • 40960 × 8 bits • 32768 × 8 bits • 24576 × 8 bits (LC877C64C) (LC877C56C) (LC877C48C) (LC877C40C) (LC877C32C) (LC877C24C) Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. Ver.1.42 83006HKIM B8-9266 No.A0135-1/21 LC877C64C/56C/48C/40C/32C/24C RAM • 2048 × 9 bits (LC877C64C/56C) • 1536 × 9 bits (LC877C48C/40C/32C/24C) Minimum Instruction Cycle Time • 250 ns (12MHz) VDD=4.5 to 5.5V • 300 ns (10MHz) VDD=2.8 to 5.5V • 750 ns (4MHz) VDD=2.2 to 5.5V Ports • Input/output ports Data direction programmable for each bit individually: 20 (P1n, P70 to P73, P8n) Data direction programmable in nibble units: 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) • Input ports: 2 (XT1, XT2) • Output ports: 2 (PWM2, PWM3) • LCD ports Segment output: 32 (S00 to S15, S24 to S39) Common output: 4 (COM0 to COM3) Bias terminals for LCD driver: 3 (V1 to V3) Other functions Input/output ports: 32 (PAn, PBn, PDn, PEn) Input ports: 7 (PLn) • Oscillator pins: 2 (CF1, CF2) • Reset pin: 1 (RES) • Power supply: 6 (VSS1-3, VDD1-3) LCD Controller • Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) • Segment output and common output can be switched to general purpose input/output ports. Small Signal Detection (MIC signals etc) • Counts pulses with the level which is greater than a preset value • 2 bit counter Timers • Timer 0: 16 bit timer / counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit Counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register • Timer 1: PWM / 16 bit timer/ counter with toggle output function Mode 0: 8-bit timer with 8-bit prescaler (and toggle output) + 8-bit timer / counter with 8-bit prescaler (and toggle output) Mode 1: 2 channel 8-bit PWM with 8-bit prescaler Mode 2: 16-bit timer / counter with 8-bit prescaler (and toggle output) (Toggle output also possible using the lower order 8 bits) Mode 3: 16-bit timer with 8-bit prescaler (and toggle output) (The lower order 8 bits can be used as PWM output) • Timer 4: 8-bit timer with 6-bit prescaler • Timer 5: 8-bit timer with 6-bit prescaler • Timer 6: 8-bit timer with 6-bit prescaler (and toggle output) • Timer 7: 8-bit timer with 6-bit prescaler (and toggle output) • Base Timer 1) The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts of five different time intervals are possible. No.A0135-2/21 LC877C64C/56C/48C/40C/32C/24C High-speed Clock Counter • Countable up to 20MHz clock (when using 10MHz main clock) • Real time output SIO • SIO 0: 8 bit synchronous serial interface 1) LSB first / MSB first is selectable 2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 tCYC) 3) Consecutive automatic data communication (1 to 256 bits) • SIO 1: 8 bit asynchronous / synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) AD Converter: 8 bits × 12 channels PWM: 2 Channels Multi-frequency 12-bit PWM Remote Control Receiver Circuit (connected to P73 / INT3 / T0IN terminal) • Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC) Watchdog Timer • The watching time period is determined by an external RC. • Watchdog timer can produce interrupt or system reset Interrupts: 20 sources, 10 vectors 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L INT3/Base timer0 /Base timer1 T0H T1L/T1H SIO0 SIO1 ADC/MIC/T6/T7 Port 0/T4/T5/PWM2, PWM3 Interrupt Source • Priority level: X > H > L • For equal priority levels, vector with lowest address takes precedence. Subroutine Stack Levels: 1024 levels max (LC877C64C/56C) 768 levels max (LC877C48C/40C/32C/24C) Stack is located in RAM. No.A0135-3/21 LC877C64C/56C/48C/40C/32C/24C High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • On-chip RC oscillation for system clock use. • CF oscillation for system clock use. (Rf built in, Rd external) • Crystal oscillation low speed system clock use. (Rf built in, Rd external) • On-chip frequency variable RC oscillation circuit for system clock use. System Clock Divider • Low power consumption operation is available • Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can be switched by program (when using 10MHz main clock) Standby Function • HALT mode HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop). 1) Oscillation circuits are not stopped automatically. 2) Released by the system reset or interrupts. • HOLD mode HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1) CF, RC, X’tal and multi-frequency RC oscillation circuits stop automatically. 2) Released by any of the following conditions. (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2 (3) Port 0 interrupt • X’tal HOLD made X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF, RC and multi-frequency RC oscillation circuits stop automatically. 2) Crystal oscillator operation is kept in its state at HOLD mode inception. 3) Released by any of the following conditions (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2 (3) Port 0 interrupt (4) Base-timer interrupt Package Form • QFP80 (14 × 14): • TQFP80J (12 × 12): Development Tools • Evaluation chip: • Emulator: Lead-free type Lead-free type LC87EV690 EVA62S + ECB876600D + SUB877100 + POD80QFP(14 × 14) or POD80SQFP ICE-B877300 + SUB877100 + POD80QFP(14 × 14) or POD80SQFP • Flash ROM Version: LC87F7CC8A No.A0135-4/21 LC877C64C/56C/48C/40C/32C/24C Package Dimensions unit : mm (typ) 3255 17.2 14.0 60 61 41 40 Package Dimensions unit : mm (typ) 3290 14.0 0.8 12.0 60 61 41 40 14.0 17.2 12.0 80 1 (0.83) 0.65 0.25 20 21 0.15 80 1 0.5 (1.25) 0.2 20 21 0.125 3.0max (2.7) 0.1 1.2max SANYO : QFP80(14X14) 0.1 (1.0) SANYO : TQFP80J(12X12) Pin Assignment V1/PL4 V2/PL5 V3/PL6 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S15/PB7 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 PWM2 VSS3 VDD3 PWM3 P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 LC877C64C/ LC877C56C/ LC877C48C/ LC877C40C/ LC877C32C/ LC877C24C 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS2 VDD2 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN P72/INT2/T0IN P71/INT1/T0HCP/AN9 14.0 Top view SANYO : QFP80 (14 × 14) “Lead-free Type” SANYO : TQFP80J (12 × 12) “Lead-free Type” No.A0135-5/21 0.5 LC877C64C/56C/48C/40C/32C/24C System Block Diagram Interrupt control IR PLA Stanby control ROM RC MRC X’tal Clock Generator CF PC SIO0 Bus interface ACC SIO1 Port 0 B register Timer 0 (High speed clock counter) Port 1 C register Timer 1 Port 3 ALU Base Timer Port 8 LCD Controller PWM PSW INT0 to 3 Noise Rejection Filter ADC RAR Timer 4 Weak Signal Detector RAM Timer 5 Timer 6 Stack pointer Timer 7 Watchdog timer No.A0135-6/21 LC877C64C/56C/48C/40C/32C/24C Pin Description Pin name VSS1, VSS2, VSS3 VDD1, VDD2 VDD3 PORT0 P00 to P07 I/O I/O • Power supply (-) • Power supply (+) • 8bit input/output port • Data direction programmable in nibble units • Use of pull-up resistor can be specified in nibble units • Input for HOLD release • Input for port 0 interrupt • Other functions P05: clock output (system clock / can selected from sub clock) P06: timer 6 toggle output P07: timer 7 toggle output PORT1 P10 to P17 I/O • 8bit input/output port • Data direction programmable for each bit • Use of pull-up resistor can be specified for each bit individually • Other pin functions P10 SIO0 data output P11 SIO0 data input or bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input or bus input/output P15 SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output PORT7 P70 to P73 I/O • 4bit Input/output port • Data direction can be specified for each bit • Use of pull-up resistor can be specified for each bit individually • Other functions P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture input AD input port: AN8(P70), AN9(P71) • Interrupt detection selection Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising and falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Yes Function Option No No Yes Continued on next page. No.A0135-7/21 LC877C64C/56C/48C/40C/32C/24C Continued from preceding page. Pin name PORT8 P80 to P87 I/O I/O • 8bit Input/output port • Input/output can be specified for each bit individually • Other functions: AD input port: AN0 to AN7 Small signal detector input port: MICIN(P87) S0/PA0 to S7/PA7 S8/PB0 to S15/PB7 S24 /PD0 to S31/PD7 S32/PE0 to S39/PE7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 PWM2 PWM3 RES XT1 O O I I I/O I/O I/O I/O I/O I/O • Segment output for LCD • Can be used as general purpose input/output port (PA) • Segment output for LCD • Can be used as general purpose input/output port (PB) • Segment output for LCD • Can be used as general purpose input/output port (PD) • Segment output for LCD • Can be used as general purpose input/output port (PE) • Common output for LCD • Can be used as general purpose input port (PL) • LCD output bias power supply • Can be used as general purpose input port (PL) PWM2 output port PWM3 output port Reset terminal • Input for 32.768kHz crystal oscillation • Other functions: General-purpose input port AD input port: AN10 • When not in use, connect to VDD1 XT2 I/O • Output for 32.768kHz crystal oscillation • Other functions: General purpose input port AD input port: AN11 • When not in use, set to oscillation mode and leave open CF1 CF2 I O Input terminal for ceramic oscillator Output terminal for ceramic oscillator No No No No No No No No No No No No No Function description Option No No.A0135-8/21 LC877C64C/56C/48C/40C/32C/24C Port Output Types Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode. Port Name P00 to P07 Option Selected in Units of each bit Option Type 1 2 P10 to P17 each bit 1 2 P70 P71 to P73 P80 to P87 S0/PA0 to S15/PB7 S24/PD7 to S39/PE7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 PWM2, PWM3 XT1 XT2 None None None None Input only CMOS Input only Output for 32.768kHz crystal oscillation None None None None None Input only None None None None None CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Output Type Pull-up Resistor Programmable (Note 1) None Programmable Programmable Programmable Programmable None Programmable Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). *1: Connect as follows to reduce noise on VDD. VSS1, VSS2 and VSS3 must be connected together and grounded. *2: The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is prevented. LSI VDD1 Power supply Back-up capacitors *2 VDD2 VDD3 VSS1 VSS2 VSS3 No.A0135-9/21 LC877C64C/56C/48C/40C/32C/24C Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V Parameter Supply voltage Supply voltage for LCD Input voltage Input/Output voltage Peak output current IOPH(2) IOPH(3) High level output current Average output current (Note 1-1) Total output current ∑IOAH(2) ∑IOAH(3) ∑IOAH(4) ∑IOAH(5) Peak output current Low level output current IOPL(1) IOPL(2) IOPL(3) IOML(1) IOML(2) IOML(3) ∑IOAL(1) ∑IOAL(2) ∑IOAL(3) ∑IOAL(4) ∑IOAL(5) Maximum power consumption Operating temperature range Storage temperature range Tstg -55 +125 Topr -30 +70 °C Pd max IOMH(2) IOMH(3) ∑IOAH(1) Ports 71, 72, 73 • Ports A, B, D, E • PWM2, PWM3 • Ports 0, 1 • PWM2, PWM3 Port 7 Ports A, B, Ports D, E Ports A, B, D, E Ports 0, 1 Ports 7,8 • Ports A, B, D, E • PWM2, PWM3 Average output current (Note 1-1) Total output current Ports 0, 1 Ports 7, 8 • Ports A, B, D, E • PWM2, PWM3 • Ports 0, 1 • PWM2, PWM3 Ports 7, 8 Ports A, B Ports D, E Ports A, B, D, E QFP80(14×14) TQFP80J(12×12) Total of all pins Total of all pins Total of all pins Total of all pins Ta = -30 to +70°C Total of all pins Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Current at each pin Total of all pins IOMH(1) Ports 71,72,73 • Ports A, B, D, E • PWM2, PWM3 Ports 0,1 • CMOS output selected • Current at each pin Current at each pin Current at each pin IOPH(1) VI VIO(1) Symbol VDD max VLCD Pin/Remarks VDD1, VDD2, VDD3 V1/PL4, V2/PL5, V3/PL6 Port L XT1, XT2, CF1, RES • Ports 0, 1, 7, 8 • Ports A, B, D, E • PWM2, PWM3 Ports 0,1 • CMOS output selected • Current at each pin Current at each pin Current at each pin -10 -5 -5 -7.5 -3 -3 -25 -10 -25 -25 -45 20 10 10 15 7.5 7.5 45 15 45 45 80 381 325 mW mA -0.3 VDD+0.3 Conditions VDD1=VDD2=VDD3 VDD1=VDD2=VDD3 Specification VDD [V] min -0.3 -0.3 -0.3 typ max +6.5 VDD VDD+0.3 V unit Note 1-1: Average output current indicates average value for 100ms term. No.A0135-10/21 LC877C64C/56C/48C/40C/32C/24C Allowable Operating Range at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Operating supply voltage range Supply voltage range in Hold mode Input high voltage VIH(2) VIH(1) • Ports 0, 8 • Ports A, B, D, E, L • Port 1 • Ports 71, 72, 73 • P70 port input/interrupt VIH(3) VIH(4) VIH(5) Input low voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) VIL(7) Operation cycle time (Note 2-1) External system clock frequency FEXCF(1) CF1 • CF2 open • system clock divider :1/1 • external clock DUTY = 50 ± 5% • CF2 open • system clock divider :1/2 tCYC • Port 1 • Ports 71, 72, 73 • P70 port input/interrupt Port 87 small signal Input Port 70 Watchdog timer XT1, XT2, CF1, RES Output disable Output disable Output disable VIL(1) P87 small signal input Port 70 Watchdog timer XT1, XT2, CF1, RES • Ports 0, 8 • Ports A, B, D, E, L Output disable Output disable Output disable 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 4.0 2.2 to 5.5 2.2 to 5.5 2.8 to 5.5 4.5 to 5.5 2.8 to 5.5 2.2 to 5.5 4.5 to 5.5 2.8 to 5.5 2.2 to 5.5 4.5 to 5.5 2.8 to 5.5 2.2 to 5.5 Oscillation frequency range (Note 2-2) FmCF(2) FmCF(1) CF1, CF2 12MHz ceramic resonator oscillation See Fig. 1. 10MHz ceramic resonator oscillation See Fig. 1. FmCF(3) 4MHz ceramic resonator oscillation See Fig. 1. FmRC FmMRC FsX’tal XT1, XT2 RC oscillation Frequency variable RC oscillation source oscillation 32.768kHz crystal resonator oscillation See Fig. 2. 2.2 to 5.5 32.768 kHz 2.2 to 5.5 2.2 to 5.5 0.3 1.0 16 2.0 2.2 to 5.5 4 2.8 to 5.5 10 MHz 4.5 to 5.5 12 0.75VDD 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS VSS 0.245 0.294 0.735 0.1 0.1 0.1 0.2 0.2 0.2 VDD VDD VDD 0.15VDD +0.4 0.2VDD 0.1VDD +0.4 0.2VDD 0.25VDD 0.8VDD -1.0 0.25VDD 200 200 200 12 10 4 24.4 20 8 MHz µs V Output disable 2.2 to 5.5 0.3VDD +0.7 VDD Output disable 2.2 to 5.5 0.3VDD +0.7 VDD Symbol VDD(1) VDD(2) VDD(3) VHD VDD1 Pin/Remarks VDD1=VDD2=VDD3 Conditions 0.245µs≤ tCYC≤ 200µs 0.294µs≤ tCYC≤ 200µs 0.735µs≤ tCYC≤ 200µs Keep RAM and register data in HOLD mode. 2.0 5.5 Specification VDD [V] min 4.5 2.8 2.2 typ max 5.5 5.5 5.5 unit Note 2-1: Oscillation frequency and Operation cycle time (tCYC) rerationship: 1/1divide-3/FmCF, 1/2divide-6/FmCF Note 2-2: The parts value of oscillation circuit is shown in Table 1 and Table 2. No.A0135-11/21 LC877C64C/56C/48C/40C/32C/24C Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High level input current Symbol IIH(1) Pin/Remarks • Ports 0, 1, 7, 8 • Ports A, B, D, E, L • PWM2, PWM3 IIH(2) IIH(3) IIH(4) IIH(5) Low level input current IIL(1) RES XT1, XT2 CF1 P87/AN7/MICIN small signal input • Ports 0, 1, 7, 8 • Ports A, B, D, E, L • PWM2, PWM3 IIL(2) IIL(3) IIL(4) IIL(5) RES XT1,XT2 CF1 P87/AN7/MICIN small signal input Conditions • Output disabled • Pull-up resister OFF. • VIN=VDD (including OFF state leak current of the output Tr.) VIN=VDD When configured as an input port. VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS: Bias voltage) • Output disabled • Pull-up resister OFF. • VIN=VSS (including OFF state leak current of the output Tr.) VIN=VSS When configured as an input port. VIN=VSS VIN=VSS VIN=VBIS-0.5V (VBIS: Bias voltage) 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 -1 -1 -15 2.2 to 5.5 -1 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 5 10 1 1 15 20 µA 2.2 to 5.5 1 Specification VDD [V] min typ max unit 4.5 to 5.5 -20 -10 -5 High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) Ports 0, 1: CMOS output option IOH=-1.0mA IOH=-0.4mA IOH=-0.2mA IOH=-0.4mA IOH=-0.2mA IOH=-1.0mA IOH=-0.4mA IOH=-0.2mA IOL=10mA IOL=1.6mA IOL=1.0mA 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 VDD-1 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 0.4 0.4 0.4 0.4 V Port 7 • Ports A, B, D, E, • PWM2, PWM3 Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) Ports 0, 1 Ports 7, 8 IOL=1.6mA IOL=1.0mA IOL=1.6mA IOL=1.0mA IO=0mA VLCD, 2/3VLCD, 1/3VLCD level output See Fig. 8. • Ports A, B, D, E, • PWM2, PWM3 S0 to S15, S24 to S39 LCD output voltage regulation VODLS 2.2 to 5.5 0 ±0.2 VODLC COM0 to COM3 IO=0mA VLCD, 2/3VLCD, 1/2VLCD 1/3VLCD level output See Fig. 8. 2.2 to 5.5 0 ±0.2 LCD bias resistor RLCD(1) RLCD(2) Resistance per one bias resistor • Resistance per one bias resistor • 1/2R mode See Fig. 8. See Fig. 8. 2.2 to 5.5 60 kΩ 2.2 to 5.5 30 Continued on next page. No.A0135-12/21 LC877C64C/56C/48C/40C/32C/24C Continued from preceding page. Parameter Resistance of pull-up MOS Tr. Hysterisis voltage VHYS(1) VHYS(2) Pin capacitance CP Symbol Rpu Pin/Remarks • Ports 0, 1, 7 • Ports A, B, D, E • Ports 1, 7 • RES Port 87 small signal input All pins • All Other Terminals Connected To VSS. • F=1MHz • Ta=25°C Input sensitivity Vsen Port 87 small signal input 2.2 to 5.5 0.12VDD Vp-p 2.2 to 5.5 10 pF Conditions VOH=0.9VDD Specification VDD [V] 4.5 to 5.5 2.2 to 4.5 2.2 to 5.5 2.2 to 5.5 min 15 18 typ 35 50 0.1VDD V 0.1VDD max 80 150 kΩ unit Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level Input clock pulse width High level pulse width tSCKH(1) tSCKHA(1) • Continuous data transmission/reception mode • See Fig. 6. • (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) • Continuous data transmission/reception mode • CMOS output selected • See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) 2.2 to 5.5 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode • (Note 4-1-3) tdD0(3) (Note 4-1-3) 2.2 to 5.5 (1/3)tCYC +0.15 2.2 to 5.5 2.2 to 5.5 0.03 • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.2 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected • See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) See Fig. 6. Conditions Specification VDD [V] min 2 1 1 tCYC typ max unit Serial clock (1/3)tCYC +0.05 1tCYC +0.05 µs Serial output Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. Output clock No.A0135-13/21 LC877C64C/56C/48C/40C/32C/24C 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) 2.2 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK. • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 0.03 µs • Must be specified with respect to rising edge of SIOCLK. • See Fig. 6. 2.2 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected • See Fig. 6. 2.2 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig. 6. Conditions Specification VDD [V] min 2 2.2 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A0135-14/21 LC877C64C/56C/48C/40C/32C/24C Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P30 to P33) INT5(P34 to P35) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) tPIL(5) tPIL(6) RES INT3(P73) (Noise rejection ratio is 1/1.) INT3(P73) (Noise rejection ratio is 1/32.) INT3(P73) (Noise rejection ratio is 1/128.) MICIN(P87) • Condition that interrupt is accepted • Condition that event input to timer 0 is accepted • Condition that interrupt is accepted • Condition that event input to timer 0 is accepted • Condition that interrupt is accepted • Condition that event input to timer 0 is accepted • Condition that signal is accepted to small signal detection counter. • Condition that reset is accepted 2.2 to 5.5 2.2 to 5.5 1 200 µs 2.2 to 5.5 256 2.2 to 5.5 64 2.2 to 5.5 2 tCYC Conditions • Condition that interrupt is accepted • Condition that event input to timer 0 is accepted 2.2 to 5.5 1 Specification VDD [V] min typ max unit AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) 3.0 to 5.5 AD conversion time=64 × tCYC (when ADCR2=1) (Note 6-2) 4.5 to 5.5 AD conversion time=32 × tCYC (when ADCR2=0) (Note 6-2) 4.5 to 5.5 (Note 6-1) Conditions Specification VDD [V] 3.0 to 5.5 3.0 to 5.5 15.62 (tCYC= 0.488µs) 23.52 (tCYC= 0.735µs) 18.82 (tCYC= 0.294µs) 47.04 3.0 to 5.5 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 0.735µs) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 VSS min typ 8 max unit bit ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs) VDD 1 LSB µs V µA Note 6-1: Absolute precision does not include quantizing error (±1/2 LSB). Note 6-2: Conversion time means time from executing AD conversion instruction to loading complete digital value to register. No.A0135-15/21 LC877C64C/56C/48C/40C/32C/24C Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Parameter Current consumption during normal operation (Note 7-1) IDDOP(2) IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) IDDOP(14) IDDOP(15) IDDOP(16) Current consumption during HALT mode (Note 7-1) IDDHALT(1) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions • FmCF=12MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 12MHz oscillation • Frequency variable RC oscillation stopped • Internal RC oscillation stopped. • Divider: 1/1 • FmCF=10MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 10MHz oscillation • Frequency variable RC oscillation stopped • Internal RC oscillation stopped. • Divider: 1/1 • FmCF=4MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 4MHz oscillation • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider:1/1 • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Frequency variable RC oscillation stopped • System clock: RC oscillation • Divider:1/2 •FmCF=0Hz (No oscillation) •FsX’tal=32.768kHz crystal oscillation •Internal RC oscillation stopped. •System clock: 1MHz with frequency variable RC oscillation •Divider:1/2 • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider:1/2 HALT mode • FmCF=12MHz Ceramic resonator oscillation • FsX’tal=32.768kHz crystal oscillation • System clock: CF 12MHz oscillation • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider: 1/1 IDDHALT(2) HALT mode • FmCF=10MHz Ceramic resonator oscillation IDDHALT(3) • FsX’tal=32.768kHz crystal oscillation • System clock: CF 10MHz oscillation • Internal RC oscillation stopped. IDDHALT(4) IDDHALT(5) • Frequency variable RC oscillation stopped • Divider: 1/1 HALT mode • FmCF=4MHz Ceramic resonator oscillation IDDHALT(6) • FsX’tal=32.768kHz crystal oscillation • System clock: CF 4MHz oscillation • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider: 1/1 2.2 to 3.0 0.38 0.88 3.0 to 3.6 0.65 1.4 2.8 to 3.0 0.7 1.5 3.0 to 3.6 1.1 2.3 mA 4.5 to 5.5 2 4.2 4.5 to 5.5 2.5 5.3 4.5 to 5.5 3.0 to 3.6 2.8 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 5.5 3.1 2.2 2.5 1.2 0.9 0.55 0.3 0.2 1.2 0.65 0.4 27 11 7 9 5.6 3.8 4 2.5 1.8 2.1 1.4 1 3.5 2.2 1.6 65 45 32 µA mA 4.5 to 5.5 7 12 Specification VDD [V] min typ max unit 4.5 to 5.5 1.2 2.6 IDDHALT(7) Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. Continued on next page. No.A0135-16/21 LC877C64C/56C/48C/40C/32C/24C Continued from preceding page. Parameter Current consumption during HALT mode (Note 7-1) IDDHALT(10) IDDHALT(11) IDDHALT(12) IDDHALT(13) IDDHALT(9) Symbol IDDHALT(8) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation • System clock: RC oscillation • Frequency variable RC oscillation stopped • Divider: 1/2 HALT mode • FmCF=0Hz (No oscillation) • FsX’tal=32.768kHz crystal oscillation • Internal RC oscillation stopped. • System clock: 1MHz with frequency variable RC oscillation • Divider :1/2 IDDHALT(14) IDDHALT(15) IDDHALT(16) HALT mode • FmCF=0Hz (Oscillation stop) • FsX’tal=32.768kHz crystal oscillation • System clock: 32.768kHz • Internal RC oscillation stopped. • Frequency variable RC oscillation stopped • Divider: 1/2 Current consumption during HOLD mode Current consumption during Date/time clock HOLD mode IDDHOLD(6) IDDHOLD(5) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) VDD1 HOLD mode • CF1=VDD or open (when using external clock) Date/time clock HOLD mode • CF1=VDD or open (when using external clock) • FmX’tal=32.768kHz crystal oscillation 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 0.025 0.015 0.009 16 5.5 3 10 7 6 45 25 15 µA 2.2 to 3.0 3.6 20 4.5 to 5.5 3.0 to 3.6 19 6.2 50 30 2.2 to 3.0 0.35 1.4 Conditions Specification VDD [V] 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 min typ 0.28 0.15 0.1 1 0.55 max 1 0.7 0.5 2.9 1.8 mA unit Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored. No.A0135-17/21 LC877C64C/56C/48C/40C/32C/24C Characteristics of a Sample Main System Clock Oscillation Circuit The characteristics in the table bellow is based on the following conditions: (1) Use the standard evaluation board SANYO has provided. (2) Use the peripheral parts with indicated value externally. (3) The peripheral parts value is a recommended value of oscillator manufacturer Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz 10MHz MURATA MURATA CSTCE12M0G52-R0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 (10) (10) (15) (15) (15) C2 [pF] (10) (10) (15) (15) (15) Rf1 [Ω] Open Open Open Open Open Rd1 [Ω] 470 1.0k 680 3.3k 3.3k Operating Voltage Range [V] 4.5 to 5.5 2.8 to 5.5 2.8 to 5.5 2.2 to 5.5 2.2 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 0.05 max [ms] 0.15 0.15 0.15 0.15 0.15 Internal C1, C2 Internal C1, C2 Internal C1, C2 Remarks 4MHz MURATA The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage (See Figure 4). Characteristics of a Sample Subsystem Clock Oscillator Circuit The characteristics in the table bellow is based on the following conditions: (1) Use the standard evaluation board SANYO has provided. (2) Use the peripheral parts with indicated value externally. (3) The peripheral parts value is a recommended value of oscillator manufacturer Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Nominal Frequency Vendor Name Oscillator Name C3 [pF] 32.768kHz SEIKO EPSON MC-306 18 Circuit Constant C4 [pF] 18 Rf2 [Ω] Open Rd2 [Ω] 560k Operating Voltage Range [V] 2.2 to 5.5 Oscillation Stabilization Time typ [s] 1.3 max [s] Applicable 3.0 CL value =12.5pF Remarks The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode (See Figure 4). Note : Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. CF1 CF2 XT1 XT2 Rf1 Rd1 Rf2 Rd2 C1 CF C2 C3 X’tal C4 Figure 1 Ceramic Oscillator Circuit Figure 2 Crystal Oscillator Circuit 0.5VDD Figure 3 AC Timing Measurement Point No.A0135-18/21 LC877C64C/56C/48C/40C/32C/24C VDD Power supply Operating VDD lower limit 0V Reset time RES Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid Internal RC oscillation tmsCF CF1, CF2 tmsX’tal XT1, XT2 State HOLD HALT HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times No.A0135-19/21 LC877C64C/56C/48C/40C/32C/24C VDD RRES RES CRES Note : Determine the value of CRES and RRES so that the reset signal is present for a period of 200µs after the supply voltage goes beyond the lower limit of the IC’s operating voltage. Figure 5 Reset Circuit SIOCLK : DATAIN : DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT : DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transfer period (SIO0 only) DO8 tSCK tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : Data RAM transfer period (SIO0 only) tSCKL SIOCLK : tsDI DATAIN : tdDO DATAOUT : thDI tSCKHA thDI tSCKH Figure 6 Serial I/O Output Waveforms tPIL tPIH Figure 7 Pulse Input Timing Signal Waveform No.A0135-20/21 LC877C64C/56C/48C/40C/32C/24C VDD SW : ON/OFF (programmable) RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND SW : ON (VLCD=VDD) Figure 8 LCD bias resistor Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 2006. Specifications and information herein are subject to change without notice. PS No.A0135-21/21