LC8784P7PB

Ordering number : ENA1795 LC878496PB,LC8784C8PB LC8784G0PB,LC8784G1PB LC8784J2PB,LC8784J3PB LC8784M4PB,LC8784P6PB LC8784P7PB Overview CMOS IC FROM 256K byte, RAM 12K byte on-chip 8-bit ETR Microcontroller The LC8784XXPB series is an 8-bit ETR microcomputer that, centered around a CPU running at a minimum bus cycle time of 74.07 ns (CF = 13.5MHz), integrate on a single chip a number of hardware features such as direct control function of CD mechanism and CD-DSP for car audio, 256K-byte ROM (max), 12K-byte RAM (max), two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.07 20211HKPC 20100618-S00013, S00012, S00011, S00010, S00009, S00008, S00007, S00006, S00005 No.A1795-1/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ROM for each model/Table RAM capacity Type No. LC878496PB LC8784C8PB LC8784G0PB LC8784G1PB LC8784J2PB LC8784J3PB LC8784M4PB LC8784P6PB LC8784P7PB ROM (byte) 96K 128K 160K 160K 192K 192K 224K 256K 256K RAM (byte) 6K 6K 6K 8K 8K 10K 10K 10K 12K Features ■Minimum Bus Cycle Time • 74.04ns (CF = 13.5MHz) Note: Bus cycle time indicates the speed to read ROM. ■Minimum Instruction Cycle Time (tCYC) ■Ports • 222ns (CF = 13.5MHz) Note: The minimum instruction cycle time: Minimum bus cycle time × 3 • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 57 (P1n, P2n, P30 to P35, P70 to P73, P8n, PBn, PCn, SI2Pm, PWM0, PWM1, XT2, n=0 to 7, m=0 to 3) Ports whose I/O direction can be designated in 2 bit units: 16 (PEn, PFn n=0 to 7) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n n=0 to 7) • Normal withstand voltage input ports: 1 (XT1) • Internal low voltage output ports: 1 (VREG) • Dedicated oscillator ports: 2 (CF1, CF2) • Reset pin: 1 (RES) • Digital power pins: 6 (VSSn, VDDn n=1, 2, 4) ■Timers • Timer 0: 16-bit programmable timer/counter with capture register Mode 0: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit programmable counter (with two 8-bit capture registers) Mode 2: 16-bit programmable timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit programmable counter (with 2 16-bit capture registers) • Timer 1: 16-bit programmable timer/counter that support PWM/ toggle output Mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle outputs) + 8-bit programmable timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) Mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit programmable timer with a 6-bit prescaler • Timer 5: 8-bit programmable timer with a 6-bit prescaler • Timer 6: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillator), cycle clock (tCYC), and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. No.A1795-2/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■High Speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz) (When High-speed clock counter is used, timer 0 cannot be used). 2) Can generate output real time. ■SIO: 3 channels • SIO 0: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle) 3) Automatic continuous data transmission (1 to 256 bits) • SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2 to or 3 to wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO2: 8 bit synchronous serial interface 1) LSB first mode 2) Built-in 3-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle) 3) Automatic continuous data transmission (1 to 32 bytes) ■UART: 2 channels 1) Full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) Built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) ■AD Converter: 8 bits × 10 channels ■PWM: Multifrequency 12-bit PWM × 4 channels ■Remote Control Receiver Noise Filtering Function (sharing pins with P73, INT3, and T0IN) 1) Noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. ■Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable No.A1795-3/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■Interrupts • 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/INT5/Base timer (BT0, 1) T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/UART2 receive SIO1/SIO2/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, PWM5 Port 0/T4/T5/PWM0, PWM1 Interrupt Source • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • The Base timers are two interrupt sources of BT0 and BT1, it is one interrupt source by PWM0 and 1, it is one interrupt source by PWM4 and 5. ■Subroutine Stack Levels • 16 bits × 8 bits • 24 bits × 16 bits • 16 bits ÷ 8 bits • 24 bits ÷ 16 bits • 6144 levels maximum (1/2 of capacity of RAM, the stack is allocated in RAM.) ■High-speed Multiplication/Division Instructions (5 tCYC execution time) (12 tCYC execution time) (8 tCYC execution time) (12 tCYC execution time) ■Oscillation Circuits For system clock For system clock with internal Rf and external Rd For time-of-day clock, for low-speed system clock with internal Rf and external Rd • Multifrequency RC oscillator circuit (internal): For system clock • RC oscillator circuit (internal): • CF oscillator circuit: • Crystal oscillator circuit: ■System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 222ns, 444ns, 888ns, 1.78μs, 3.55μs, 7.10μs, 14.2μs, 28.4μs, and 56.8μs.(at a main clock of 13.5MHz) No.A1795-4/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by system reset, detection VDET0 or occurrence of interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF oscillators, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the Reset pin to the lower level. (2) Voltage descent detection (VDET1) (3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (4) Having an interrupt source established at port 0. • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF oscillators, and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when X’tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the Reset pin to the low level. (2) Voltage descent detection (VDET0) (3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the base timer circuit. ■Reset • External reset • Voltage descent detection (VDET0, VDET1) reset circuit (internal) • QIP100E (Lead Free Product) • LC87F83P7PB • LC87F83P7PBU (User writing) ■Shipping Form ■Flash ROM Version No.A1795-5/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Maximum Supply voltage Input voltage Input/Output voltage VI(1) VIO(1) Symbol VDD max Pins/Remarks VDD1, VDD2, VDD3, VDD4 CF1, XT1, Ports 0, 1, 2 Ports 3, 7, 8 Ports B, C, E, F SI2P0 to SI2P3 PWM0, PWM1, XT2 Peak output current IOPH(1) Ports 0, 1, 2, 3 Ports 71 to 73 Ports B, C, E, F SI2P0 to SI2P3 IOPH(2) Average output current (Note 1-1) High level output current IOMH(2) Total output current ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) IOMH(1) PWM0, PWM1 Ports 0, 1, 2, 3 Ports 71 to 73 Ports B, C, E, F SI2P0 to SI2P3 PWM0, PWM1 P71 to P73 PWM0, PWM1 SI2P0 to SI2P3 Ports 0 Port 0 PWM0, PWM1 SI2P0 to SI2P3 ΣIOAH(5) ΣIOAH(6) ΣIOAH(7) ΣIOAH(8) ΣIOAH(9) ΣIOAH(10) Ports 2, 3, B Ports C Ports 2, 3, B, C Ports F Ports 1, E Ports 1, E, F Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins -25 -25 -45 -25 -25 -45 Total of all applicable pins Total of all applicable pins -45 Per 1 application pin. Total of all applicable pins Total of all applicable pins -15 -25 -25 -25 mA Per 1 application pin. CMOS output select per 1 application pin -7.5 -20 CMOS output select per 1 application pin -10 -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3 =VDD4 min -0.3 -0.3 Specification typ max +6.5 VDD+0.3 V unit Note 1-1: Average output current is average of current in 100ms interval. Continued on next page. No.A1795-6/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter Peak output current Symbol IOPL(1) Pins/Remarks Ports 0, 1, 2, 3, 8 Ports B, C, E, F SI2P0 to SI2P3 XT2 IOPL(2) Average output current (Note 1-1) IOML(2) Low level output current Total output current ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) ΣIOAL(4) ΣIOAL(5) ΣIOAL(6) IOML(1) PWM0, PWM1 Ports 0, 1, 2, 3, 7 Ports 8, B, C, E, F SI2P0 to SI2P3 XT2 PWM0, PWM1 Port 7, XT2 Port 8 Ports 7, 8, XT2 PWM0, PWM1 SI2P0 to SI2P3 Port 0 Port 0 PWM0, PWM1 SI2P0 to SI2P3 ΣIOAL(7) ΣIOAL(8) ΣIOAL(9) ΣIOAL(10) ΣIOAL(11) ΣIOAL(12) Maximum power consumption Operating temperature range Storage temperature range Tstg Topr -40 -45 Pd max Ports 2, 3, B Ports C Ports 2, 3, B, C Port F Ports 1, E Ports 1, E, F QIP100E Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins Ta = -40 to +85°C 25 25 45 25 25 45 400 +85 +125 mW °C °C Total of all applicable pins Total of all applicable pins 45 Per 1 application pin. Total of all applicable pins Total of all applicable pins Total of all applicable pins Total of all applicable pins 20 25 25 45 25 25 mA Per 1 application pin. Per 1 application pin. 7.5 20 Conditions VDD[V] Per 1 application pin. 10 min Specification typ max unit Note 1-1: Average output current is average of current in 100ms interval. No.A1795-7/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Recommended operating range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) VHD Symbol VDD(1) Pins/Remarks VDD1=VDD2=VDD3 =VDD4 VDD1=VDD2=VDD3 =VDD4 Ports 1, 2 SI2P0 to 3 P71 to P73 P70 port input/ interrupt side VIH(2) Ports 0, 3, 8 Ports B, C, E, F PWM0, PWM1 VIH(3) VIH(4) Low level input voltage VIL(2) VIL(1) Port70 Watchdog timer side XT1, XT2, RES Ports 1, 2 SI2P0 to 3 P71 to P73 P70 port input/ interrupt side VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-1) Oscillation frequency range FmCF FmRC FmMRC CF1, CF2 CF oscillation. Internal RC oscillation Frequency variable RC oscillation source oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation. 3.0 to 5.5 32.768 kHz 3.0 to 5.5 16 tCYC Ports 0, 3, 8 Ports B, C, E, F PWM0, PWM1 Port70 Watchdog timer side XT1, XT2, RES When XT1 and XT2 general purpose input 4.0 to 5.5 3.0 to 4.0 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 VSS VSS VSS VSS 0.222 4 0.3 1.0 13.5 2.0 MHz 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD μs 3.0 to 4.0 VSS 0.2VDD When XT1 and XT2 general purpose input 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 3.0 to 5.5 0.3VDD +0.7 0.9VDD 0.75VDD VSS VDD 3.0 to 5.5 Conditions VDD[V] CPU operation RAM and register contents in HOLD mode. min 3.0 1.0 Specification typ max 5.5 5.5 unit 0.35VDD +0.7 VDD VDD V VDD 0.1VDD +0.4 Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. No.A1795-8/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High level input curre Symbol IIH(1) Pins/Remarks Ports 0, 1, 2 Ports 3, 7, 8 Ports B, C, E, F SI2P0 to SI2P3 RES PWM0, PWM1 IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 CF1 Ports 0, 1, 2 Ports 3, 7, 8 Ports B, C, E, F SI2P0 to SI2P3 RES PWM0, PWM1 IIL(2) IIL(3) High level output voltage VOH(2) VOH(3) VOH(4) Low level output voltage VOL(2) VOL(3) VOL(4) VOL(5) Pull-up resistation Rpu(1) Rpu(2) Hysteresis voltage VHYS Ports 70, 8, XT2 Ports 0, 1, 2, 3 Port 7 Ports B, C, E, F RES Ports 1, 2, 7 SI2P0 to SI2P3 Pin capacitance CP All pins • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C Power down detection voltage VDET0 VDET1 VDD1 • Excluding the HOLD mode • HOLD mode 3.0 1.1 3.3 1.6 3.6 2.1 V 3.0 to 5.5 10 pF 3.0 to 5.5 0.1VDD V 3.0 to 5.5 15 35 150 VOL(1) VOH(1) XT1, XT2 CF1 Ports 0, 1, 2, 3 Ports B, C, E, F Ports 71, 72, 73 SI2P0 to SI2P3 PWM0, PWM1 P30, P31(PWM4, 5 output mode) Ports 0, 1, 2, 3 Ports B, C, E, F Ports 71, 72, 73 SI2P0 to SI2P3 PWM0, PWM1 IOL=10mA IOL=1.6mA IOL=1.6mA VOH=0.9VDD IOL=0.4mA IOL=1.0mA IOH=-10mA IOH=-1.6mA IOH=-0.4mA Using as an input port VIN=VSS VIN=VSS IOH=-1.0mA 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 4.5 to 5.5 3.0 to 5.5 3.0 to 5.5 4.5 to 5.5 15 35 -1 -15 VDD-1 VDD-0.4 VDD-1.5 VDD-0.4 V 1.0 0.4 1.5 0.4 0.4 80 kΩ -5 -1 Using as an input port VIN=VDD VIN=VDD Output disable Pull-up resistor OFF VIN=VDD (including the off-leak current of the output Tr.) 3.0 to 5.5 -1 3.0 to 5.5 3.0 to 5.5 1 5 1 15 μA Conditions VDD[V] Output disable Pull-up resistor OFF VIN=VDD (including the off-leak current of the output Tr.) 3.0 to 5.5 1 min Specification typ max unit No.A1795-9/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(1a) • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. • See Fig. 2. • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode • SIO2 is in use simultaneous. Serial clock • See Fig. 2. • (Note 4-1-2) Frequency Low level pulse width High level pulse width Output clock tSCKHA(2a) • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. • CMOS output selected. • See Fig. 2. tSCKHA(2b) • Continuous data transmission/reception mode • SIO2 is in use simultaneous. • CMOS output selected. • See Fig. 2. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold time thDI(1) • Must be specified with respect to rising edge of SIOCLK • See fig. 2. 3.0 to 5.5 0.03 Output Input clock delay time tdD0(2) tdD0(3) tdD0(1) SI0(P11), SB0(P11) • Continuous data transmission/reception mode • (Note 4-1-3) • Synchronous 8-bit mode. • (Note 4-1-3) Output clock • (Note 4-1-3) 3.0 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) +(16/3)tCYC 3.0 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3)tCYC tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) • CMOS output selected. • See Fig. 2. 4/3 1/2 tSCK 1/2 6 3.0 to 5.5 4 tSCKH(1) Symbol tSCK(1) tSCKL(1) Pins/ Remarks SCK0(P12) Conditions VDD[V] • See Fig. 2. min 2 1 1 Specification typ max unit tCYC (1/3)tCYC +0.05 1tCYC +0.05 μs Serial output (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 2. No.A1795-10/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14), SB1(P14) Data hold time thDI(2) • Must be specified with respect to rising edge of SIOCLK • See fig. 2. 3.0 to 5.5 0.03 Output Serial output delay time tdD0(4) SO1(P13), SB1(P14) • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 2. 3.0 to 5.5 (1/3)tCYC +0.05 μs 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) • CMOS output selected. • See Fig. 2. 3.0 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pins/ Remarks SCK1(P15) Conditions VDD[V] • See Fig. 2. min 2 3.0 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Serial clock No.A1795-11/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB 3. SIO2 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Low level pulse width High level pulse width Input clock tSCKHA(5a) • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. • See Fig. 2. • (Note 4-3-2) tSCKHA(5b) • Continuous data transmission/reception mode of SIO0 is in use simultaneous. Serial clock • See Fig. 2. • (Note 4-3-2) Frequency Low level pulse width High level pulse width Output clock tSCKHA(6a) • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. • CMOS output selected. • See Fig. 2. tSCKHA(6b) • Continuous data transmission/reception mode of SIO0 is in use simultaneous. • CMOS output selected. • See Fig. 2. Data setup time Serial input tsDI(3) SI2(SI2P1), SB2(SI2P1) Data hold time thDI(3) • Must be specified with respect to rising edge of SIOCLK • See fig. 2. 3.0 to 5.5 0.03 Output delay Serial output time tdD0(5) SO2(SI2P0), SB2(SI2P1) • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state change in open drain output mode. • See Fig. 2. 3.0 to 5.5 (1/3)tCYC +0.05 μs 0.03 tSCKH(6) +(5/3)tCYC tSCKH(6) +(19/3)tCYC 3.0 to 5.5 tSCKH(6) +(5/3)tCYC tSCKH(6) +(10/3)tCYC tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK2 (SI2P2) SCK2O (SI2P3) • CMOS output selected. • See Fig. 2. 4/3 1/2 tSCK 1/2 7 3.0 to 5.5 4 tSCKH(5) Symbol tSCK(5) tSCKL(5) Pins/ Remarks SCK2 (SI2P2) Conditions VDD[V] • See Fig. 2. min 2 1 1 Specification typ max unit tCYC Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input, a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. No.A1795-12/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter High/low level pulse wid Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant is 1/1. INT3(P73) (The noise rejection clock is selected to 1/32.) INT3(P73) (The noise rejection clock is selected to 1/128.) RES • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Interrupt source flag can be set. • Event inputs for timer 0 are enabled. • Reset acceptable * See Fig. below 3.0 to 5.5 200 μs 3.0 to 5.5 256 3.0 to 5.5 64 3.0 to 5.5 2 tCYC Conditions VDD[V] • Interrupt source flag can be set. • Event inputs for timer 0 or 1 are enabled. 3.0 to 5.5 1 min Specification typ max unit VDD RES Internal regulator stabilization time must be 10ms (max.) or more. Figure Power-on Time Reset Timing AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Resolution Absolute precision Conversion time Symbol N ET TCAD Pins/Remarks AN0(P80) to AN7(P87) AN8(P70) AN9(P71) (Note 6-1) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 7.104(tCYC= 0.222μs) 14.21(tCYC= 0.222μs) VSS VDD 1 V μA μs min Specification typ 8 ±1.5 max unit bit LSB Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. No.A1795-13/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 Conditions VDD[V] • FmCF=13.5MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode • System clock set to 13.5MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(3) • FmCF=8MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDOP(4) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(5) • FmCF=4MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode • System clock set to 4MHz side IDDOP(6) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(7) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDOP(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. IDDOP(9) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • Internal RC oscillation stopped IDDOP(10) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio. IDDOP(11) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • System clock set to 32.768kHz side. IDDOP(12) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. 3.0 to 4.5 250 450 μA 4.5 to 5.5 300 500 3.0 to 4.5 0.5 1.5 4.5 to 5.5 0.8 2.0 3.0 to 4.5 0.6 1.0 4.5 to 5.5 0.8 1.2 3.0 to 4.5 2.4 3.0 mA 4.5 to 5.5 3.0 4.0 3.0 to 4.5 4.0 5.0 4.5 to 5.5 5.0 6.0 3.0 to 4.5 6.0 8.0 4.5 to 5.5 8.0 10.0 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting Continued on next page. No.A1795-14/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter HALT mode consumption current (Note 7-1) IDDHALT(2) Symbol IDDHALT(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 • HALT mode • FmCF=13.5MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode • System clock set to 13.5MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDHALT(3) • HALT mode • FmCF=8MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(4) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDHALT(5) • HALT mode • FmCF=4MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(6) • System clock set to 4MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDHALT(7) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. IDDHALT(9) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDHALT(10) • Internal RC oscillation stopped • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio. IDDHALT(11) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDHALT(12) • System clock set to 32.768kHz side. • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. Current drain during HOLD mode Current drain during timebase clock HOLD mode IDDHOLD(4) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) VDD1 • Timer HOLD mode • FmX'tal=32.768kHz by crystal oscillation mode 3.0 to 4.5 100 200 VDD1 • HOLD mode 4.5 to 5.5 3.0 to 4.5 4.5 to 5.5 1.5 1.0 150 20.0 18.0 300 3.0 to 4.5 200 400 μA 4.5 to 5.5 250 500 3.0 to 4.5 0.8 1.5 4.5 to 5.5 1.0 2.0 3.0 to 4.5 0.3 0.8 4.5 to 5.5 0.5 1.0 3.0 to 4.5 0.5 0.7 4.5 to 5.5 0.6 0.9 mA 3.0 to 4.5 1.0 1.5 4.5 to 5.5 1.2 1.8 3.0 to 4.5 1.8 2.5 4.5 to 5.5 2.0 3.0 Conditions VDD[V] min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting Continued on next page. No.A1795-15/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter Current drain during Intermittent for clock mode Symbol IDDCLOCK(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 IDDCLOCK(2) Conditions VDD[V] • Intermittent for clock mode • Each 500ms is shifted to a normal mode, and 20 steps are executed. • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • System clock set to 32.768kHz side. • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. 3.0 to 4.5 200 400 μA 4.5 to 5.5 250 500 min Specification typ max unit Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting UART(Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Clock rate Symbol UBR, UBR2 Pins/ Remarks UTX1(P32), RTX1(P33), UTX2(P33), RTX2(P34) 3.0 to 5.5 16/3 8192/3 tCYC Conditions VDD[V] min Specification typ max unit Data length: 7, 8, and 9 bits ( LSB first ) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: Non Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission UBR, UBR2 Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Start bit Start of reception Received data (LSB first) Stop bit End of reception UBR, UBR2 No.A1795-16/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Package Dimensions unit : mm (typ) 3151A 23.2 80 81 51 50 0.8 14.0 20.0 100 1 0.65 (0.58) (2.7) 31 30 0.3 0.15 3.0max 0.1 SANYO : QIP100E(14X20) 17.2 No.A1795-17/29 VREG VDD3 VSS3 PC4 PB0 PB1 PB2 PB3 PB4 PB5 NC NC NC NC NC NC 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PC3 PC2 PC1 PC0 Pin Assignment PC5/DBGP0 PB6 PB7 P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP PC6/DBGP1 PC7/DBGP2 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P07/T7O P06/T6O P05/CKO P04 P03 P02 P01 P00 VSS2 VDD2 PWM0 PWM1 SI2P3/SCK2O SI2P2/SCK2 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LC878496PB,LC8784C8PB LC8784G0PB,LC8784G1PB LC8784J2PB,LC8784J3PB LC8784M4PB,LC8784P6PB LC8784P7PB PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Top view VSS4 VDD4 SI2P0/SO2 SI2P1/SI2/SB2 SANYO: QIP100E (14×20) “Lead Free Product” No.A1795-18/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME PC5/DBGP0 PC6/DBGP1 PC7/DBGP2 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VSS4 VDD4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 SI2P0/SO2 SI2P1/SI2/SB2 PIN No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME SI2P2/SCK2 SI2P3/SCK2O PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P21/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P25/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P27/INT5/T1IN/T0LCP/T0HCP P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 VREG VSS3 VDD3 NC NC NC NC NC NC PC0 PC1 PC2 PC3 PC4 No.A1795-19/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB System Block Diagram CF1 CF2 CF Clock RC XT1 XT2 X'tal MRC generator Bus Interface Standby control Timer 0 IR RES Timer 1 ROM Timer 4 VREG Regulator Timer 5 PC VDD VSS Port 1 ACC Port 0 PLA Interrupt control Port 3 B register Port 7 C register SIO0 Port 8 ALU SIO1 ADC SIO2 INT0 to 3 noise rejection filter PSW PWM0 Port 2 INT4, 5, 6, 7 RAR PWM1 Port B RAM Base Timer Port C Stack pointer Timer 6 Port E Watchdog timer Timer 7 Port F UART1 PWM4 VREG operation UART2 PWM5 VDD operation No.A1795-20/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Pin Description Name VSS1 VSS2 VSS3 VSS4 VDD1 VDD2 VDD3 VDD4 Port 0 P00 P01 P02 P03 P04 P05 P06 P07 Port 1 P10 P11 P12 P13 P14 P15 P16 P17 23 24 25 26 27 28 29 30 57 58 59 60 61 62 63 64 I/O Pin No. 11 56 88 39 14 55 89 40 I/O • 8-bit I/O port • I/O specifiable in 4-bit units • Pull-up resistor can be turned on and off in 4-bit units • HOLD release input • Port 0 interrupt input • Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P10: SIO0 data output P11: SIO0 data input, bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input, bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output, beeper output Port 2 P20 P21 P22 P23 P24 P25 P26 P27 65 66 67 68 69 70 71 72 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Other functions P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT7 input/timer 0H capture 1 input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer0L capture input/ timer 0H capture input Interrupt acknowledge type • Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 Port 3 P30 P31 P32 P33 P34 P35 73 74 75 76 77 78 I/O • 6-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Pin functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Yes Yes • Power supply pin • Connect it with VDD No I/O • Power supply pin • Connect it with GND Function Description Option No Continued on next page. No.A1795-21/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Name Port 7 P70 P71 P72 P73 4 5 6 7 Pin No. I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units • Other functions P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer/ AD converter input port P71: INT1 input/HOLD release input/Timer 0H capture input/ AD converter input port P72: INT2 input/HOLD release input/Timer 0 event input/timer0L capture input P73: INT3 input with noise filter/Timer 0 event input/timer 0H capture input • Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 Port B PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Port C PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 Port E PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Port F PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 41 42 43 44 45 46 47 48 31 32 33 34 35 36 37 38 I/O • 8-bit I/O port • I/O specifiable in 2-bit units • Pull-up resistor can be turned on and off in 1-bit units No 96 97 98 99 100 1 2 3 I/O • 8-bit I/O port • I/O specifiable in 2-bit units • Pull-up resistor can be turned on and off in 1-bit units No 86 85 84 83 82 81 80 79 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units Yes 15 16 17 18 19 20 21 22 I/O • 8-bit I/O port • I/O specifiable in 1-bit units • Pull-up resistor can be turned on and off in 1-bit units Yes I/O enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Function Description Option No • 8-bit I/O port (Output: N-channel open drain) • I/O specifiable in 1-bit units • Other functions P80 to P87: AD converter input port Continued on next page. No.A1795-22/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Name SIO2 SI2P0 SI2P1 SI2P2 SI2P3 49 50 51 52 Pin No. I/O I/O • 4-bit I/O port • I/O specifiable in 1-bit units • Shared functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, bus input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 PWM1 RES XT1 54 53 8 9 I/O I/O I I • PWM0 output port • General-purpose I/O available • PWM1 output port • General-purpose I/O available • Reset pin Must connect it with VDD1 through RC (Refer to Page27 Figure 1) • Input terminal for 32.768kHz X'tal oscillation • Shared functions: General-purpose input port Must be set for input with software and connected to VSS1 if not to be used. XT2 10 I/O • Output terminal for 32.768kHz X'tal oscillation • Shared functions: General-purpose I/O port Must be set for general-purpose output and kept open if not to be used. Please connect suitable dumping resistance for the crystal used between the terminal when you use it as Output terminal for 32.768kHz X'tal oscillation. CF1 CF2 NC NC NC NC NC NC VREG 12 13 90 91 92 93 94 95 87 I O O • Input terminal for oscillation • Output terminal for oscillation • Please open the terminal • Please open the terminal • Please open the terminal • Please open the terminal • Please open the terminal • Please open the terminal • Internal low voltage output • Connect a bypass capacitor to this pin. (Refer to Page27) No No No No No No No No No No No No No No Function Description Option No No.A1795-23/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port P00 to P07 Options Selected in Units of 1 bit Option Type 1 2 P10 to P17 P20 to P27 P30 to P35 PB0 to PB7 PC0 to PC7 PE0 to PE7 PF0 to PF7 P70 P71 to P73 P80 to P87 SI2P0, SI2P2, SI2P3 PWM0, PWM1 SI2P1 XT1 XT2 No No No CMOS (when selected as ordinary port) N-channel open drain (When SIO2 data is selected) Input only Output for 32.768kHz quartz oscillator N-channel open drain (when in general-purpose output mode) No No No No No No No N-channel open drain CMOS N-channel open drain CMOS Programmable Programmable No No 1 bit 1 2 No CMOS N-channel open drain CMOS Programmable Programmable Programmable 1 bit 1 2 CMOS N-channel open drain CMOS N-channel open drain Output Type Pull-up Resistor Programmable (Note 1) No Programmable Programmable Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, AVSS and VSS4 pins. Example 1: When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup capacitors. Back-up capacitor Power Supply LSI VDD1 VDD2 VDD3 VDD4 VREG VSS1 VSS2 VSS3 VSS4 No.A1795-24/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Example 2: The high level output at the ports is unstable when the HOLD mode.backup is in effect. Back-up capacitor Power supply LSI VDD1 VDD2 VDD3 VDD4 VREG VSS1 VSS2 VSS3 VSS4 No.A1795-25/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB VDD1, VSS1 Terminal condition It is necessary to place capacitors between VDD1 and VSS1 as describe below. • Place capacitors as close to VDD1 and VSS1 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’). • Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. • Capacitance of C2 must be more than 0.1μF. • Please mount a suitable capacitor about C1. • Use thicker pattern for VDD1 and VSS1. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ VREG, VSS3 Terminal condition It is necessary to place capacitors between VREG and VSS3 as describe below. • Place capacitors as close to VREG and VSS3 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L4 = L4’). • Capacitance of C4 must be more than 1μF to 10μF. • Use thicker pattern for VREG and VSS3. L4 VSS3 C4 VREG L4’ No.A1795-26/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB VDDx, VSSx Terminal condition x=2 to 4 • It is necessary to place capacitors between VDDx and VSSx as describe below. • Place capacitors as close to VDDx and VSSx as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L5 = L5’). • Capacitance of C5 must be more than 0.1μF. • Use thicker pattern for VDDx and VSSx. L5 VSSx C5 VDDx L5’ VDD RRES (Note) Select CRES and RRES value to assure that reset is generated after the VDD becomes higher than the minimum operating voltage. Recommended value CRES: 0.47μF RRES: 270kΩ Figure 1 Reset Circuit RES CRES No.A1795-27/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 Data RAM transmission period (only SIO0, 2) DO8 tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH Data RAM transmission period (only SIO0, 2) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA Figure 2 Serial Input/Output Test Condition tPIL tPIH Figure 3 Pulse Input Timing Condition No.A1795-28/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2011. Specifications and information herein are subject to change without notice. PS No.A1795-29/29