LC895125W

Ordering number : EN*5241 CMOS LSI LC895125Q, 895125W CD-ROM Driver with On-Chip SCSI Interface and Subcode Functions Preliminary Functions CD-ROM ECC function, subcode read function, SCSI interface Package Dimensions unit: mm 3182-QIP128E [LC895125Q] Features • On-chip SCSI interface (with built-in SCAM selection register) • Supports 8× playback - Using ×16 80-ns DRAMs • Supports 4× playback - Using ×16 80-ns DRAMs or ×8 70-ns DRAMs • Transfer rates: 10 MB/s (synchronous), 5 MB/s (asynchronous) using ×16 80-ns DRAMs*1 • Transfer rates: 8.467 MB/s (synchronous), 4.2336 MB/s (asynchronous) using ×8 70-ns DRAMs*2 • Supports the connection of up to 32 Mb of buffer RAM (using DRAM) • The user can freely set the CD main channel, C2 flag, and other areas in buffer RAM. • Batch transfer function (transfers the CD main channel and C2 flag data in a single operation) • Multi-block transfer function (automatically transfers multiple blocks in a single operation) • High-speed transfer mode supports a 10-MB/s (synchronous) transfer rate using ×8 80-ns DRAMs • Subcode ECC function Note: 1. For speeds up to 8× speed, use a SCSI master clock frequency of 20 MHz. Note: 2. For speeds up to 4× speed, use a SCSI master clock frequency of 16.9344 MHz. SANYO: QIP128E unit: mm 3214-SQFP144 [LC895125W] Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistance (pins only) Symbol VDD max VI, VO Pd max Topr Tstg 10 seconds Ta = 25°C Ta = 25°C Ta ≤ 70°C Conditions SANYO: SQFP144 Ratings –0.3 to +7.0 –0.3 to VDD + 0.3 450 –30 to +70 –55 to +125 260 Unit V V mW °C °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 22896HA (OT) No. 5241-1/11 LC895125Q, 895125W Allowable Operating Ranges at Ta = –30 to +70°C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V DC Characteristics at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = –30 to +70°C Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output low level voltage Output low level voltage Input leakage current Pull-up resistance Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOL2 VOL3 IL RUP Applicable Pins* (See below) All input pins other than (1), (3), and XTALCK RESET, IO0 to IO15, D0 to D7, RD, CS, WR, WFCK, SBSO, SCOR (1) Input pins (3), ACK, and ATN IOH1 = –2 mA: All output pins except (2), (3), and XTALCK, IO0 to IO15, and D0 to D7 IOL1 = 2 mA: All output pins except (2), (3), and XTALCK, IO0 to IO15, and D0 to D7 IOL2 = 2 mA: INT1, INT0, and ZSWAIT (open-drain outputs with pull-up resistors) (2) IOL3 = 48 mA: DB0, to DB7, DBP, BSY, I/O, MSG, SEL, RST, REQ, C/D (3) VI = VSS, VDD: All input pins IO0 to IO15, D0 to D7, INT0, INT1, ZSWAIT –25 40 80 min 2.2 0.8 2.5 0.6 2.0 0.8 2.4 0.4 0.4 0.4 +25 160 typ max Unit V V V V V V V V V V µA kΩ SCSI Pin Input Characteristics Parameter Input threshold voltage Hysteresis width Symbol Vt + t1 Vt – t1 ∆Vtt1 VDD = 4.5 to 5.5 V VDD = 5.0 V Conditions min typ 1.60 0.80 0.41 1.11 0.49 max 2.00 Unit V V V Sample Recommended Oscillator Circuit R1 = 120 kΩ R2 = 47 Ω C1 = 30 pF Crystal oscillator frequencies: XTALCK0 = 16.9344 MHZ and XTALCK1 = 20 MHz or: R1 = 3.3 kΩ R2 = None C1 = 5 pF Crystal oscillator frequency: XTALCK0 = 33.8688 MHz If third harmonic overtones appear when using a 33.8688 MHz frequency with the recommended circuit example, consult with the manufacturer of the crystal element, since detailed values of the circuit constants will be influenced by the printed circuit board. No. 5241-2/11 LC895125Q, 895125W Block Diagram Note: 1. WFCK, SBSO, SCOR 2. BCK, SDATA, LRCK, C2PO 3. DB0 to DB7, DBP, BSY, MSG, SEL, RST, REQ, I/O, C/D 4. ACK, ATN 5. ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL 6. D0 to D7 7. IO0 to IO15 8. RA0 to RA16, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE Note: IO8 to IO15 and RA9 to RA16 are the same pins. No. 5241-3/11 LC895125Q, 895125W Pin Functions (LC895125Q) Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: 1. 2. 3. 4. Symbol VDD VSS0 RA5 RA6 RA7 RA8 RA9 (IO15) RA10 (IO14) VSS0 RA11 (IO13) RA12 (IO12) RA13 (IO11) RA14 (IO10) RA15 (IO9) RA16 (IO8) IO7 VSS0 IO6 IO5 IO4 IO3 IO2 IO1 IO0 VSS0 TEST0 TEST1 TEST2 TEST3 TEST4 ZRESET VDD VSS0 CSCTRL XTALCK0 XTAL0 VSS0 D0 D1 D2 D3 D4 D5 D6 D7 VSS0 ZSWAIT ZINT0 VDD ZINT1 Type P P O O O O B B P B B B B B B B P B B B B B B B P I I I I I I P P I I O P B B B B B B B B P O O P O Interrupt request output to the microcontroller (SCSI side. Set with a register.) WAIT signal output to the microcontroller Interrupt request output to the microcontroller (ECC side. Set with a register.) Microcontroller data signals Selects active-high or active-low for the microcontroller CS logic. Crystal oscillator input Crystal oscillator output LSI reset. The LSI is reset on a 0 input. Test pins. These pins must be connected to VSS0. Buffer RAM data I/O. The pin circuits include pull-up resistors. Buffer RAM data I/O. The pin circuit includes a pull-up resistor. Address outputs for the buffer RAM or data I/O pins The pin circuits include pull-up resistors. Address outputs for the buffer RAM or data I/O pins The pin circuits include pull-up resistors. Address outputs for the buffer RAM Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. Continued on next page. No. 5241-4/11 LC895125Q, 895125W Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Note: 1. 2. 3. 4. VSS0 VSS0 Symbol ZRD ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VSS0 X1EN XTALCK1 XTAL1 VDD VSS1 DB0 DB1 VSS1 DB2 DB3 VDD VSS1 DB4 DB5 VSS1 DB6 DB7 VSS1 DBP VSS1 ATN VDD BSY ACK VSS1 RST MSG VDD SEL C/D VSS1 REQ I/O VSS1 VDD VSS0 Type I I I I I I I I I I P I I O P P B B P B B P P B B P B B P B P B P B B P B B P B B P B B P P P NC P P SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection Selection pin that must be set to 1 when XTALCK1 is used. SCSI block oscillator circuit input. Selected by X1EN. SCSI block oscillator circuit output. Microcontroller register selection signals Microcontroller data read signal input Microcontroller data write signal input Register chip select signal from the microcontroller Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. Continued on next page. No. 5241-5/11 LC895125Q, 895125W Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Note: 1. 2. 3. 4. C2PO SDATA BCK LRCK MCK VSS0 EXCK WFCK SBSO VDD SCOR VSS0 ZRAS0 ZRAS1 ZCAS0 ZCAS1 ZOE ZUWE ZLWE VSS0 RA0 RA1 RA2 RA3 RA4 Symbol VSS0 Type P NC NC I I I I O P O I I P I P O O O O O O O P O O O O O Buffer RAM address signal outputs Buffer RAM RAS signal output pin 0 (Normally, pin 0 is used) Buffer RAM RAS signal output pin 1 Buffer RAM CAS signal output pin 0 (Normally, pin 0 is used) Buffer RAM CAS signal output pin 1 Buffer RAM output enable Buffer RAM upper write enable Buffer RAM lower write enable Subcode I/O Subcode I/O Outputs the XTALCK0 frequency, or that frequency divided by 2. CD DSP interface Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. No. 5241-6/11 LC895125Q, 895125W Pin Functions (LC895125W) Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: 1. 2. 3. 4. IO6 IO5 IO4 IO3 IO2 IO1 IO0 VSS0 TEST0 TEST1 TEST2 TEST3 TEST4 ZRESET VDD VSS0 VDD VSS0 CSCTRL XTALCK0 XTAL0 VSS0 D0 D1 D2 D3 D4 D5 D6 D7 Symbol VSS0 VDD VSS0 RA5 RA6 RA7 RA8 RA9 (IO15) RA10 (IO14) VSS0 RA11 (IO13) RA12 (IO12) RA13 (IO11) RA14 (IO10) RA15 (IO9) RA16 (IO8) IO7 VDD VSS0 Type P P P O O O O B B P B B B B B B B P P NC B B B B B B B P I I I I I I P P P P I I O P B B B B B B B B Microcontroller data signals Selects active-high or active-low for the microcontroller CS logic. Crystal oscillator input Crystal oscillator output LSI reset. The LSI is reset on a 0 input. Test pins. These pins must be connected to VSS0. Buffer RAM data I/O. The pin circuit includes a pull-up resistor. Buffer RAM data I/O. The pin circuit includes a pull-up resistor. Address outputs for the buffer RAM or data I/O pins The pin circuits include pull-up resistors. Address outputs for the buffer RAM or data I/O pins The pin circuits include pull-up resistors. Buffer RAM address signal outputs Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. Continued on next page. No. 5241-7/11 LC895125Q, 895125W Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Note: 1. 2. 3. 4. ATN VDD BSY ACK VSS1 RST MSG VDD VDD VSS1 DB4 DB5 VSS1 DB6 DB7 VSS1 DBP VDD VSS1 ZWR ZCS SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VSS0 X1EN XTALCK1 XTAL1 VSS0 VDD VSS1 DB0 DB1 VSS1 DB2 DB3 Symbol VSS0 ZSWAIT ZINT0 VDD VSS0 ZINT1 ZRD Type P O O P P O I NC I I I I I I I I I P I I O P P P B B P B B NC P P B B P B B P B P P NC B P B B P B B P SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection SCSI connection Selection pin that must be set to 1 when XTALCK1 is used SCSI block oscillator circuit input. Selected by X1EN. SCSI block oscillator circuit output Microcontroller register selection signals Microcontroller data write signal input Input for the register chip select signal from the microcontroller Interrupt request output to the microcontroller (SCSI side. Set with a register.) Microcontroller data read signal input WAIT signal output to the microcontroller Interrupt request output to the microcontroller (ECC side. Set with a register.) Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. Continued on next page. No. 5241-8/11 LC895125Q, 895125W Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Note: 1. 2. 3. 4. ZRAS0 ZRAS1 ZCAS0 ZCAS1 ZOE ZUWE ZLWE VSS0 RA0 RA1 RA2 RA3 RA4 VDD C2PO SDATA BCK LRCK MCK VSS0 EXCK WFCK SBSO VDD VSS0 SCOR VSS0 VSS0 VSS0 VSS0 Symbol SEL C/D VSS1 REQ I/O VSS1 VDD VSS0 VDD VSS0 Type B B P B B P P P P P NC P P P NC NC I I I I O P O I I P P I P NC O O O O O O O P O O O O O P Buffer RAM address signal outputs Buffer RAM RAS signal output pin 0 (Normally, pin 0 is used) Buffer RAM RAS signal output pin 1 Buffer RAM CAS signal output pin 0 (Normally, pin 0 is used) Buffer RAM CAS signal output pin 1 Buffer RAM output enable Buffer RAM upper write enable Buffer RAM lower write enable Subcode I/O Subcode I/O Outputs the XTALCK0 frequency, or that frequency divided by 2. CD DSP interface SCSI connection SCSI connection Function NC pins must be left open. Do not connect any signal to these pins. Pin names that start with Z are negative-logic signals. VSS0 is the logic system ground and VSS1 is the SCSI interface ground. Applications that use DRAM must insert resistors in the CAS and RAS lines, connect capacitors between these lines and ground, and take any other measures necessary to prevent undershoot in the DRAM related circuits. 5. Since these circuits include buffers that sink 48 mA, adequate noise prevention measures must be applied. No. 5241-9/11 LC895125Q, 895125W Pin Functions 1. SCSI Pins • BSY, ACK, MSG, SEL, REQ, ATN, I/O, C/D (input and output) SCSI bus control pins. • DB0 to DB7, DBPB (input and output) These are the SCSI data bus pins. 2. Microcontroller Interface Pins • ZCS (input) Microcontroller chip select line • CSCTRL (input) Microcontroller chip select logic selection signal High - ZCS is an active low signal. Low - ZCS is an active high signal. • ZRD, ZWR, SUA0 to SUA6 (input) Microcontroller interface control signal The SUA0 to SUA6 pins are used for addressing. • ZSWAIT (output) When the microcontroller accesses RAM, it must wait if this pin is low. This is a built-in pull-up resistor open-drain output. • D7 to D0 (input and output) Microcontroller data bus. Pull-up resistors are built in. • ZINT0, ZINT1 (output) Interrupt request output to the microcontroller. A SCSI-side interrupt can be output from ZINT1 by setting the C register (bit 7 in R11). This is a built-in pull-up resistor open-drain output. 3. Buffer RAM Pins • IO0 to IO15 (input and output) Buffer RAM data bus. Pull-up resistors are built in. The IO8 to IO15 pins have shared functions as the RA9 to RA16 pins. This means that 16-bit PSRAM cannot be used. • RA0 to RA16 (output) Buffer RAM address lines. RA9 to RA16 have shared functions as the IO8 to IO15 pins. This means that 16-bit PSRAM cannot be used. • ZRAS0, ZRAS1, (ZCS0), (ZCS1) (output) Buffer DRAM RAS outputs. Normally, ZRAS0 is used. However, when two 1-MB (64k × 16-bit) DRAM chips are used, the respective DRAM RAS pins are connected to ZRAS0 and ZRAS1. Connected to the CS pin if PSRAM is used. • ZCAS0, ZCAS1 (output) Buffer DRAM CAS outputs. Normally, ZCAS0 is used. However, when two 1-MB (64k × 16-bit) DRAM chips are used, the respective DRAM CAS pins are connected to ZCAS0. • ZOE (output) Buffer RAM read output signal • ZUWE, ZLWE (output) Buffer RAM write output signals. Connected to the corresponding pins on the RAM chip. Leave ZUWE open if an 8-bit RAM is used. 4. Subcode Interface Pins • EXCK, WFCK, SBSO, SCOR (input and output) Subcode interface pins. Connecting a CD DSP using these pins allows the LC895125 to read in subcode data and transfer it to the host. No. 5241-10/11 LC895125Q, 895125W 5. CD DSP Data Pins • BCK, SDATA, LRCK, C2PO (input) The LC895125 reads in CD-ROM data over these pins connected to a CD DSP. C2PO is the C2 flag pin. 6. Other Pins • ZRESET (input) Reset input to the LC895125. The LC895125 is reset by a low-level input. This pin must be held low for a period of at least 1 µs when power is first applied. • XTALCK0, XTAL0 The main clock for the ECC and SCSI blocks. These pins support frequencies from 16.9344 to 25 MHz. When a double-frequency input is used, these pins accept frequencies up to 38 MHz. Use a double-frequency input when a ceramic oscillator and DRAM are used. (This is because the internal clock must have a 50% duty.) An external clock may input to the XTALCK pin. The SCSI block main clock can also be provided from XTALCK1 and XTAL1 if so specified by the setting of X1EN (pin 89). • XTALCK1, XTAL1 The main clock for the ECC and SCSI blocks. These pins are enabled for oscillator operation by setting X1EN (pin 89). The LC895125 is designed so that the ECC and SCSI blocks can also be operated asynchronously. This means that precise 10-MB/s synchronous transfers can be achieved by providing a 20-MHz input to XTALCK1 and XTAL1. A ceramic oscillator may be used here since only the rising edge of this signal is used. In applications that do not use these pins, XTALCK1 must be tied to VSS and XTAL1 must be left open. • X1EN (input) Set this pin to 1 to us use XTALCK1 and XTAL1 for the SCSI block main clock. Set this pin to 0 to drive both the ECC and SCSI blocks from XTALCK0 and XTAL0. • MCK (output) Outputs either the XTALCK0 frequency or that frequency divided by 2. This pin’s output can also be stopped if desired. s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1996. Specifications and information herein are subject to change without notice. PS No. 5241-11/11