LC89962M

Ordering number : EN*5420 CMOS LSI LC89962, LC89962M NTSC Format Delay Line Overview The LC89962 and LC89962M are delay line circuits that provide a delayed signal by a 1H period of NTSC format with an external low-pass filter. Package Dimensions unit: mm 3001B-DIP8 [LC89962] Features • Requires only the input of a 3.58-MHz clock to produce a 1H delayed signal and the external low-pass filter. • Uses a 5-V single-voltage power supply. • Requires a minimal number of external components due to the peripheral components provided on chip. • Output signal has the same phase as the input signal. • Operation has a 4fsc clock synchronized with the input clock allows these products to be used as wide bandwidth delay lines. • A 4fsc clock can be output from the 4FSC pin (pin 7). Functions • • • • • • • 906-bit CCD shift register Timing generator and CCD driver circuits Auto-bias circuit Sync-tip clamp circuit Sample-and-hold and output amplifier circuits 4 × PLL circuit 4fsc output circuit unit: mm 3032B-MFP8 [LC89962M] SANYO: DIP8 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD LC89962 Pd max Topr Tstg LC89962M Conditions SANYO: MFP8 Ratings –0.3 to +6.0 400 140 –10 to +60 –55 to +125 Unit V mW mW °C °C SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5420-1/6 LC89962, LC89962M Allowable Operating Ranges at Ta = 25°C Parameter Supply voltage Clock input amplitude Clock frequency Signal input amplitude Symbol VDD VCLK FCLK VIN (*1) Sine wave Conditions min 4.75 200 typ 5.0 300 3.579545 500 572 max 5.25 500 Unit V mVp–p MHz mVp–p Note 1. The input signal must be input with low impedance for correct operation of sync-tip clamping. Electrical Characteristics at Ta = 25°C, VDD = 5.0 V, CLK = 3.579545 MHz; 300 mV p-p Switch states Parameter Supply current Voltage gain Frequency characteristics Differential gain Differential phase Linearity Clock leakage Noise Output impedance Delay time Symbol IDD GV Gf DG DP LS Lck NO ZO TD SW1 a a b a a a a a a a SW2 a b b a a a b b b b SW3 a a a a a a a a a↔b a Test conditions *1 *2 *3 *4 *4 *5 *6 *7 *8 *9 220 min 5 –2 –2 0 0 37 typ 15 0 –1 5 5 40 5 1 370 63.33 43 50 2 520 max 25 +2 0 Unit mA dB dB % deg % mVrms mVrms Ω µs Test Conditions 1. The supply current with no input signal 2. The following formula is used to calculate the voltage gain (GV). VOUT [mVp-p] GV = 20log ——————— [dB] 500 [mVp-p] Output signal symbol VOUT Input signal Sine wave: 200 kHz, 500 mV p-p 3. The following formula is used to calculate the frequency characteristics (Gf). V2 [mVp-p] Gf = 20log —————— [dB] V1 [mVp-p] Output signal symbol V1 V2 Input signal Sine wave: 200 kHz, 200 mV p-p Sine wave: 3.58 MHz, 200 mV p-p During this test, adjust Vbias so that the input signal DC level is 250 mV higher than the clamp level. No. 5420-2/6 LC89962, LC89962M 4. Measure the differential gain (DG) and differential phase (DP) using a vector scope with a 5-step function wave input. (See the following figure.) 5. To measure LS, input a 5-step function wave and measure the ratio of the sync level (S) to the luminance level (Y). S [mV] LS = ———— × 100 [%] Y [mV] 6. To measure clock leakage (Lck), measure the 4fsc (14.3 MHz) component in the output signal with a spectrum analyzer when no input signal is presented. 7. To measure the noise level (NO), measure the noise output in the OUT pin output when no input signal is present with a video noise meter. Set up the noise meter with a 200-kHz high-pass filter, a 4.2-MHz low-pass filter, and 3.58-MHz trap filter. 8. The following formula is used to calculate the output impedance (ZO). V1 [mVp-p] – V2 [mVp-p] ZO = ——————————— × 500 [Ω] V2 [mVp-p] Output signal symbol V1 V2 SW3 a b Sine wave: 200 kHz, 500 mV p-p Input signal 9. To measure the delay time (TD), measure the delay time of the output signal to the input signal. In this measurement, the delay time associated with the low-pass filter must be excluded. No. 5420-3/6 LC89962, LC89962M Pin Assignment Block Diagram No. 5420-4/6 LC89962, LC89962M Test Circuit Sample Application Circuit No. 5420-5/6 LC89962, LC89962M 4FSC (pin 7) Sample Application Circuit s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5420-6/6