LE28CV1001M

Ordering number : EN*5409 CMOS LSI LE28CV1001M, T-12/15 1MEG (131072 words × 8 bits) Flash Memory Overview The LE28CV1001M, T Series ICs are 1 MEG flash memory products that feature a 131072-word × 8-bit organization and 3.3 V single-voltage power supply operation. CMOS peripheral circuits are adopted for high speed, low power, and ease of use. A 128-byte page rewrite function provides rapid data rewriting. Package Dimensions unit: mm 3205-SOP32 [LE28CV1001M] Features • Highly reliable 2-layer polysilicon CMOS flash EEPROM process • Read and write operations using a 5 V single-voltage power supply • Fast access time: 120 and 150 ns • Low power dissipation — Operating current (read): 12 mA (maximum) — Standby current: 15 µA (maximum) • Highly reliable read/write —Erase/write cycles: 104/103 cycles —Data retention time: 10 years • Address and data latches • Fast page rewrite operation — 128 bytes per page — Byte/page rewrite time: 5 ms (typical) — Chip rewrite time: 5 s (typical) • Automatic rewriting using internally generated Vpp • Rewrite complete detection function — Toggle bit — Data polling • Hardware and software data protection functions • All inputs and outputs are TTL compatible. • Pin assignment conforms to the JEDEC byte-wide EEPROM standard. • Package SOP 32-pin (525 mil) plastic package:LE28CV1001M TSOP 32-pin (8 × 20 mm) plastic package:LE28CV1001T SANYO: SOP32 unit: mm 3224-TSOP32 [LE28CV1001T] SANYO: TSOP32 (TYPE-I) These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 93096HA (OT) No. 5409-1/14 LE28CV1001M, T-12/15 Block Diagram Pin Assignments Pin Functions Symbol A16 to A0 Address input Pin Function Supply the memory address to these pins. The address is latched internally during a write cycle. These pins output data during a read cycle and input data during a write cycle. Data is latched internally during a write cycle. Outputs go to the high-impedance state when either OE or CE is high. The device is active when CE is low. When CE is high, the device becomes unselected and goes to the standby state. Makes the data output buffers active. OE is a low-active input. Makes the write operation active. WE is an active-low input. Apply 3.3 V ±0.3 to this pin. DQ7 to DQ0 Data input and output CE OE WE VDD VSS N.C. Chip enable Output enable Write enable Power supply Ground No connection These pins must be left open. No. 5409-2/14 LE28CV1001M, T-12/15 Function Logic Mode Read Write Standby Write inhibit CE VIL VIL VIH X X OE VIL VIH X VIL X WE VIH VIL X X VIH AIN AIN X X X A16 to A10 = VIL, A8 to A1 = VIL, Product identification VIL VIL VIH A9 = 12 V, A0 = VIL A16 to A10 = VIL, A8 to A1 = VIL, A9 = 12 V, A0 = VIH A16 to A0 DOUT DIN High-Z High-Z/DOUT High-Z/DOUT Manufacturer code (BF) DQ7 to DQ0 Device code (07) Software Data Protection Command Byte sequence Write 0 Write 1 Write 2 Write 3 Write 4 Write 5 Note: Address format A14 to A0 (hex.) Set protection Address 5555 2AAA 5555 Data AA 55 A0 Reset protection Address 5555 2AAA 5555 5555 2AAA 5555 Data AA 55 80 AA 55 20 Software Product ID Entry Command and Exit Command Codes Byte sequence Write 0 Write 1 Write 2 Write 3 Write 4 Write 5 Protect ID Entry Address 5555 2AAA 5555 5555 2AAA 5555 Data AA 55 80 AA 55 60 Protect ID Exit Address 5555 2AAA 5555 Data AA 55 F0 Notes on software Product ID Command Code: 1. Command Code Address format: A14 to A0 (hex.) 2. With A14 to A1 = VIL, Manufacturer Code is read with A0 = VIL to be BFH LE28CV1001M, T Device Code is read with A0 = VIH to be 07H 3. The device does not remain in Software Product ID Mode if powered down. 4. A16 and A15 at VIH or VIL. No. 5409-3/14 LE28CV1001M, T-12/15 Device Operation This Sanyo 1 MEG flash memory allows electrical rewrites using a 3.3 V single-voltage power supply. The LE28CV1001M, T series products are pin and function compatible with the industry standards for this type of product. Read The LE28CV1001M, T series products read operations are controlled by CE and OE. The host must set both pins to the low level to acquire the output data. CE is used for chip selection. When CE is at the high level, the chip will be in the unselected state and only draw the standby current. OE is used for output control. The output pins go to the highimpedance state when either CE or OE is high. See the timing waveforms (Figure 1) for details. Page Write Operation The write operation starts when both CE and WE are at the low level, and furthermore OE is at the high level. The write operation is executed in two stages. The first stage is a byte load cycle in which the host writes to the LE28CV1001M, T series products internal page buffer. The second stage is an internal programming cycle in which the data in the page buffer is written to the nonvolatile memory cell array. In the byte load cycle, the address is latched on the falling edge of either CE or WE, whichever occurs later. The input data is latched on the rising edge of either CE or WE, whichever occurs first. The internal programming cycle starts if either WE or CE remains high for 200 µs (t ). Once this programming cycle starts, the operation continues until the programming operation is completely done. This operation executes within 5 ms (typical). Figures 2 and 3 show the WE and CE control write cycle timing diagrams, and Figure 9 shows the flowchart for this operation. In the page write operation, 128 bytes of data can be written to the LE28CV1001M, T series products internal page buffer before the internal programming cycle. All the data in the page buffer is written to the memory cell array during the 5 ms (typical) internal programming cycle. Therefore the LE28CV1001M, T series products page write function can rewrite all memory cells in 5 seconds (typical). The host can perform any other activities desired, such as moving data at other locations within the system and preparing the data required for the next page write, during the period prior to the completion of the internal programming cycle. In a given page write operation, all the data bytes loaded into the page buffer must be for the same page address specified by address lines A7 through A16. All data that was not explicitly loaded into the page buffer is set to FFH. Figure 2 shows the page write cycle timing diagram. If the host loads the second data byte into the page buffer within the 100 µs byte load cycle time (t ) after the first byte load cycle the LE28CV1001M, T series products stop in the page load cycle thus allowing data to be loaded continuously. The page load cycle terminates if additional data is not loaded into the internal page buffer within 200 µs (t ) after the previous byte load cycle, as in the case where WE does not switch from high to low after the last WE rising edge. The data in the page buffer can be rewritten in the next byte load cycle. The page load period can continue indefinitely as long as the host continues to load data into the device within the 100 µs byte load cycle. The page that is loaded is determined by the page address of the last byte loaded. BLCO BLC BLCO Detecting the Write Operation State The LE28CV1001M, T series products provide two functions for detecting the completion of the write cycle. These functions are used to optimize the system write cycle time. These functions are based on detecting the states of the Data polling bit (DQ7) and the toggle bit (DQ6). Data Polling (DQ7) The LE28CV1001M, T series products output to DQ7 the inverse of the last data loaded during the page and byte load cycles when the internal programming cycle is in progress. The last data loaded will be read from DQ7 when the internal programming cycle completes. Figure 4 shows the Data polling cycle timing diagram and Figure 10 shows the flowchart for this operation. No. 5409-4/14 LE28CV1001M, T-12/15 Toggle Bit (DQ6) Data values of 0 and 1 are output alternately for DQ6, that is DQ6 is toggled between 0 and 1, during the internal programming cycle. When the internal programming cycle completes this toggling is stopped and the device becomes ready to execute the next operation. Figure 5 shows the toggle bit timing diagram and Figure 10 shows the flowchart for this operation. Data Protection Hardware Data Protection Noise and glitch protection: The LE28CV1001 does not execute write operations for WE or OE pulses that are 15 ns or shorter. Power (VDD) on and cutoff detection: The programming operation is disabled when VDD is 2.5 V or lower. Write inhibit mode: Writing is disabled when OE is low and either CE is high or WE is high. Use this function to prevent writes from occurring when the power is being turned on or off. Software Data Protection The LE28CV1001 implements the optional software data protection function recognized by JEDEC. This function requires that a 3-byte load operation to be performed before a write operation data load. The 3-byte load sequence starts a page load cycle without activating any write operation. Thus this is an optimal protection scheme for unintended write cycles triggered by noise associated with powering the chip on or off. Note that the LE28CV1001 is shipped with the software data protection function disabled. The software data protection circuit is activated by executing a 3-byte byte load cycle in advance of the data sequence in the page load cycle. (See Figure 6.) This causes the device to automatically enter data protection mode. After this, write operations require a 3-byte byte load cycle to be executed in advance. A 6-byte write sequence is required to switch the device out of this protection mode. Figure 7 shows the timing diagram. If a write operation is attempted in software protection mode, all device functions are disabled for 200 µs. Figure 11 shows the flowchart for this operation. Product Identification The device identification code is used for recognizing the device and its manufacturer. This mode can be used by hardware and software. The hardware operating mode is used to recognize algorithms that match the device when an external programming unit is used. Also, user systems can recognize the product number using software product identification mode. Figure 12 shows the flowchart for this operation. The manufacturer and device codes are the same in both modes. No. 5409-5/14 LE28CV1001M, T-12/15 Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Input pin voltage DQ pin voltage A9 pin voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD VIN VOUT VA9 Pd max Topr Tstg Ratings –0.5 to +6.0 –0.5 to VDD + 0.5 –0.5 to VDD + 0.5 –0.5 to +14.0 600 0 to +70 –65 to +150 Unit V V V V mW °C °C Note 1 1, 2 1, 2 1, 3 1, 4 1 1 Notes:1. The device may be destroyed by the application of stresses in excess of the absolute maximum ratings. 2. –1.0 V to VDD + 1.0 V for pulses less than 20 ns 3. –1.0 V to +14 V for pulses less than 20 ns DC Recommended Operating Ranges at Ta = 0 to +70°C Parameter Supply voltage Input low-level voltage Input high-level voltage Symbol VDD VIL VIH 2.0 min 3.0 typ 3.3 max 3.6 0.6 Unit V V V DC Electrical Characteristics at Ta = 0 to +70°C, VDD = 3.3 V ± 0.3 V Parameter Current drain during read Current drain during write TTL standby current CMOS standby current Input leakage current Output leakage current Output low-level voltage Output high-level voltage Symbol ICCR ICCW ISB1 ISB2 ILI ILO VOL VOH Conditions CE = OE = VIL, WE = VIH, all DQ pins open, address inputs = VIH or VIL, operating frequency = 1/tRC (minimum), VDD = VDD max CE = WE = VIL, OE = VIH, VDD = VDD max CE = OE = WE = VIH, VDD = VDD max CE = OE = WE = VDD – 0.3 V, VDD = VDD max VIN = VSS to VDD, VDD = VDD max VIN = VSS to VDD, VDD = VDD max IOL = 2.1 mA, VDD = VDD min IOH = –400 µA, VDD = VDD min 2.4 min typ max 12 15 1 20 10 10 0.4 Unit mA mA mA µA µA µA V V Input/Output Pin Capacitances at Ta = 25°C, VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Input/output capacitance Input capacitance Symbol CDQ CIN VDQ = 0 V VIN = 0 V Conditions max 12 6 Unit pF pF Power on Timing Parameter Time from power on until first read operation Time from power on until first write operation Symbol tPU-READ tPU-WRITE Conditions max 100 5 Unit µs ms No. 5409-6/14 LE28CV1001M, T-12/15 AC Electrical Characteristics at Ta = 0 to +70°C, VDD = 3.3 V ± 0.3 V AC Testing Conditions (See Figure 8) Input rise and fall time: ..................10 ns (max.) Output load: ....................................1 TTL gate + 30 pF Read Cycle LE28CV1001M, T Parameter Symbol min Read cycle time CE access time Address access time OE access time Output low-impedance time from CE Output low-impedance time from OE Output high-impedance time from CE Output high-impedance time from OE Output valid time from address input tRC tCE tAA tOE tCLZ tOLZ tCHZ tOHZ tOH 0 0 0 50 50 0 120 120 120 80 0 0 50 50 -12 max min 150 150 150 90 -15 max ns ns ns ns ns ns ns ns ns Unit Page Write Cycle Parameter Write cycle time (erase and program) Address setup time Address hold time CE setup time CE hold time OE setup time OE hold time CE pulse width WE pulse width Data setup time Data hold time Byte load cycle time Byte load time out time Note: * typ is reference value at VDD = 3.3 V and Ta = 25°C Symbol tWC tAS tAH tCS tCH tOES tOEH tCP tWP tDS tDH tBLC tBLCO 0 100 0 0 0 0 120 120 100 0 0.10 200 100 min typ* 5 max 10 Unit ms ns ns ns ns ns ns ns ns ns ns µs µs Figure 1 Read Cycle No. 5409-7/14 LE28CV1001M, T-12/15 Figure 2 WE Control Page Write Cycle Figure 3 CE Control Page Write Cycle No. 5409-8/14 LE28CV1001M, T-12/15 Figure 4 Data Polling Figure 5 Toggle Bit Figure 6 Enable Software Data Protection No. 5409-9/14 LE28CV1001M, T-12/15 Figure 7 Disable Software Data Protection Figure 8 AC I/O Reference Waveform No. 5409-10/14 LE28CV1001M, T-12/15 Figure 9 Write Algorithm No. 5409-11/14 LE28CV1001M, T-12/15 Figure 10 Write Operating State Detection No. 5409-12/14 LE28CV1001M, T-12/15 Figure 11 Software Data Protection Flowcharts No. 5409-13/14 LE28CV1001M, T-12/15 Figure 12 Product ID Flowcharts s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use:  Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. No. 5409-14/14