LV1115

Ordering number : EN8263A Bi-CMOS IC LV1115/M Overview Surround Processor ICs for Electronic Volume Control The LV1115/M are a sound processor ICs developed for use in TV sets. They incorporate surround processing function (AViSS), pseudo stereo function, auto gain control, and the major functional blocks of an electronic volume control IC. Features • Input gain control (-9dB, -6dB, 0dB, 4dB, 6dB: 5 positions) • AViSS (ON/OFF/6-stage level control) • Tone control (BASS: ±20dB, TREBLE: ±18dB [in 2dB steps]) • Master volume control (0dB to -14dB: 1dB steps/-14dB to -80dB: 2dB steps/-∞ = -82dB) • Balance control • Through mode/MUTE mode • Pseudo stereo function (ON/OFF/MONO control) • Auto gain control function • I2C bus control Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max Pd max1 Pd max2 Topr Tstg Ta ≤ 70°C *, DIP Ta ≤ 70°C *, MFP Conditions Ratings 10.5 700 450 -25 to +70 -40 to +125 Unit V mW mW °C °C Note *: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 11608 TI IM B8-8522, 8618 / 92706 / 31005 YY PC No.8263-1/15 LV1115/1115M Operating Condtions at Ta = 25°C Parameter Recommended supply voltage Operating supply voltage 1 Operating supply voltage 2 Control data “H” level voltage “L” level voltage Pulse width Hold time Operating frequency VIH VIL tφw thold fopg 2.0 to 3.3 0.0 to 1.0 1.0 1.0 100 V V μs μs kHz Symbol VCC VCC opg1 VCC opg2 DIP MFP Conditions Ratings 9.0 8.0 to 10.0 8.0 to 9.0 Unit V V V Electrical Characteristics at Ta = 25°C, VCC = 9.0V, fin = 1kHz, VIN = 300mVrms = 0dB, RL = 10kΩ (Output=L/R-VROUT, VCA circuit though) Parameter Quiescent current Symbol ICCO Conditions Ratings min typ 50 max Unit mA Total through (Total through mode, Volume control: 0dB) Voltage gain Maximum output voltage Total harmonic distortion Output noise voltage Cross talk VGT VOT THDT VNOT CTT VGF VOM THDM VNOM CTM VOS THDS VNOS VOS THDS VNOS VOS THDS VNOS GeqB EstepB GeqT EstepT Max. Boost/Cut THD=1% DIN AUDIO DIN AUDIO DIN AUDIO 80 THD=1% DIN AUDIO DIN AUDIO DIN AUDIO 80 -1.5 2.00 -0.5 2.45 0.01 -94 90 0.1 -85 +0.5 dB Vrms % dBV dB Matrix through (Matrix mode, Volume control: 0dB) Voltage gain Maximum output voltage Total harmonic distortion Output noise voltage Cross talk MONO mode (MONO mode, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.50 1.85 0.05 -92 0.5 -85 Vrms % dBV -1.6 1.50 -0.6 1.85 0.05 -92 90 0.1 -85 +0.6 dB Vrms % dBV dB Surround (Surround mode-A, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.50 1.85 0.26 -90 0.5 -80 Vrms % dBV Pseudo stereo (Pseudo mode, Volume control: 0dB) Maximum output voltage Total harmonic distortion Output noise voltage THD=1% DIN AUDIO DIN AUDIO 1.50 1.85 0.06 -92 0.5 -85 Vrms % dBV Bass band EQR (Matrix through mode, Volume control: 0dB) Control range Step resolution Max. Boost/Cut ±17 1.0 ±20 2.0 ±23 3.0 dB dB Treble band EQR (Matrix through mode, Volume control: 0dB) Control range Step resolution ±15 1.0 ±18 2.0 ±21 3.0 dB dB Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or input signal level. No.8263-2/15 LV1115/1115M Package Dimensions unit : mm (typ) 3067B 21.0 24 13 0.9 0.95 3.9 max 3.3 (0.71) 0.51min (3.25) 1.78 0.48 SANYO : DIP24S(300mil) Package Dimensions unit : mm (typ) 3112B 12.5 24 13 5.4 7.6 1 1.0 (0.75) 0.35 12 0.15 SANYO : MFP24S(300mil) 0.1 (1.5) 1.7max 0.63 0.25 1 12 7.62 6.4 No.8263-3/15 SCL Block Diagram I2C BUS Control Signal SDA Lch-IN L-DC1 HPFC 21 15 14 DET TONE CONT DC DC DATA CONTROL CONTROL + Matrix Bypass Bypass P Stereo tSU:STA ST-2 20 13 19 18 17 16 L-TC1 L-BC L-BC L-DC2 L-VROUT CLK DATA 24 23 22 AVL TOTAL MUTE + SURROUND Pseud Stereo (AViSS) SURROUND Bypass Bypass Matrix MUTE DC TONE CONT DC TOTAL SURROUND ANALOG P Stereo DET OUT tHD:STA AVL + + - tLOW tHIGH tR tHD:DAT LV1115/1115M tF tSU:DAT Figure 1. I2C BUS Control Signal timing chart 1 2 3 R-DC1 ST-1 Rch-IN 4 LPFC 5 6 R-TC1 7 R-BC 8 R-BC R-DC2 9 L-VROUT 10 11 VREF VCC 12 GND tSU:STO tBUF No.8263-4/15 LV1115/1115M I2C BUS register 1) The explanation of I2C Bus I2C Bus (Inter IC Bus) is the bus system which the PHILIPS company developed. It does controls such as the start, the stop by two control signals of SDA (Serial Data) and SCL (Serial Clock). The output of each signal is open drain and forms out of wired OR. S: Start condition P: Stop condition ACK: Acknowledge Data is transmitted in the MSB first. 1 unit is composed of 8 bits and ACK is put back from the slave to confirm. Slave IC reads data with rising edge of SCL. Master IC changes data by falling edge in SCL. 2) The control register Table1 Slave Address MSB 1 1 1 0 1 1 1 LSB 0 Note; LV1115/M are reception exclusive use. It depends and it uses LSB by the "0" fixation. Table2 I2C Bus transmission Function Input Gain/AVL (On-Off) control Volume control AVL detection level/Surround/MODE control Tone control [Bass] Tone control [TREBLE] AVL CONTROL Sub Address BINARY 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 HEX 01 02 03 04 05 06 0 0 0 D7 0 D6 0 D5 D4 Gain Volume Surround 0 0 0 0 0 Bass TREBLE AVL SLOPE MODE Data D3 D2 D1 AVL MODE D0 Channel AVL DET LEVEL 0 0 0 Table3 AVL MODE Sub Address A7 Mute AVL ON AVL OFF Mute Mute 0 0 0 0 0 0 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 D6 0 0 0 0 0 D5 * * * * * D4 * * * * * Data D3 * * * * * D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 No.8263-5/15 LV1115/1115M Table4 Gain control Sub Address A7 -9dB -6dB 0dB +4dB +6dB 0 0 0 0 0 0 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 D6 0 0 0 0 0 D5 0 0 0 1 1 D4 1 1 0 1 1 Data D3 1 0 0 0 1 D2 * * * * * D1 * * * * * D0 * * * * * Table5 Mode control Sub Address A7 Bypass (Total) Matrix Mono Pseudo Stereo 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 * * * * D6 * * * * D5 * * * * D4 * * * * Data D3 * * * * D2 * * * * D1 0 0 1 1 D0 0 1 0 1 Table6 Surround control Sub Address A7 OFF MODE-C MODE-B MODE-A MODE-F MODE-E MODE-D * * * 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 * * * * D6 * * * * D5 * * * * D4 0 0 0 0 1 1 1 Data D3 0 1 1 0 1 1 0 D2 0 1 0 1 1 0 1 * * D1 * * * * D0 * * * * Note: At the time of forced mono mode, there is not Surround effect. Note: Output gain = Step1 < Step7 Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or input signal level. Table7 AVL DETECTION LEVEL Sub Address A7 OFF 100mV 200mV 300mV 400mV 500mV 600mV 700mV 0 0 0 0 0 0 1 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 1 1 1 1 D6 0 0 1 1 0 0 1 1 D5 0 1 0 1 0 1 0 1 D4 * * * * * * * * Data D3 * * * * * * * * D2 * * * * * * * * D1 * * * * * * * * D0 * * * * * * * * Table8 AVL SLOPE Sub Address A7 LEVEL1 LEVEL2 LEVEL3 LEVEL4 LEVEL5 LEVEL6 0 0 0 0 0 1 1 0 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 D6 0 0 0 0 0 0 D5 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 Data D3 0 D2 0 0 0 0 1 1 D1 0 0 1 1 0 0 D0 0 1 0 1 0 1 No.8263-6/15 LV1115/1115M Table9 Tone control [Bass control] Sub Address A7 +20dB +18dB +16dB +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB 0 0 0 0 0 1 0 0 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Data D3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D2 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 D1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or input signal level. Table10 Tone control [TREBLE control] Sub Address A7 +18dB +16dB +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB 0 0 0 0 0 1 0 1 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Data D3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D2 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note: The output wave form becomes big depending on the surround or tone control setting. Please make sure the output waveform is not distorted. If the waveform is distorted, reduce the gain setting of surround, tone control, or input signal level. No.8263-7/15 LV1115/1115M Table11 Volume control Sub Address A7 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB -32dB -34dB -36dB -38dB -40dB -42dB -44dB -46dB -48dB -50dB -52dB -54dB -56dB -58dB -60dB -62dB -64dB -66dB -68dB -70dB -72dB -74dB -76dB -78dB -80dB -∞dB 0 0 0 0 0 0 1 0 A6 A5 A4 A3 A2 A1 A0 D7 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * D6 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 No.8263-8/15 LV1115/1115M Table12 Volume channel control Sub Address A7 L-ch R-ch L/R 0 0 0 0 0 0 1 0 A6 A5 A4 A3 A2 A1 A0 D7 0 1 1 D6 1 0 1 D5 * * * D4 * * * Data D3 * * * D2 * * * D1 * * * D0 * * * Pin Functions Pin No 1 2 GND INPUT-R Function 0 VREF Input Impedance ri=25kΩ 23 INPUT-L Voltage Internal equivalent circuit Remarks 3 9 16 22 4 DC1 Cut(R) DC2 Cut(R) DC2 Cut(L) DC1 Cut(L) ST-1 VREF DC offset cancellation capacitor connection pin VREF Pseudo stereo phase shift capacitor connection pin 21 ST-2 4 21 5 AViSS LPF VREF Capacitor connection pin for surround low pass filter 6 TREBLE(R) VREF Capacitor connection pin for configuring treble filter 19 TREBLE(L) 7 BASS-1(R) VREF Bass band filter configuration capacitor and resistor connection pins 8 BASS-1(L) 17 BASS-2(R) 18 BASS-2(L) Continued on next page. No.8263-9/15 LV1115/1115M Continued from preceding page. Pin No 10 Function EVR-OUT(R) Voltage VREF ro=500Ω Internal equivalent circuit Output Impedance Remarks 15 EVR-OUT(L) 10 15 11 VREF 0.5 VCC Reference voltage 12 13 VCC I2C-DATA VCC 0/Hi-Z I2C control data input 13 14 I2C-CLK 0/Hi-Z I2C control data input 20 AViSS HPF VREF 20 24 DET-OUT 4.5V AVL DET OUT No.8263-10/15 LV1115/1115M Treble / Bass Band Block Equivalent Circuit Diagram From L-Input Block + SW2 SW1 0dB ±2dB ±4dB ±6dB ±8dB ±10dB ±12dB ±14dB ±16dB ±18dB R1=10.633kΩ R2=8.446kΩ R3=6.709kΩ R4=5.329kΩ R5=4.233kΩ R6=3.363kΩ R7=2.671kΩ R8=2.122kΩ R9=1.665kΩ R10=6.510kΩ Total=51.7kΩ 0dB ±2dB ±4dB ±6dB ±8dB ±10dB ±12dB ±14dB ±16dB ±18dB ±20dB R12=100Ω L-TC1 L-BC2 R1=15.220kΩ R2=12.089kΩ R3=9.603kΩ R4=7.628kΩ R5=6.059kΩ R6=4.813kΩ R7=3.823kΩ R8=3.037kΩ R9=2.412kΩ R10=1.916kΩ R11=100Ω Total=66.7kΩ SW4 SW1 SW3 + SW2 SW4 SW3 To L-OUT Block L-BC1 During boost, SW1 and SW3 are ON, during cut, SW2 and SW4 are ON, when 0dB, 0dBSW and SW2 and SW3 are ON. Tone Circuit Constant Calculation Examples Treble Band Circuit: The shelving characteristics can be obtained for the treble band. The equivalent circuit and calculation formula during boost are indicated below. • Calculation example 1: Specification Set frequency: f = 24000Hz Gain during maximum boost: G+18dB = 17.5dB Let us use R1 = 6.51kΩ and R2 = 45.19kΩ The above constants are inserted in the following formula R2 R12+(1/ ω C)2 1 C= 2πf R2 10G/20-1 2 + R2 R1 C G = 20 × Log10 1+ -R12 1 = 2π24000 45190 7.50 - 1 2 - 65102 ≈2700 (pF) No.8263-11/15 LV1115/1115M Bass Band Circuit: The equivalent circuit and the formula for calculating the external RC with a mean frequency of 100Hz are shown below. • Calculation example 1: specification Mean frequency: f0 = 100Hz Gain during maximum boost: G+20dB = 20dB Let us use R1 = 0kΩ and R2 = 66.7kΩ, and C1 = C2 = C. We obtain R2 from G = 20dB C1 C2 + R1 R2 G = 20 × Log10 1+ R2 2R3 66700 2 (10 - 1) R3 R3 = R2 2 (10 G+20dB/20 - 1) = ≈3.6kΩ We obtain C from mean frequency f0 = 100Hz f0 = 2π 2πf0 1 (R3R2C1C2) 1 R3R2 = 2π × 100 1 66700 × 3600 ≈0.1μF C= We obtain Q Q= R3R2 2R3 × 1 R3R2 ≈2.15 Note item when using (1) When turning on the power, the setting inside is unsettled. Before setting control data, it does a mute. (2) To prevent the digital noise of the high frequency influence a terminal (SCL, SDA). It can be protected by a signal line in the ground pattern or by the shielding cable. (3) To prevent the noise in changing a mode, please set the mute ON. Sample Application Circuit 3.6k 0.068 F 2700pF 0.1 F 4.7 F 4.7 F 0.1 F 0.1 F 1F 1F 1F 1F 47 F 47 F 1F 4.7 F 0.1 F 0.01 F 4.7 F 0.1 F 5600pF 2700pF 3.6k No.8263-12/15 LV1115/1115M Volume control Characteristics [Vcc = 9.0V / fin = 1kHz / Vin = 0dBV / Total Mode] 10 8 6 4 2 0 -2 -4 -6 -8 -10 Gain control Characteristics [Vcc = 9.0V / fin = 1kHz / Vin = -10dBV / Matrix Mode] -10 -30 -50 -70 -90 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Volume setting (dB) Vout (dB) Vout (dB) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 Gain setting (dB) Bass Band Freq. Characteristics (Vcc=9.0V / Vin=-20dBV / C=0.1μF / R=3.6kΩ ) 0 -5 -10 Vout (dBV) Vout (dBV) -15 -20 -25 -30 -35 -40 -45 10 100 fin (Hz) 1000 10000 0 -5 -10 -15 -20 -25 -30 -35 -40 10 Treble Band Freq. Characteristics (Vcc=9.0V / Vin=-20dBV / C=2700pF) 100 1000 fin (Hz) 10000 100000 Surround Mode Freq. Characteristics (Vcc=9.0V / Vin=-10dBV) 5 0 Vout (dBV) -5 -10 -15 10 100 fin (Hz) 1000 10000 Mode-A Mode-B Mode-C Mode-D Mode-E Mode-F Phase (Deg.) 360 270 180 90 0 10 Pseudo mode Lch - Rch Phase Characteristics [Vcc = 9.0V / Vin = -10dBV] 100 fin (Hz) 1000 10000 AVL Function Characteristics [Vcc=9.0V, fin=1kHz, Det.level = 100mV setting] 400 1100 Vout (mVrms) Level 2 200 100 0 0 400 800 1200 1600 2000 Vin (mVrms) Level 3 Level 4 Level 5 Level 6 500 0 Vout (mVrms) 300 Level 1 AVL Function Characteristics [Vcc=9.0V, fin=1kHz, Det.level = 700mV setting] Level 1 Level 2 Level 3 800 Level 4 Level 5 Level 6 400 800 1200 1600 2000 Vin (mVrms) No.8263-13/15 LV1115/1115M AVL Function Characteristics [Vcc=9.0V, fin=1kHz, Slope.level = 1] 800 700 Vout (mVrms) 600 500 400 300 200 100 0 0 400 800 1200 1600 2000 Vin (mVrms) Det.100 Det.300 Det.400 Det.500 Det.600 Det.700 Vout (mVrms) Det.200 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 AVL Function Characteristics [Vcc=9.0V, fin=1kHz, Slope.level = 6] Det.100 Det.200 Det.300 Det.400 Det.500 Det.600 Det.700 400 800 1200 1600 2000 Vin (mVrms) Vin - THD Characteristics (Vcc=9.0V, fin=1kHz, [VR / Bass / Treble setting=0dB]) 1 Total THD (%) Matrix Mono 0.01 Pseudo Pseudo Surround 10 1 0.1 0.01 0.001 -40 -35 -30 -25 -20 -15 -10 -5 Vin (dBV) 0 5 Vcc - THD Characteristics (fin=1kHz, Vin=-10dBV, [VR / Bass / Treble setting=0dB]) THD (%) 0.1 Total Matrix Mono Pseudo Pseudo Surround 0.001 8 8.5 9 9.5 10 10.5 Vcc (V) fin - THD Characteristics (Vcc=9.0V, Vin=-10dBV, [VR / Bass / Treble setting=0dB]) 10 1 THD (%) 0.1 0.01 0.001 100 Total Mono Pseudo Pseudo Surround THD (%) Matrix Vcc - Vomax Characteristics (fin=1kHz, [VR / Bass / Treble setting=0dB / Surround mode=A]) 3.0 Total Matrix Mono 2.0 Pseudo Pseudo Surround 2.5 1.5 1000 fin (Hz) 10000 8 8.5 9 9.5 10 10.5 fin (Hz) AVL Function THD Characteristics [Vcc=9.0V, fin=1kHz, Slope.level = 1] 10 Det.100 THD (%) THD (%) 1 Det.200 Det.300 Det.400 0.1 Det.500 Det.600 Det.700 0.01 0 400 800 1200 1600 2000 Vin (mVrms) 0.01 0 1 10 AVL Function THD Characteristics [Vcc=9.0V, fin=1kHz, Slope.level = 6] Det.100 Det.200 Det.300 Det.400 0.1 Det.500 Det.600 Det.700 400 800 1200 1600 2000 Vin (mVrms) No.8263-14/15 LV1115/1115M VCC - ICCO Characteristics 60.0 5.5 VCC - VREF Reg. Characteristics 5.0 ICCO (mA) VREF (V) 55.0 4.5 50.0 4.0 45.0 8.0 8.5 9.0 Vcc (V) 9.5 10.0 10.5 3.5 8.0 8.5 9.0 Vcc (V) 9.5 10.0 10.5 SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of January, 2008. Specifications and information herein are subject to change without notice. PS No.8263-15/15