Ordering number : EN7497A
LB11922
Monolithic Digital IC
For OA Products
http://onsemi.com
Three-Phase Brushless Motor Driver
Overview
The LB11922 is a pre-driver IC designed for constantspeed control of 3-phase brushless motors. It can be used to
implement a motor drive circuit with the desired output capacity (voltage, current) by using discrete transistors for the
output stage. It implements direct PWM drive for minimal power loss.
Features
• Direct PWM drive output
• Speed discriminator + PLL speed control circuit
• Speed lock detection output
• Built-in crystal oscillator circuit
• Forward/reverse switching circuit
• Braking circuit (short braking)
• Full complement of on-chip protection circuits, including lock protection, current limiter, and thermal shutdown
protection circuits.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
8
Maximum input current
IREG max
VREG pin
V
2
mA
Output current
IO max
UH, VH, WH, UL, VL, and WL outputs
Allowable power dissipation
Pd max1
Independent IC
30
mA
0.62
Pd max2
When Mounted on the specified PCB
1.36
W
W
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
* Specified circuit board : 114.3 × 76.1 ×
1.6mm3
: glass epoxy board
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
May, 2013
82008 MS PC/41503RM (OT) No.7497-1/15
LB11922
Allowable Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
VCC
Input current range
IREG
FG Schmitt output applied voltage
VFGS
0 to 7
V
FG Schmitt output current
IFGS
0 to 5
mA
Lock detection applied voltage
VLD
0 to 7
V
Lock detection output current
ILD
0 to 20
mA
VREG pin (7V)
4.4 to 7.0
V
0.2 to 1.5
mA
Electrical Characteristics at Ta = 25°C, VCC = 6.3V
Parameter
Symbol
Ratings
Conditions
min
Supply current
typ
ICC1
Unit
max
22
30.5
mA
mA
ICC2
In stop mode
2.4
3.4
ICC3
VCC = 5V
21
28
mA
ICC4
VCC = 5V, In stop mode
2.1
2.9
mA
Output saturation voltage 1-1
VO sat1-1
At low level : IO = 400μA
0.1
0.3
V
Output saturation voltage 1-2
VO sat1-2
At low level : IO = 10mA
0.8
1.2
V
Output saturation voltage 2
VO sat2
At high level : IO = -20mA
VCC-1.2
VCC-0.9
-2
-0.1
V
Hall Amplifier
Input bias current
IHB (HA)
Common-mode input voltage range 1
VICM1
When Hall-effect sensors are used
Common-mode input voltage range 2
VICM2
When one-side biased inputs are used
μA
0.5
VCC-2.0
V
0
VCC
V
(Hall-effect IC applications)
Hall input sensitivity
Sine wave
Hysteresis width
ΔVIN (HA)
Input voltage low → high
VSLH
Input voltage high → low
VSHL
100
20
mVp-p
30
50
mV
9
17
29
mV
-25
-13
-5
mV
PWM oscillator
Output high-level voltage 1
VOH (PWM)1
Output high-level voltage 2
VOH (PWM)2
Output low-level voltage 1
VOL (PWM)1
VCC = 5V
Output low-level voltage 2
VOL (PWM)2
VCC = 5V
Oscillator frequency
f (PWM)
C = 560pF
Amplitude 1
V (PWM)1
Amplitude 2
V (PWM)2
3.5
3.8
4.1
V
2.75
3.0
3.25
V
1.8
2.1
2.4
V
1.45
1.65
1.9
22
V
kHz
1.4
1.7
2.0
Vp-p
VCC = 5V
1.1
1.35
1.6
Vp-p
3.95
4.4
4.85
V
VCC = 5V
3.15
3.5
3.85
V
1.1
1.4
1.7
V
VCC = 5V
0.9
1.1
1.3
V
-13
-9
-6
μA
8
12
16
CSD circuit
Output high-level voltage 1
VOH (CSD)1
Output high-level voltage 2
VOH (CSD)2
Output low-level voltage 1
VOL (CSD)1
Output low-level voltage 2
VOL (CSD)2
External capacitor charge current
ICHG1
External capacitor discharge current
ICHG2
Oscillator frequency
f (RK)
Amplitude 1
V (RK)1
Amplitude 2
V (RK)2
C = 0.068μF
VCC = 5V
22
μA
kHz
2.65
3.0
3.35
Vp-p
2.1
2.4
2.65
Vp-p
10
MHz
Crystal Oscillator
Operating frequency range
fOSC
3
Low-level pin voltage
VOSCL
IOSC = -0.3mA
1.65
V
High-level pin current
IOSCH
VOSC = VOSCL + 0.3V
0.35
mA
Current Limiter Operation
Limiter
VRF
0.235
0.260
0.285
V
Continued on next page.
No.7497-2/15
LB11922
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Thermal Shutdown Operation
Thermal shutdown operating
TSD
Design target value *
ΔTSD
Design target value *
VREG
I = 500μA
150
180
°C
30
°C
temperature
Hysteresis width
VREG Pin
VREG pin voltage
6.6
7.0
7.4
V
Low-voltage Protection Circuit
Operating voltage
VSDL
3.55
3.75
4.00
V
Release voltage
VSDH
3.85
4.03
4.25
V
Hysteresis width
ΔVSD
0.18
0.28
0.38
V
-10
+10
mV
-1
+1
μA
FG Amplifier
Input offset voltage
VIO (FG)
Input bias current
IB (FG)
Output high-level voltage 1
VOH (FG)1
IFGI = -0.1mA, No load
4.2
4.6
5.0
V
Output high-level voltage 2
VOH (FG)2
IFGI = -0.1mA, No load, VCC = 5V
3.6
3.95
4.3
V
Output low-level voltage 1
VOL (FG)1
IFGI = 0.1mA, No load
1.3
1.7
2.1
V
Output low-level voltage 2
VOL (FG)2
IFGI = 0.1mA, No load, VCC = 5V
0.7
1.05
1.4
Gain : 100 ×
FG input sensitivity
Schmitt amplitude for the next stage
3
100
180
Operating frequency range
Open-loop gain
Reference voltage
f (FG) = 2kHz
VB (FG)
V
mV
250
mV
2
kHz
45
51
-5%
VCC/2
5%
dB
0.2
0.4
V
10
μA
V
FGS Output
Output saturation voltage
VO (FGS)
IO (FGS) = 2mA
Output low-level voltage
IL (FGS)
VO = VCC
Speed Discriminator Output
Output high-level voltage
VOH (D)
Output low-level voltage
VOL (D)
VCC-1.0
VCC-0.7
0.8
V
1.1
V
Speed Control PLL Output
Output high-level voltage
VOH (P)1
VOH (P)2
Output low-level voltage
VCC = 5V
VOL (P)1
VOL (P)2
VCC = 5V
4.05
4.30
4.65
V
3.25
3.50
3.85
V
1.85
2.15
2.45
V
1.25
1.60
1.85
V
0.25
0.4
V
10
μA
-6.25
+6.25
%
-10
+10
mV
+0.4
μA
Lock Detection
Output saturation voltage
VOL (LD)
ILD = 10mA
Output leakage current
IL (LD)
VO = VCC
Lock range
Integrator
Input offset voltage
VIO (INT)
Design target value *
Input bias current
IB (INT)
Output high-level voltage 1
VOH (INT)1
IINTI = -0.1mA, No load
-0.4
Output high-level voltage 2
VOH (INT)2
IINTI = -0.1mA, No load, VCC = 5V
Output low-level voltage 1
VOL (INT)1
IINTI = 0.1mA, No load
Output low-level voltage 2
VOL (INT)2
IINTI = 0.1mA, No load, VCC = 5V
45
51
-5%
VCC/2
Open-loop gain
Gain-bandwidth product
Reference voltage
4.1
4.4
4.7
V
3.45
3.7
3.95
V
1.2
1.4
1.65
V
1.1
1.3
1.5
V
Design target value *
VB (INT)
Design target value *
dB
1.0
MHz
5%
V
Note : * These items are design target values and are not tested.
Continued on next page.
No.7497-3/15
LB11922
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
S/S Pin
Input high-level voltage
VIH (S/S)
VCC = 6.3V, 5V
2.0
VCC
Input low-level voltage
VIL (S/S)
VCC = 6.3V, 5V
0
1.0
V
Input open voltage
VIO (S/S)
VCC-0.5
VCC
V
Hysteresis width
ΔVIN (S/S)
VCC = 6.3V, 5V
Input high-level current
IIH (S/S)
VS/S = VCC
Input low-level current
IIL (S/S)
VS/S = 0V
Pull-up resistance
RU (S/S)
V
0.13
0.22
0.31
V
-10
0
+10
μA
-170
-118
37
53.5
μA
70
kΩ
VCC
V
F/R Pin
Input high-level voltage
VIH (F/R)
VCC = 6.3V, 5V
Input low-level voltage
VIL (F/R)
VCC = 6.3V, 5V
Input open voltage
VIO (F/R)
Hysteresis width
ΔVIN (F/R)
VCC = 6.3V, 5V
Input high-level current
IIH (F/R)
VF/R = VCC
Input low-level current
IIL (F/R)
VF/R = 0V
Pull-up resistance
RU (F/R)
2.0
0
1.0
V
VCC-0.5
VCC
V
0.22
0.31
V
+10
μA
70
kΩ
V
0.13
-10
0
-170
-118
37
53.5
μA
BR Pin
Input high-level voltage
VIH (BR)
VCC = 6.3V, 5V
2.0
VCC
Input low-level voltage
VIL (BR)
VCC = 6.3V, 5V
0
1.0
V
Input open voltage
VIO (BR)
VCC-0.5
VCC
V
Hysteresis width
ΔVIN (BR)
VCC = 6.3V, 5V
Input high-level current
IIH (BR)
VBR = VCC
Input low-level current
IIL (BR)
VBR = 0V
Pull-up resistance
RU (BR)
0.13
0.22
0.31
V
-10
0
+10
μA
-170
-118
37
53.5
μA
70
kΩ
VCC
V
N Pin
Input high-level voltage
VIH (N)
VCC = 6.3V, 5V
2.0
Input low-level voltage
VIL (N)
VCC = 6.3V, 5V
Input open voltage
VIO (N)
Hysteresis width
ΔVIN (N)
VCC = 6.3V, 5V, Design target value *
Input high-level current
IIH (N)
VN = VCC
Input low-level current
IIL (N)
VN = 0V
Pull-up resistance
RU (N)
0
1.0
V
VCC-0.5
VCC
V
0.22
0.31
V
+10
μA
70
kΩ
0.13
-10
0
-170
-118
37
53.5
μA
Note : * These items are design target values and are not tested.
Package Dimensions
unit : mm (typ)
3247A
Pd max -- Ta
7.6
19
0.5
5.6
36
1
18
0.2
(0.7)
0.8
(1.5)
0.1
15.0
1.7max
0.3
Allowable power dissipation, Pd max – W
1.6
Specified board : 114.3×76.1×1.6mm3
glass epoxy
1.36
1.2
0.8
0.62
0.76
Independent IC
0.4
0.35
0
– 20
0
20
40
60
80
100
Ambient temperature, Ta – °C
SANYO : SSOP36(275mil)
No.7497-4/15
LB11922
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
VCC
WH
WL
VH
VL
UH
UL
GND
RF
RFGND
FGIN+
FGIN-
Pin Assignment
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
12
13
14
15
16
17
18
XO
XI
NC
Top view
FGOUT
11
NC
10
CSD
9
PWM
8
INT.OUT
N
7
INT.IN
BR
6
POUT
5
DOUT
4
LD
3
FGS
2
F/R
VREG
1
S/S
LB11922
Speed Discriminator Counts
N
Number of counts
High or open
512
Low
1024
fFG = fOSC ÷ (16 × )
Three-Phase Logic Truth Table (A high (H) input is the state where IN+ > IN-.)
Item
F/R = L
F/R = H
IN1
IN2
Output
IN1
IN2
IN3
IN3
PWM
-
1
H
L
H
L
H
L
VH
UL
2
H
L
L
L
H
H
WH
UL
3
H
H
L
L
L
H
WH
VL
4
L
H
L
H
L
H
UH
VL
5
L
H
H
H
L
L
UH
WL
6
L
L
H
H
H
L
VH
WL
S/S pin
BRK pin
Input condition
Condition
Input condition
High or open
Stop
High or open
Condition
Brake
Low
Start
Low
Released
No.7497-5/15
+
FGIN+
VREG
–
FGIN-
VREG
FGO
+
–
XI
X tal
OSC
ECL
1/16
FG
RST
XO
FG
FILTER
FGS
N
N
1/N
Speed control
system PLL
Speed
discriminator
DOUT
LD
LD
GND
POUT
PWM
PWM
OSC
LVSD
1.3VREF
VCC
INT IN
+
–
RFGND
RF
CURR
LIM
COMP
S/S
S/S
INT OUT
TSD
BR
BR
PRI DRIVER
LOGIC
HALL
HYS
AMP
CSD
OSC
F/R
FR
UL VL WL UH VH WH
LOGIC
VCC
IN3-
IN3+
IN2-
IN2+
IN1-
IN1+
CSD
LB11922
Block Diagram
No.7497-6/15
LB11922
Pin Functions
Pin No.
Pin name
1
VREG
Function
Equivalent circuit
7V shunt regulator output.
1
VCC
2
S/S
Start/stop control.
Low : 0 to 1.0V
VCC
50kΩ
High : 2.0V to VCC
Goes high when left open.
Low for start.
3.5kΩ
High or open for stop.
2
The hysteresis is about 0.22V.
3
F/R
Forward/reverse control.
Low : 0 to 1.0V
VCC
50kΩ
High : 2.0V to VCC
Goes high when left open.
Low for forward.
3.5kΩ
High or open for reverse.
3
The hysteresis is about 0.22V.
4
BR
Brake control (short braking operation).
Low : 0 to 1.0V
VCC
50kΩ
High : 2.0V to VCC
Goes high when left open.
High or open for brake mode operation.
3.5kΩ
The hysteresis is about 0.22V.
N
Speed discriminator count switching.
Low : 0 to 1.0V
High : 2.0V to VCC
Goes high when left open.
The hysteresis is about 0.22V.
VCC
50kΩ
5
4
3.5kΩ
5
Continued on next page.
No.7497-7/15
LB11922
Continued from preceding page.
Pin No.
Pin name
6
FGS
Function
Equivalent circuit
FG amplifier output (after the Schmitt circuit).
VCC
This is an open collector output.
6
7
LD
Speed lock detection output.
VCC
Goes low when the motor speed is within the
speed lock range (±6.25%).
7
8
DOUT
Speed discriminator output.
VCC
Acceleration → high, deceleration → low
8
9
POUT
Speed control system PLL output.
VCC
Outputs the phase comparison result for
CLK and FG.
9
Integrating amplifier inverting input.
VCC
30kΩ
INT IN
500Ω
500Ω
10
30kΩ
10
Continued on next page.
No.7497-8/15
LB11922
Continued from preceding page.
Pin No.
Pin name
11
INT OUT
Function
Equivalent circuit
Integrating amplifier output (speed control).
VCC
40kΩ
11
12
PWM
PWM oscillator frequency setting.
Connect a capacitor between this pin and
VCC
ground.
300Ω
7.5kΩ
12
13
CSD
Sets the operating time of the constrained-rotor
protection circuit.
VCC Reset circuit
Reference signal oscillator used when the
clock signal is cut off and to prevent
malfunctions.
300Ω
The protection function operating time can be
13
set by connecting a capacitor between this pin
and ground.
This pin also functions as the logic circuit block
power-on reset pin.
15
XO
16
XI
Oscillator circuit connections.
XO : Output pin
VCC
XI : Input pin
A reference clock can be generated by
connecting an oscillator element to these pins.
If an external clock with a frequency of a few
MHz is used, input that signal through a series
resistor of about 5.1kΩ.
15
The XO pin must be left open in this case.
16
FGOUT
FG amplifier output.
This pin is connected to the FG Schmitt
VCC
comparator circuit internally in the IC.
18
40kΩ
18
FG Schmitt comparator
Continued on next page.
No.7497-9/15
LB11922
Continued from preceding page.
Pin No.
19
Pin name
FGIN-
20
FGIN+
Function
Equivalent circuit
FG amplifier inputs.
FGIN- : FG amplifier inverting input
500Ω
VCC
FGIN+ : FG amplifier noninverting input
30kΩ
Insert capacitors between these
FGOUT
pins (which have a potential of 1/2
VCC) and ground.
500Ω
500Ω
19
30kΩ
20
21
RFGND
Output current detection.
VCC
Connect a resistor between this pin and
ground.
21
22
RF
Output current detection.
VCC
Connect a resistor between this pin and
ground.
The output limitation maximum current, IOUT,
is set to be 0.26/Rf by this resistor.
22
GND
24
UL
Ground connection.
Outputs (that are used to drive external
25
UH
transistors).
26
VL
These are push-pull outputs.
27
VH
The PWM duty is controlled on the UH, VH, and
28
WL
WH side of these outputs.
29
WH
30
VCC
VCC
24 26 28
50kΩ
23
25 27 29
Power-supply voltage.
Connect a capacitor between this pin and
ground for power supply stabilization.
31
32
IN3IN3+
35
IN2IN2+
IN1-
36
IN1+
33
34
Hall-effect device inputs.
opposite state.
If noise on the Hall-effect device signals is a
problem, insert capacitors between the
corresponding IN+ and IN- inputs.
The logic high state indicates that VIN+ > VIN-.
14
17
NC
VCC
The input is seen as a high-level input when
IN+ > IN-, and as a low-level input for the
32 34 36
500Ω
500Ω
31 33 35
These are unconnected pins, and can be used
for wiring.
No.7497-10/15
LB11922
Sample Application Circuit 1 (P-channel + n-channel, Hall-effect sensor application)
IN2-
IN3+
IN3-
VCC
WH
26
25
24
23
22
21
20
19
FGIN-
IN2+
27
FGIN+
IN1-
28
RFGND
29
RF
30
GND
31
UL
32
UH
33
VL
34
VH
35
WL
36
IN1+
24V
VREG
S/S
F/R
BR
N
FGS
LD
DOUT
POUT
INT.IN
INT.OUT
PWM
CSD
NC
XO
XI
NC
FGOUT
LB11922
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S/S
F/R
BR
N
FGS LD
Sample Application Circuit 2 (PNP + NPN, Hall-effect sensor application)
+
24V
IN1-
IN2+
IN2-
IN3+
IN3-
VCC
WH
WL
27
26
25
24
23
22
21
20
19
FGIN-
28
FGIN+
29
RFGND
30
RF
31
GND
32
UL
33
UH
34
VL
35
VH
36
IN1+
+
VREG
S/S
F/R
BR
N
FGS
LD
DOUT
POUT
INT.IN
INT.OUT
PWM
CSD
NC
XO
XI
NC
FGOUT
LB11922
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S/S
F/R
BR
N
FGS LD
No.7497-11/15
LB11922
LB11922 Description
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The speed
discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The PLL
circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a speed
discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in motor
speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency (fFG) is
controlled to have the following relationship with the crystal oscillator frequency (fOSC).
fFG = fOSC ÷ (16 × )
N
Number of counts
High or open
512
Low
1024
Therefore it is possible to implement half-speed control without switching the clock frequency by using combinations
of the N1 = high, N2 = low state and other setting states.
2. Reference Clock
This IC supports the use of either of the following methods for providing the speed control reference clock.
(1) Crystal oscillator
Use a circuit consisting of a crystal and capacitors such as the one shown below to implement a crystal oscillator.
XO
XI
C3
C2
C1
C1 : Used to prevent oscillation at upper harmonic frequencies.
C2 : Used for stabilization and to prevent oscillation at upper harmonic frequencies.
C3 : Used for oscillator coupling.
Oscillator frequency (MHz)
C1 (pF)
C2 (pF)
C3 (pF)
3 to 5
39
10
47
5 to 8
10
10
47
8 to 10
5
10
22
(Values provided for reference purposes)
This circuit and these component values are only provided for reference purposes. When implementing a crystal
oscillator in an application, it is necessary to consult the manufacturer of the crystal to verify that problems will not
occur due to interactions between stray capacitances due to wiring in the PCB and the crystal.
Notes :
The capacitor C1 is effective at lowering negative resistance values at high frequencies, but care is required to assure
that it does not excessively reduce the negative resistance at the fundamental frequency.
Since this crystal oscillator circuit is a high-frequency circuit, it can be easily influenced by stray capacitances on the
PCB. To minimize stray capacitances, keep connections between external components as short as possible and use
narrower line widths in the PCB patter.
The C1 and C2 ground lines must be as short as possible, and must be connected to the IC's ground pin (pin 23, GND).
If the PCB lines are excessively long, the oscillator circuit may be influenced by fluctuations in the ground line voltage
when, for example, the motor is overloaded, and the oscillator frequency may change. The C1 and C2 ground lines can
be made shorter by using the NC pins next to the XI and XO pins for the C1 and C2 ground, and connecting those pins
across the back of the IC to the IC GND pin.
No.7497-12/15
LB11922
(2) External clock (A frequency equivalent to that of the crystal oscillator circuit : a few MHz)
If a signal from an external signal source with a frequency equivalent to that of the crystal oscillator circuit is used,
input that signal to the IC through a series resistor (example value : 5.1kΩ). In this case, the XO pin must be left
open.
Input signal levels (signal source)
Low-level voltage : 0 to 0.8V
High-level voltage : 2.5 to 5.0V
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. The PWM switching is performed on the high side for each phase (UH, VH, and WH). The
PWM switching side in the output can be selected to be either the high or low side depending on how the external
transistors are connected.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.26V (typical), Rf : current
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current
detection resistor (Rf).
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to the
speed error to control the motor speed to be within the lock range.
6. Notes on the PWM Frequency
The PWM frequency is determined by the capacitor (F) connected to the PWM pin.
When VCC = 6.3V : fPWM ≈ 1/(82000 × C)
When VCC = 5.0V : fPWM ≈ 1/(66000 × C)
A PWM frequency of between 15 and 25kHz is desirable. If the PWM frequency is too low, the motor may resonate at
the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result in
audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the circuit
less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 23) with lines that are as
short as possible.
7. Hall effect sensor input signals
An input amplitude of over 100mVp-p is desirable in the Hall effect sensor inputs. The closer the input waveform is to
a square wave, the lower the required input amplitude. Inversely, a higher input amplitude is required the closer the
input waveform is to a triangular wave. Also note that the input DC voltage must be set to be within the commonmode
input voltage range.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins.
When the Hall inputs for all three phases are in the same state, all the outputs will be in the off state.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the
Hall effect sensor signal inputs as 0 to VCC level signals if the other side is held fixed at a voltage within the
common-mode input voltage range that applies when a Hall effect sensors are used.
No.7497-13/15
LB11922
8. Forward/Reverse Switching
The motor rotation direction can be switched using the F/R pin. However, the following notes must be observed if the
motor direction is switched while the motor is turning.
• This IC is designed to avoid through currents when switching directions. However, increases in the motor supply
voltage (due to instantaneous return of motor current to the power supply) during direction switching may cause
problems. The values of the capacitors inserted between power and ground must be increased if this increase is
excessive.
• If the motor current after direction switching exceeds the current limit value, the PWM drive side outputs will be
turned off, but the opposite side output will be in the short-circuit braking state, and a current determined by the motor
back EMF voltage and the coil resistance will flow. Applications must be designed so that this current does not exceed
the ratings of the output transistors used. (The higher the motor speed at which the direction is switched, the more
severe this problem becomes.)
9. Brake Switching
The LB11922 provides short-circuit braking implemented by turning the output transistors for the high side for all
phases (UH, VH, and WH) on. (The opposite side transistors are turned off for all phases.) Note that the current limiter
does not operate during braking. During braking, the duty is set to 100%, regardless of the motor speed. The current
that flows in the output transistors during braking is determined by the motor back EMF voltage and the coil resistance.
Applications must be designed so that this current does not exceed the ratings of the output transistors used. (The higher
the motor speed at which braking is applied, the more severe this problem becomes.)
The braking function can be applied and released with the IC in the start state. This means that motor startup and stop
control can be performed using the brake pin with the S/S pin held at the low level (the start state).
10. Constraint Protection Circuit
The LB1922M includes an on-chip constraint protection circuit to protect the IC and the motor in motor constraint
mode. If the LD output remains high (indicating the locked state) for a fixed period in the start state, the upper side
(external) transistors are turned off. This time is set by the capacitance of the capacitor attached to the CSD pin.
When VCC = 6.3V : The set time (in seconds) is 74 × C (μF)
When VCC = 5.0V : The set time (in seconds) is 60 × C (μF)
To clear the rotor constrained protection state, the application must either switch to the stop state for a fixed period
(about 1ms or longer) or turn off and reapply power.
If the rotor constrained protection circuit is not used, a 220kΩ resistor and a 1500pF capacitor must be connected in
parallel between the CSD pin and ground. Since the CSD pin also functions as the power-on reset pin, if the CSD pin
were connected directly to ground, the IC would go to the power-on reset state and motor drive operation would remain
off. The power-on reset state is cleared when the CSD pin voltage rises above a level of about 0.64V.
11. Low-Voltage Protection Circuit
The LB11922 includes a low-voltage protection circuit to protect against incorrect operation when power is first
applied or if the power-supply voltage (VCC) falls. The (external) upper side output transistors are turned off if VCC
falls under about 3.75V (tpyical), and this function is cleared at about 4.0V (typical).
12. Power Supply Stabilization
Since this IC is used in applications that draw large output currents, the power-supply line is subject to fluctuations.
Therefore, capacitors with capacitances adequate to stabilize the power-supply voltage must be connected between the
VCC pin and ground. If diodes are inserted in the power-supply line to prevent IC destruction due to reverse power
supply connection, since this makes the power-supply voltage even more subject to fluctuations, even larger capacitors
will be required.
13. Ground Lines
The signal system ground and the output system ground must be separated and a single ground point must be taken at
the connector. Since the output system ground carries large currents, this ground line must be made as short as possible.
Output system ground ... Ground for Rf and the output diodes
Signal system ground ... Ground for the IC and the IC external components
No.7497-14/15
LB11922
14. VREG Pin
If a motor drive system is formed from a single power supply, the VREG pin (pin 1) can be used to create the
powersupply voltage (about 6.3V) for this IC. The VREG pin is a shunt regulator and generates a voltage of about 7V
by passing a current through an external resistor. A stable voltage can be generated by setting the current to value in the
range 0.2 to 1.5mA. The external transistors must have current capacities of at least 80mA (to cover the ICC + Hall bias
current + output current requirements) and they must have voltage handling capacities in excess of the motor
power-supply voltage. Since the heat generated by these transistor may be a problem, heat sinks may be required
depending on the packages used. If the IC power-supply voltage (4.4 to 7.0V) is provided from an external circuit,
apply that voltage directly to the VCC pin (pin 30). In that case, the VREG pin must either be left open or connected to
ground.
15. FG Amplifier
The FG amplifier is normally implemented as a filter amplifier such as that shown in the application circuits to reject
noise. Since a clamp circuit has been added at the FG amplifier output, the output amplitude is clamped at about 3Vp-p,
even if the gain is increased.
Since a Schmitt comparator is inserted after the FG amplifier, applications must set the gain so that the amplifier output
amplitude is at least 250mVp-p. (It is desirable that the gain be set so that the amplitude is over 0.5Vp-p at the lowest
controlled speed to be used.)
The capacitor inserted between the FGIN+ pin (pin 20) and ground is required for bias voltage stabilization. To make
the connected capacitor as immune from noise as possible, connect this capacitor to the GND pin (pin 23) with a line
that is as short as possible.
16. Integrating Amplifier
The integrating amplifier integrates the speed error pulses and the phase error pulses and converts them to a speed
command voltage. At the same time it also sets the control loop gain and frequency characteristics using external
components.
17. NC pin
Since the NC pins are electrically open with respect to the IC itself, they can be used as intermediate connection points
for lines in the PCB pattern.
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PS No.7497-15/15
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