SSG4505

Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET RoHS Compliant Product SOP-8 Description 0.40 0.90 0.19 0.25 The SSG4505 provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SOP-8 package is universally preferred for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters. 0.35 0.49 1.27Typ. 45 6.20 5.80 0.25 o 0.375 REF 3.80 4.00 4.80 5.00 0.10~0.25 Features * Simple Drive Requirement * Lower On-Resistance 0 o 8 o 1.35 1.75 Dimensions in millimeters D1 8 D1 7 D2 6 D2 5 D1 D2 * Fast Switching Performance Date Code 4505SS G2 G1 S1 S2 1 S1 2 G1 3 S2 4 G2 Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 Symbol VDS VGS ID@TA=25 C ID@TA=70 C IDM PD@TA=25 C o o o Ratings 30 ±20 10 7.9 30 2 .0 0 .0 1 6 Unit -30 ±20 -8.4 -6.7 -30 V V A A A W W/ C o o 3 T otal Power Dissipation L inear Derating Factor O perating Junction and Storage Temperature Range Tj, Tstg -55~+150 C Thermal Data Parameter Thermal Resistance Junction-ambient 3 Symbol Max. Rthj-a Ratings 62.5 o Unit C /W http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 1 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET Electrical Characteristics N Channel( Tj=25 C Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25oC) o Unless otherwise specified) Typ. _ Symbol BVDSS BVDS/ Tj VGS(th) IGSS IDSS Min. 30 _ Max. _ _ Unit V V/oC V nA uA uA Test Condition VGS=0V, ID=250uA Reference to 25 C, ID=1mA VDS=VGS, ID=250uA VGS=± 20V VDS=30V,VGS=0 VDS=24V,VGS=0 VGS=10V, ID=6A o 0.02 _ _ _ _ _ _ 1.0 _ _ _ _ 3.0 ±100 1 25 14 Drain-Source Leakage Current (Tj=70 C ) 2 o Static Drain-Source On-Resistance RDS(ON) Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs mΩ _ _ _ _ _ _ _ _ _ _ _ 20 65 _ _ VGS=4.5V, ID=4 A Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time2 Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance 23 6 14 14 10 36 17 1770 430 350 14 nC ID=9 A VDS=24V VGS= 4.5V _ VDD=15V _ ID=1 A nS VGS=10V RG=3.3 Ω RD=15 Ω _ _ 2830 _ _ pF VGS=0V VDS=25V f=1.0MHz _ _ S VDS=10V, ID=9 A Source-Drain Diode Parameter Forward On Voltage 2 Symbol VSD Trr Qrr Min. _ _ _ Typ. _ Max. 1.2 _ _ Unit V Test Condition IS= 1.7A ,VGS=0V IS=9A,V GS=0V dl/dt=100A/us Reverse Recovery Time Reverse Recovery Charge 31 25 nS nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width≦300us, dutycycle≦2%. 3.Surface mounted on 1 inch2 copper pad of FR4 board;135 °C/W when mounted on min. copper pad. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 2 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET o Electrical Characteristics P-Channel( Tj=25 C Unless otherwise specified) Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25 C) o Symbol BVDSS BVDS/ Tj VGS(th) IGSS IDSS Min. -30 _ Typ. _ Max. _ _ Unit V V/ oC V nA uA uA Test Condition VGS=0V, ID=-250uA Reference to 25oC, ID=-1mA VDS=VGS, ID=-250uA VGS=± 20V VDS=-30V,VGS=0 VDS=-24V,VGS=0 VGS=-10V, ID=-8A -0.02 _ _ _ _ _ _ -1.0 _ _ _ _ -3.0 ±100 -1 -25 20 Drain-Source Leakage Current (Tj=70oC) Static Drain-Source On-Resistance 2 RDS(ON) Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs mΩ _ _ _ _ _ _ _ _ _ _ _ 30 45 _ _ VGS=-4.5V, ID=-4 A Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time 2 Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance 27 4 18 16 11 40 25 1580 540 450 14 nC ID=-8 A VDS=-24V VGS=-4.5V _ VDS=-15V _ ID=-1A nS VGS=-10V RG=3.3Ω RD=15 Ω _ _ 2530 _ _ pF VGS=0V VDS=-25V f=1.0MHz _ _ S VDS=-10V, ID=-8 A Source-Drain Diode Parameter Forward On Voltage 2 Symbol VSD Trr Qrr Min. _ _ _ Typ. _ Max. -1.2 _ _ Unit V Test Condition IS= -1.7A, VGS=0V IS=-8A,VGS=0V dl/dt=100A/us Reverse Recovery Time Reverse Recovery Charge 40 32 nS nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width≦300us, dutycycle≦2%. 3.Surface mounted on 1 inch2 copper pad of FR4 board;135 °C/W when mounted on min. copper pad. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 3 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET Characteristics Curve N-Channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature http://www.SeCoSGmbH.com/ Fig 5. Forward Characteristics of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 4 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET N-Channel Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform http://www.SeCoSGmbH.com/ Fig 12. Gate Charge Waveform Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 5 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET P-Channel GND Description Typic ally a large stor age c apacitor is c onnec ted fr om this pin to gr ound to ins ur e that the input 1.3V or open= output enable. NC tage does not s ag below the minimum dr opout voltage during the load V higher than Vout in or der f or the devic e to Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Forward Characteristics of Reverse Diode http://www.SeCoSGmbH.com/ Fig 6. Gate Threshold Voltage v.s. Junction Temperature Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 6 of 7 Elektronische Bauelemente N Channel 10A, 30V,RDS(ON) 14mΩ P Channel -8.4A, -30V,RDS(ON) 20mΩ SSG4505 Enhancement Mode Power Mos.FET P-Channel Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform h tp://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jan-2008 Rev. B Page 7 of 7