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SST2603

SST2603

  • 厂商:

    SECOS

  • 封装:

  • 描述:

    SST2603 - P-Channel Enhancement Mode Power Mos.FET - SeCoS Halbleitertechnologie GmbH

  • 数据手册
  • 价格&库存
SST2603 数据手册
SST2603 -5A, -20V,RDS(ON) 65mΩ Elektronische Bauelemente P-Channel Enhancement Mode Power Mos.FET RoHS Compliant Product SOT-26 Description The SST2603 utilized advanced processing techniques to achieve the lowest possible on-resistance, extremely efficient and cost-effectiveness device. The SST2603 is universally used for all commercial industrial surface mount application and suited for low voltage applications such as DC/DC converters. 1.90REF 0.95REF 0.95REF 1.2 REF 0.37 REF 2.60 3.00 0.60 REF 1.40 1.80 0.30 0.55 2.70 3.10 0.10 Max Features * Small package outline * Simple drive requirement D D 6 D 5 0 o 10 o 1.10 1.35 Dimensions in millimeters S 4 G Date Code 1 D 2603 2 D 3 G S Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1,2 3 Symbol VDS VGS ID@TA=25 C ID@TA=70 C IDM PD@TA=25 C o o o Ratings -20 ±12 -5 -4 -20 2 0.016 Unit V V A A A W W/ C o o 3 Total Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Tj, Tstg -55~+150 C Thermal Data Parameter Thermal Resistance Junction-ambient 3 Symbol Max. Rthj-a Ratings 62.5 o Unit C /W http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 1 of 4 SST2603 Elektronische Bauelemente o -5A, -20V,RDS(ON) 65mΩ P-Channel Enhancement Mode Power Mos.FET Electrical Characteristics( Tj=25 C Unless otherwise specified) Parameter Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Gate Threshold Voltage Gate-Source Leakage Current Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=55 C) o o Symbol BVDSS BVDS/ Tj VGS(th) IGSS IDSS Min. -20 _ Typ. _ Max. _ _ Unit V V/ C V nA uA uA o Test Condition VGS=0V, ID=-250uA Reference to 25 C, ID=-1mA VDS=VGS, ID=-250uA VGS=± 12V VDS=-20V,VGS=0 VDS=-16V,VGS=0 VGS=-10V, ID=-4.5A o -0.1 _ _ _ _ -0.5 _ _ _ _ -1.2 ±100 -1 -10 53 65 120 250 16 _ _ _ _ _ _ 10.6 2.32 3.68 5.9 3.6 32.4 2.6 740 Static Drain-Source On-Resistance 2 _ RDS(ON) _ _ mΩ VGS=-4.5V, ID=-4.2A VGS=-2.5V, ID=-2.0A VGS=-1.8V, ID=-1.0A ID=-4.2A VDS=-16V VGS=-4.5V Total Gate Charge 2 Qg Qgs Qgd Td(ON) Tr Td(Off) Tf Ciss Coss Crss Gfs _ _ _ _ _ _ _ _ _ _ Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Forward Transconductance 2 nC _ _ _ _ VDD=-15V ID=-4.2A nS VGS=-10V RG=6 Ω RD=3.6Ω 1200 _ _ 167 126 9 pF VGS=0V VDS=-15V f=1.0MHz _ _ S VDS=-5V, ID=-2.8A Source-Drain Diode Parameter Forward On Voltage 2 Symbol VDS Min. _ Typ. _ 27.7 22 Max. -1.2 Unit V Test Condition IS=-1.2A, VGS=0V. Is=-4.2A, VGS=0V dl/dt=100A/us Reverse Recovery Time 2 Trr Qrr _ _ _ _ nS nC Reverse Recovery Charge Notes: 1.Pulse width limited by safe operating area. 2.Pulse width≦300us, dutycycle≦2%. O 3.Surface mounted on 1 in2 copper pad of FR4 board; 156 C/W when mounted on Min. copper pad. http://www.SeCoSGmbH.com/ Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 2 of 4 SST2603 Elektronische Bauelemente -5A, -20V,RDS(ON) 65mΩ P-Channel Enhancement Mode Power Mos.FET Characteristics Curve Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Forward Characteristics of Reverse Diode http://www.SeCoSGmbH.com/ Fig 6. Gate Threshold Voltage v.s. Junction Temperature Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 3 of 4 SST2603 Elektronische Bauelemente -5A, -20V,RDS(ON) 65m Ω P-Channel Enhancement Mode Power Mos.FET Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform http://www.SeCoSGmbH.com/ Fig 12. Gate Charge Waveform Any changing of specification will not be informed individual 01-Jun-2002 Rev. A Page 4 of 4
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