SC4508A

Buck or Buck-Boost (Inverting) Current Mode Controller POWER MANAGEMENT Description The SC4508A is a low voltage current mode switching regulator controller that drives a P-channel power MOSFET with programmable switching frequency. It can be configured in either buck or buck boost (inverting) converters. The converters can be operated from 2.7V to 15V input voltage range. The typical operating supply current is 3mA and a shutdown pin allows the user to turn the controller off reducing it to less than 200µA. The output voltage can adjusted by external resistor divider. The switching frequency is programmable up to 1.5MHz, allowing small inductor and capacitor values to minimize PCB space. The operating current level is programmable via an external sense resistor. Accessible reference voltage allows users to make output voltage as low as they want. SC4508A Features Wide input voltage range 2.7V to 15V Programmable output voltage Programmable switching frequency up to 1.5MHz Buck or buck boost (inverting) configuration Current mode control with slope compensation Very low quiescent current in shutdown mode Accessible reference voltage Hiccup mode after 32 cycle-by-cycle OCP 4mm x 4mm MLPQ-12 lead free package. This product is fully WEEE and RoHS compliant Applications Low power point of use converters Single or multiple output low power converters Positive and/or negative output voltage DSL cards Graphic cards I/O cards Negative bias supplies Typical Application Circuits Vin Vin V+ V+ VREF VREF CS FB+ OUT FB- FB+ FB- SC4508A SC4508A CS COMP Vout SS/EN GND OSC COMP OUT Vout SS/EN GND OSC Revision: July 25, 2007 1 www.semtech.com SC4508A POWER MANAGEMENT Absolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter VDD to GND SS/EN to GND(1) FB+, FB-, COMP, OSC to GND VREF Current Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case Storage Temperature Range Junction Temperature Range Peak IR Reflow Temperature 10 - 40s Symbol Maximum -0.3 to 16 3.2 5 1 Units V V V mA °C/W °C/W °C °C °C θJ A θJ C TSTG TJ TPKG 48 3 -60 to +150 -40 to +150 260 Note: (1) Voltage from internal circuitry could be higher than 3.2V. See Application Information, Soft-Start section. Electrical Characteristics Unless specified: VDD = 12V, VFB+ = VREF, VFB- = 0, OUT = open, CVDD = 1uF, CSS/EN = 0.1uF, COSC = 330pF. TA = TJ = -40°C to 125°C Parameter Pow er Supply Input Voltage Range Quiescent Current Operating Current Undervoltage Lockout Start Threshold UVLO Hysteresis Oscillator Frequency Range Frequency Charge Current Error Amplifier Feedback Input Voltage Offset Voltage Input Bias Current Transconductance Output Source or Sink Current  2007 Semtech Corp. Test Conditions Min Typ Max Unit 2.7 SS/EN = low SS/EN = high, No load 200 3 15 500 V µA mA VDD rising 2.35 2.5 100 2.55 V mV 100 450 500 100 1500 550 KHz KHz µA -0.2 2 100 5 50 2 0.7 V mV 300 nA mS µA www.semtech.com 100 SC4508A POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: VDD = 12V, VFB+ = VREF, VFB- = 0, OUT = open, CVDD = 1uF, CSS/EN = 0.1uF, COSC = 330pF. TA = TJ = -40°C to 125°C Parameter PWM Comparator Maximum Duty Cycle Test Conditions Min Typ Max Unit C = 1.5nF, 100kHz C = 100pF, 1.5MHz 97 95 200 63 50 % % nS mV/Ts ns Minimum On Time Slope Compensation Delay to Output VREF Reference Output Voltage Output Voltage Output Current Line Regulation Load Regulation Soft Start/Enable/Shutdow n Charge Current VSS/EN > 0.9V VSS/EN < 0.9V Discharge Current Enable Logic Voltage SHDN Logic Voltage Current Limit Cycle by Cycle Threshold Consecutive Overcurrent Clock Cycles before Auto Restart Shutdown Delay to Output Output Gate Drive On-Resistance(H) Gate Drive On-Resistance(L) Gate Drive On-Resistance(H) Gate Drive On-Resistance(L) Rise Time Fall Time  2007 Semtech Corp. 0.4925 TA = 25°C, VDD = 5V 0.496 0.5 0.5 0.5075 0.504 1 V V mA mV mV VDD = 2.7 to 15V, IVREF = 1mA VDD = 5V, IVREF = 0 to 1mA 5 2 10 4 20 10 12 2 0.35 µA mA V V V D D = 5V 90 110 32 130 mV 50 nS 8 8 V D D = 5V V D D = 5V COUT = 1000pF COUT = 1000pF 3 Ohm Ohm Ohm Ohm nS nS www.semtech.com 15 15 20 20 SC4508A POWER MANAGEMENT Pin Configuration TOP VIEW VDD OSC COMP Ordering Information Part Number SC4508AMLTRT(2) SC4508ABUCKEVB SC4508ABUCK-BOOSTEVB P ackag e (1) MLPQ -12 Evaluation Board Evaluation Board 12 OUT CS SS/EN 1 2 3 4 11 10 9 8 7 FB+ FBPGND Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. 5 6 VREF NC AGND (MLPQ - 12, 4mm x 4mm) Pin Descriptions Pin # 1 2 3 Pin Name OUT CS SS/EN Pin Function Gate driver output for external P-MOSFET. OUT swings from VDD to PGND. Current sense input pin. Connect a current sense resistor between VDD and CS. Soft start pin. Connects an external capacitor between this pin and AGND. The ramp up time is defined by the capacitor. The device goes into shutdown when VSS/EN is pulled below 0.25V. 0.5V reference output. VREF can source up to 1mA. Bypass with a 0.1uF ceramic capacitor from VREF to AGND. No connection. Analog ground. Power ground. Error amplifier inverting input. Error amplifier non-inverting input. Compensation pin for internal transconductance error amplifier. Connect loop compensation network from COMP to AGND. Oscillator frequency set input. Connect a ceramic capacitor from OSC to AGND to set the internal oscillator frequency from 100KHz to 1.5MHz. Use equation to set the 100µA f= oscillator frequency. C is the capacitor from OSC to AGND. C • 0.65 Supply voltage. Bypass a 1uF ceramic capacitor from VDD to PGND. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally. 4 www.semtech.com 4 5 6 7 8 9 10 11 VREF NC AGND PGND FB FB + COMP OSC 12 VD D THERMAL PAD  2007 Semtech Corp. SC4508A POWER MANAGEMENT Block Diagram Marking Information Top View yyww = Date Code (Example: 0012)  2007 Semtech Corp. 5 www.semtech.com SC4508A POWER MANAGEMENT Application Information The SC4508A is designed to control buck (step down) or buck-boost (inverting) converter with P-channel MOSFET as a switch using current mode, programmable switching frequency architecture. During steady state operation, the switch is turned on each cycle and turned off when the voltage across current sense resistor exceeds the voltage level at COMP pin set by voltage loop error amplifier. A fixed 0.5V artificial ramp is added internally to the amplified current signal for operations when dutycycle is larger than 50%. In over load or output shortage condition, if the sensed current signal reaches typical 100mV, the switch is turned off immediately in the same cycle. If the sensed current signal continues up to 32 cycles, not only the switch is turned off but also the soft start capacitor is discharged by a internal MOSFET to ground then charging back to threshold 1.4V during which the switch is held off. With the “hiccup” mode over current protection, the thermal stress is reduced in the faulty conditions. Frequency Setting The switching frequency in the SC4508A is userprogrammable. The advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs should be considered. 1) 2) 3) 4) 5) Passive component size Circuitry efficiency EMI condition Minimum switch on time and Maximum duty ratio operating up to 1.5 MHz. It is necessary to consider the operating duty-ratio before deciding the switching frequency. Minimum Switch On Time Consideration In the SC4508A the falling edge of the clock turns on the MOSFET. The inductor current and the sensed voltage ramp up. After the sensed voltage crosses a threshold determined by the error amplifier output, the MOSFET is turned off. The propagation delay time from the turn-on of the controlling MOSFET to its turn-off is the minimum switch on time. The SC4508A has a minimum on time of about 180ns at room temperature. This is the shortest on interval of the controlling PFET. The controller either does not turn on the MOSFET at all or turns it on for at least 80ns. For a buck converter, the operating duty cycle is VO/VIN. So the required on time for the MOSFET is VO/(VINfs). If the frequency is set such that the required pulse width is less than 180ns, then the converter will start skipping cycles. Due to minimum on time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not practical. If the voltage conversion ratio VO/VIN and hence the required duty cycle is higher, the switching frequency can be increased to reduce the sizes of passive components. There will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the SC4508A. For ease of control, we recommend the required pulse width to be at least 1.5 times the minimum on time. Current Sense and Current Limit The SC4508A senses peak inductor current by a current sense resistor. The sensed voltage is referenced to VDD and the typical current limit threshold is 100mV. The current sense resistor can be calculated by the following equation assuming the current limit is 20% above peak incuctor current: For a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas MOSFET’s/Diodes switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are also to be considered. The frequency bands for signal transmission should be avoided because of EM interference. The free-running frequency of the internal oscillator can be programmed with an external capacitor from the OSC pin to the ground. The SC4508A controller is capable of 100mV Rs = 120% • I (pk ) L 1V −V V +V IN O O D IL (pk) = IO + 2 f • L ( V + V ) for Buck s IN D  2007 Semtech Corp. 6 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) IL (pk ) = IO VIN + VO + VD VIN + VO + VD 1 VIN ( ) 2 fs • L VIN + VO + VD undergoes soft-start. If overload persists, the SC4508A will undergo repetitive auto-shutdown-restart hiccup mode. In normal operation, the VREF voltage follows the SS/ EN voltage from 0 to 0.5V as the SS/EN voltage ramps up from 1.4V to 1.9V. After the SS/EN voltage rises above 1.9V, it settles at final value depending upon VDD. If VDD higher than 7V, it is clamped around 6.8V. In the worst case, the clamped voltage is about 10V. Therefore, the external soft-start capacitor should be rated at least 16V. The SS/EN pin can also be used as the enable input. The MOSFET will be turned off if the SS/EN pin is pulled below 0.5V. Converter Specifications Buck or buck-boost converter design includes the following specifications: Input voltage range: Vin ∈ [ Vin,min , Vin,max ] Input voltage ripple (peak-to-peak): DVin Output voltage: Vo Output voltage accuracy: e Output voltage ripple (peak-to-peak): DVo Nominal output (load) current: Io Maximum output current limit: Io,max Output (load) current transient slew rate: dIo (A/s) Circuit efficiency: h Selection criteria and design procedures for the following are described. 1) output inductor (L) type and value 2) output capacitor (Co) type and value 3) input capacitor (Cin) type and value 4) power MOSFETs 5) current sensing and limiting circuit 6) voltage sensing circuit 7) loop compensation network Inductor (L) and Ripple Current The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC 7 www.semtech.com for Buck − Boost IO - full load current VO - output voltage VIN - input voltage VD - diode forward voltage drop fS - switching frequency L - inductor Error Amplifier The error amplifier in the SC4508A is a transconductance error amplifier, which is easily configured as a type two compensator by connecting compensation network from the COMP pin to AGND. The output voltage of the error amplifier is compared to the sensed current signal (amplified by gain 8) plus internal 500mV ramp to generate duty cycle. Both the non-inverting and the inverting inputs of the error amplifier are brought out as device pins so that a converter can be configured as either buck or buck-boost converter. Soft-Start and Overload Protection The undervoltage lockout circuit discharges the SS/EN capacitors. After V DD r ises above 2.5V, the SS/EN capacitors are slowly charged by internal 10uA current source. As the SS/EN capacitor continues to be charged, the VREF and the COMP voltage follows. The converter gradually delivers increasing power to the output. The inductor current follows the COMP voltage envelope until the output goes into regulation. After the SS/EN capacitor is charged above 1.4V (high enough for the error amplifier to provide full load current), the overload detection circuit is activated. If the CS pin senses 32 consective switching cycles of over current, the SC4508A will shut down and hold off the MOSFET while discharging the soft-start capacitor. The SS/EN capacitor is discharged with an internal 12mA current sink. The overload latch is reset when the SS/EN capacitor is discharged below 0.5V. The SS/EN capacitor is then recharged with the 10µA current source and the converter  2007 Semtech Corp. SC4508A POWER MANAGEMENT Application Information (Cont.) core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripplecurrent is 20% to 30% of the rated output load current or the inductor DC current. Assuming that the inductor current ripple (peak-to-peak) value is ∆IL = δ *Idc, the inductance value will then be: L= VIN − VO VO + VD ( ) for Buck fs • ∆IL VIN + VD Co Lesl Resr Figure 1. An equivalent circuit of Co If the current through the branch is ib(t), the voltage across the terminals will then be: v o ( t ) = Vo + 1 di ( t ) ib ( t )dt + L esl b + Resr ib ( t ) Co 0 dt VO + VD VIN L= ( ) for Buck-Boost fs • ∆IL VIN + VO + VD The peak current in the inductor becomes (1+δ/2)*Idc and the RMS current is: IL,rms = Idc 1 + δ2 12 ∫ t This basic equation illustrates the effect of ESR, ESL and Co on the output voltage. The first term is the DC voltage across Co at time t=0. The second term is the voltage variation caused by the charge balance between the load and the converter output. The third term is voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms. Since the inductor current is a triangular waveform in buck configuration with peak-to-peak value δ*Io, the ripple-voltage caused by inductor current ripples is: ∆v C ≈ δIo 8Co fs δIo D The Idc is the inductor average or DC current. The following are to be considered when choosing inductors: a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Output Capacitor (Co) and Vout Ripple The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure 1).  2007 Semtech Corp. 8 the ripple-voltage due to ESL is: ∆v ESL = L esl fs and the ESR ripple-voltage is: ∆v ESR = R esr δIo Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low ESL’s. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripple-voltage < ∆Vo, the ESR should satisfy: R esr1 < ∆Vo δIo the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10 µ F, 4m Ω c eramic capacitor is connected in parallel with 2x1500µF, 90mΩ electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100µ F, 2mΩ ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100µF, 2mΩ ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESRs either. Instead they should be calculated using the following formulae. C eq (ω) := (R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2 (R1a C1a + R1b C1b )ω2 C1a C1b + (C1a + C1b ) R1aR1b (R1a + R1b )ω2C1a C1b + (R1b C1b + R1a C1a ) (R1a + R1b )2 ω2 C1a C1b + (C1a + C1b )2 2 2 2 2 2 2 2 2 2 2 To limit the dynamic output voltage overshoot/ undershoot within α (say 3%) of the steady state output voltage) from no load to full load, the ESR value should satisfy: R esr 2 < αVo Io Then, the required ESR value of the output capacitors should be: Resr = min{Resr1,Resr2 } The voltage rating of aluminum capacitors should be at least 1.5Vo. The RMS current ripple rating should also be greater than: δIo 23 Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/ discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy: Co > 10 2πfsR esr R eq (ω) := Buck-boost converter has higher ripple current than buck in output. The RMS value is the most important factor to consider. It has to be less than the output capacitor ripple current rating. The buck-boost output capacitor RMS current is: IRMS _ CAP ≈ IO VO + Vd VIN where R 1a a nd C 1a a re the ESR and capacitance of electrolytic capacitors, and R1b and C1b are the ESR and capacitance of the ceramic capacitors respectively. (Figure 2) ∆v ESR = R esr ⋅ Id where, Vd and Id are rectifier forward voltage and current. In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors,  2007 Semtech Corp. 9 C1a C1b Ceq R1a R1b Req Figure 2. Equivalent RC branch. www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and Req = 1/2 R1 and Ceq = 2C1 Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 3. It can be seen that the current in the input capacitor pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFETs on the PC board to reduce trace inductances around the pulse current loop. The RMS value of the capacitor current is approximately ICin = Io D[(1 + δ2 D D )(1 − )2 + 2 (1 − D) ] η η 12 The power dissipated in the input capacitors is then: PCin = ICin2Resr For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (RMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is: Figure 3. A simple model for the converter input In Figure 3 the DC input voltage source has an internal impedance Rin and the input capacitor Cin has an ESR of Resr. MOSFET and input capacitor current waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 4. δ ∆v ESR = R esr (1 + )Idc 2 The peak-to-peak input voltage ripple due to the capacitor is: ∆v C ≈ DIdc Cin fs From these two expressions, CIN can be found to meet the input voltage ripple specification. Power MOSFETs Selection Main considerations in selecting the MOSFETs are power dissipation, cost and packaging. Switching losses and conduction losses of the MOSFETs are directly related to the total gate charge (Cg) and channel on-resistance (Rds(on)). In order to judge the performance of MOSFETs, the product of the total gate charge and on-resistance is used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 5. Figure 4. Typical waveforms at converter input.  2007 Semtech Corp. 10 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) 50 Gate Charge (nC) 40 Cg( 100 , Rds) Cg( 200 , Rds) Cg( 500 , Rds) 20 manufacturers’ data sheet. From the FDS6675 datasheet, Rds(on) is less than 14mΩ when Vgs is greater than 10V. However R ds(on) i ncreases by 30% as the junction temperature increases from 25oC to 110oC. The switching losses can be estimated using the simple formula: δ 1 Pts = 2 ( t r + t f )(1 + 2 )Idc Vin fs 1 0 0 1 5 10 15 20 20 FOM:100*10^{-12} FOM:200*10^{-12} FOM:500*10^{-12} Rds On-resistance (mOhm) Figure 5. Figure of Merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFETs with both low Cg and low Rds(on. Usually a trade-off between Rds(on and Cg has to be made. MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For buck and buckboost converters with high input to output voltage ratios, the MOSFET is hard switched but conducts with very low duty cycle. For such applications, MOSFETs with low Cg should be used. MOSFET power dissipation consists of: a) conduction loss due to the channel resistance Rds(on), b) switching loss due to the switch rise time tr and fall time tf, and c) the gate loss due to the gate resistance RG. The RMS value of the MOSFET switch current is calculated as: δ IQrms = Idc D(1 + 12 ) 2 where tr is the rise time and tf is the fall time of the switching process. Different manufacturers have different definitions and test conditions for t and t . To r f clarify these, we sketch the typical MOSFET switching characteristics under clamped inductive mode in Figure 6. Figure 6. MOSFET switching characteristics In Figure 6, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold voltage Vgs_th, Qgs2 is the additional gate charge required for the switch current to reach its full-scale value Ids and . Qgd is the charge needed to charge gate-to-drain (Miller) capacitance when Vds is falling. Switching losses occur during the time interval [t1, t3]. Defining tr = t3-t1 and tr can be approximated as: tr = (Qgs 2 + Qgd )Rgt Vcc − Vgsp The conduction losses are then Ptc = IQrms2 Rds(on) Idc is average inductor current. In buck converter, it is also load current. In buck-boost, it is load current divided by 1-D. Rds(on) varies with temperature and gate-source voltage. Curves showing R ds(on) v ariations can be found in  2007 Semtech Corp. where Rgt is the total resistance from the driver supply rail to the gate of the MOSFET. It includes the gate driver internal impedance Rgi, external resistance Rge and the gate resistance Rg within the MOSFET i.e. Rgt = Rgi+Rge+Rg Vgsp is the Miller plateau voltage shown in Figure 11. Similarly an approximate expression for tf is: 11 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) tf = (Qgs2 + Qgd )R gt Vgsp (Tj,max, usually 125oC) is not exceeded under the worstcase condition. The equivalent thermal impedance from junction to ambient (θja) should satisfy: θ ja ≤ Tj,max − Ta,max Ploss Only a portion of the total losses (Pg = QgVccfs) is dissipated in the MOSFET package. Here Qg is the total gate charge specified in the datasheet. The power dissipated within the MOSFET package is: Ptg = Rg Rgt Qg Vcc fs θja depends on the die to substrate bonding, packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area and the air flow condition (free or forced convection). Actual temperature measurement of the prototype should be carried out to verify the thermal design. Overload Protection and Hiccup During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the converter starts and enters regulation, the same capacitor operates as an overload shutoff timing capacitor. As the load current increases, the cycle-bycycle current-limit comparator will first limit the inductor current. If the over-current persists for more than 32 consecutive switching cycles, the controller will shut off the MOSFETs. Meanwhile an internal 12mA current source discharges the soft-start capacitor CSS connected to the SS/EN pin. When the capacitor is discharged to 0.5V, a 10µA current source recharges the SS/EN capacitor to 0.9V and driver stage is enabled. Then a 20uA current source continues to charge the soft-start capacitor. As the soft-start capacitor reaches 1.4V, VREF will start to follow the softstart capacitor voltage until VREF=0.5V. If overload persists, the controller will shut down the converter when the soft-start capacitor voltage exceeds 1.4V. The converter will repeatedly start and shut off until it is no longer overloaded. This hiccup mode of overload protection is a form of foldback current limiting. The following calculations estimate the average inductor current when the converter output is shorted to the ground. a) The time taken to charge the capacitor from 0.5V to 0.9V t ssr1 = CSS ( 0.9 − 0.5 ) V 10uA The total power loss of the top switch is then: Pt = Ptc+Pts+Ptg If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design. Freewheeling Diode Selection The Schottky diode is recommended as freewheeling diode in the both Buck and Buck-Boost applications. The diode conducts during the off-time. The diode voltage and current ratings are selected based on the peak reverse voltage, the peak current and average power dissipation. The following could be used to determine the diode reversed voltage: VD(REV ) = VIN , ID(PEAK ) = IO + ∆IL V − VO ,ID( AVG ) = IO IN for Buck 2 VIN + VD VIN + VO + VD VIN )+ ∆IL ,ID( AVG ) = IO 2 VD(REV ) = VIN + VO , ID(PEAK ) = IO ( for Buck − Boost The most stressful condition for the diode occurs when the output is shorted. Under this condition, due to the VOUT = 0, the diode conducts at close to 100% duty cycle. Therefore, attention should be paid to the thermal condition when laying out a board. Once the power losses (P loss ) for the MOSFET and freewheeling diode are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature  2007 Semtech Corp. If CSS = 0.1µF, tssr1 is calculated as 4ms. b) The time to charge the capacitor from 0.9V to 1.4V (driver is enabled but output duty cycle is 0) 12 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) t ssr 2 = CSS (1.4 − 0.9)V 20µA Vo (V) (1- h)/h 0.6 0.2 0.9 0.8 806 1K 1.2 1.4 1.4K 1K 1.5 2 2K 1K 1.8 2.6 2.5 4 3.3 5.6 When CSS = 0.1µF, tssr2 is calculated as 2.5ms. Note that during this period, the converter does not start switching until SS/EN reaches 1.4V. c) The effective start-up time is: t sse = 32 200KHz Ro1 (Ohm) 200 Ro2 (Ohm) 1K 2.61K 4.02K 5.62K 1K 1K 1K Assuming inductor current hitting current limit for 32 cycles after SS/EN reaches 1.4V and fs=200KHz. The average inductor current is then: ILeff = ILIM t sse t ssr1 + t ssr 2 Only the voltages in boldface can be precisely set with standard 1% resistors. From this table, one may also observe that when the value 1 − h Vo − 0.5 = h 0.5 and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value resistors to exactly set up the required output voltage value. In buck-boost converter, output voltage is set by ILeff ≈ 0.025 ILIM and is independent of the soft start capacitor value. The converter will not overheat in hiccup. Setting the Output Voltage The non-inverting input of the error amplifier is brought out as a device pin (Pin 9) to which the user can connect Pin 4 or an external voltage reference. A simple voltage divider (Ro1 at top and Ro2 at bottom) sets the converter output voltage. In buck converter, the voltage feedback gain (h=0.5/Vo ) is related to the divider resistors value as: R o2 = h R o1 1− h R o2 = 0.5 Ro1 VO The input bias current of the error amplifier also causes an error in setting the output voltage. The inverting input bias currents of error amplifiers is -100nA. Since the non-inverting input is biased to 0.5V in buck converter, the percentage error in the second output voltage will be –100% · (0.1µA) · R R /[0.5 · (R +R ) ]. To keep o1 o2 o1 o2 this error below 0.2%, R //R < 10kΩ. o1 o2 Loop Compensation SC4508A is a current-mode controller. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner currentloop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This pole-splitting property of current-mode control greatly simplifies loop compensation. Once either R o1 o r R o2 i s chosen, the other can be calculated for the desired output voltage Vo. Since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the converter output voltage. This non-random error is caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. The following table lists a few standard resistor combinations for realizing some commonly used output voltages.  2007 Semtech Corp. 13 www.semtech.com SC4508A POWER MANAGEMENT Application Information (Cont.) The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. For stable operation above 50% duty-cycle, a compensation ramp is added to the sensed-current. In the SC4508A the compensation ramp is made switching frequency dependent. The slope of the compensation ramp is: h= 0.5 Vo For the rated output current Io, the current sensing gain k is fixed as: k= 1 8 ⋅ RS S e = 500 * fsmV The slope of the internal compensation ramp is above the minimal slope requirement for current loop stability and is sufficient for all the applications. With the inner current loop stable, the output voltage is then regulated with the outer voltage feedback loop. A simplified equivalent circuit model of the buck converter with current mode control is shown in Figure 7. From Figure 7, the transfer function from the voltage error amplifier output (vc ) to the converter output (vo )is: s Vo (s) s z1 := Gvc (s) = kR o s Vc (s) 1+ sp1 1+ where, the single dominant pole is: sp1 = 1 (R o + R oesr )Co and the zero due to the output capacitor ESR is: s z1 = 1 R oesr Co The dominant pole moves as output load varies. The controller transfer function (from the converter output (vo ) to the voltage error amplifier output (vc) is: k s sz2 gm Gc ( s ) = s(C 2 + C3 ) 1 + s sp 2 1+ where sz2 = 1 R 2C 2 Figure 7. A simple model of buck converter with current mode control. The transconductance error amplifier (in the SC4508A) has a gain (g m ) of 100µA/V. The target of the compensation design is to select the compensation network consisting of C 2, C 3 a nd R 2, along with the feedback resistors Ro1, Ro2 and the current sensing gain, such that the converter output voltage is regulated with satisfactory dynamic performance. With the output voltage Vo known, the feedback gain h and the feedback resistor values are determined using the equations given in the “Output Voltage Setting” section with:  2007 Semtech Corp. and sp 2 = 1 C 2C 3 R2 C 2 + C3 The loop transfer function is then: T(s)=Gvc(s)GC(s)h To simplify design, we assume that C3