SLE4432C

ICs for Chip Cards Intelligent 256-Byte EEPROM SLE 4432/SLE 4442 Data Sheet 07.95 Semiconductor Group -1 Edition 07.95 This edition was realized using the software system FrameMaker‚. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. ICs for Chip Cards Intelligent 256-Byte EEPROM SLE 4432/SLE 4442 Data Sheet 07.95 SLE 4432/SLE4442 Revision History: Previous Releases: Page 01.94 Original Version 07.95 Subjects (changes since last revision) Editorial changes This edition was realized using the software system FrameMaker® Important: For further information please contact: Siemens Semiconductor Group in Munich, Germany, Key Account Service Chip Card ICs and Identsystem ICs, Tel.: + 49 89 4144-4362, Fax + 49 89 4144-2360 The supply of this component does not include a licence for its use in smart card applications. This licence is due to: INNOVATRON Patents 137 Boulevard de Sébastopol, 75002 Paris, France, Fax + 33 1 40 13 39 09 General Information Contents 1 2 2.1 2.2 2.2.1 2.2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.4 2.5 2.6 2.7 2.8 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 4 Page Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset and Answer-to-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Main Memory (SLE 4432 and SLE 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Protection Memory (SLE 4432 and SLE 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Update Main Memory (SLE 4432 and SLE 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Protection Memory (SLE 4432 and SLE 4442) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Security Memory (SLE 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Update Security Memory (SLE 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Compare Verification Data (SLE 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PSC Verification (SLE 4442 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reset Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Coding of the Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operational Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 27 27 28 29 Package and Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Semiconductor Group 3 Published by Semiconductor Group Siemens Aktiengesellschaft Semiconductor Group 4 Ordering No. B116-H6695-G1-X-7600 Printed in Germany DA 07952. Intelligent 256-Byte EEPROM with Write Protect Function Intelligent 256-Byte EEPROM with Write Protect Function and Programmable Security Code (PSC) SLE 4432 SLE 4442 Features q 256 × 8-bit EEPROM organization q Byte-wise addressing q Irreversible byte-wise write protection of lowest q q q q q q q q 32 addresses (Byte 0 ... 31) 32 × 1-bit organization of protection memory Two-wire link protocol End of processing indicated at data output Answer-to-Reset acc. to ISO standard 7816-3 Programming time 2.5 ms per byte for both erasing and writing Minimum of 104 write/erase cycles1) Data retention for minimum of ten years1) Contact configuration and serial interface in accordance with ISO standard 7816 (synchronous transmission) M2.2 Additional Feature of SLE 4442 q Data can only be changed after entry of the correct 3-byte programmable security code (security memory) Type SLE 4432 M2.2 SLE 4432 C SLE 4442 M2.2 SLE 4442 C Ordering Code on request on request on request on request Package Wire-Bonded Module M2.2 Chip Wire-Bonded Module M2.2 Chip 1) Values are temperature dependent, for further information please refer to your Siemens sales office. Semiconductor Group 5 07.95 SLE 4432 SLE 4442 1 Pin Configuration (top view) M2.2 (Card Contacts) Pin Definitions and Functions Card Contact C1 C2 C3 C4 C5 C6 C7 C8 Symbol VCC RST CLK N.C. GND N.C. I/O N.C. Function Supply voltage Reset Clock input Not connected Ground Not connected Bidirectional data line (open drain) Not connected SLE 4432/SLE 4442 comes as a M2.2 wire-bonded module for embedding in plastic cards or as a die for customer packaging. Semiconductor Group 6 SLE 4432 SLE 4442 2 Functional Description Block Diagram Semiconductor Group 7 SLE 4432 SLE 4442 2.1 Memory Overview Figure 1 Memory Overwiew SLE 4432 The SLE 4432 consists of 256 x 8 bit EEPROM main memory and a 32-bit protection memory with PROM functionality. The main memory is erased and written byte by byte. When erased, all 8 bits of a data byte are set to logical one. When written, the information in the individual EEPROM cells is, according to the input data, altered bit by bit to logical zeros (logical AND between the old and the new data in the EEPROM). Normally a data change consists of an erase and write procedure. It depends on the contents of the data byte in the main memory and the new data byte whether the EEPROM is really erased and/or written. If none of the 8 bits in the addressed byte requires a zeroto-one transition the erase access will be suppressed. Vice versa the write access will be suppressed if no one-to-zero transition is necessary. The write and the erase operation takes at least 2.5 ms each. Each of the first 32 bytes can be irreversibly protected against data change by writing the corresponding bit in the protection memory. Each data byte in this address range is assigned to one bit of the protection memory and has the same address as the data byte in the main memory which it is assigned to. Once written the protection bit cannot be erased (PROM). Semiconductor Group 8 SLE 4432 SLE 4442 SLE 4442 Additionally to the above functions the SLE 4442 provides a security code logic which controls the write/erase access to the memory. For this purpose the SLE 4442 contains a 4-byte security memory with an Error Counter EC (bit 0 to bit 2) and 3 bytes reference data. These 3 bytes as a whole are called Programmable Security Code (PSC). After power on the whole memory, except for the reference data, can only be read. Only after a successful comparison of verification data with the internal reference data the memory has the identical access functionality of the SLE 4432 until the power is switched off. After three successive unsuccessful comparisons the Error Counter blocks any subsequent attempt, and hence any possibility to write and erase. 2.2 Transmission Protocol The transmission protocol is a two wire link protocol between the interface device IFD and the integrated circuit IC. It is identical to the protocol type “S = A”. All data changes on I/O are initiated by the falling edge on CLK. The transmission protocol consists of the 4 modes: – – – – Reset and Answer-to-Reset Command Mode Outgoing Data Mode Processing Mode Operational modes Note: The I/O pin is open drain and therefore requires an external pull up resistor to achieve a high level. Semiconductor Group 9 SLE 4432 SLE 4442 2.2.1 Reset and Answer-to-Reset Answer-to-Reset takes place according to ISO standard 7816-3 (ATR). The reset can be given at any time during operation. In the beginning, the address counter is set to zero together with a clock pulse and the first data bit (LSB) is output to I/O when RST is set from level H to level L. Under a continuous input of additional 31 clock pulses the contents of the first 4 EEPROM addresses is read out. The 33rd clock pulse switches I/O to high impedance Z and finishes the ATR procedure. Answer-to-Reset (Hex) Byte 1 DO7 … DO0 Byte 2 DO15 … DO8 Byte 3 DO23 … DO16 Byte 4 DO31 … DO24 Figure 2 Reset and Answer-to-Reset 2.2.2 Operational Modes Command Mode After the Answer-to-Reset the chip waits for a command. Every command begins with a start condition, includes a 3 bytes long command entry followed by an additional clock pulse and ends with a stop condition. – Start condition: Falling edge on I/O during CLK in level H – Stop condition: Rising edge on I/O during CLK in level H After the reception of a command there are two possible modes: – Outgoing data mode for reading – Processing mode for writing and erasing Semiconductor Group 10 SLE 4432 SLE 4442 Outgoing Data Mode In this mode the IC sends data to the IFD. The first bit becomes valid on I/O after the first falling edge on CLK. After the last data bit an additional clock pulse is necessary in order to set I/O to high impedance Z and to prepare the IC for a new command entry. During this mode any start and stop condition is discarded. Processing Mode In this mode the IC processes internally. The IC has to be clocked continuously until I/O, which was switched to level L after the first falling edge of CLK, is set to high impedance level Z. Any start and stop condition is discarded during this mode. Note: The RST line is low during the modes mentioned above. If RST is set to high during the CLK low level any operation is aborted and I/O is switched to high impedance Z (Break). Figure 3 Operational Modes Semiconductor Group 11 SLE 4432 SLE 4442 2.3 Commands Command Format Each command consists of three bytes: MSB Control LSB MSB Address LSB MSB Data LSB & & & & & & & & % % % % % % % % ( ( ( ( ( ( ( ( Beginning with the control byte LSB is transmitted first. Figure 4 Command Mode The SLE 4432 provides 4 commands which are listed in table 1. Additionally to these commands the SLE 4442 provides 3 commands which can be found in table 2. Semiconductor Group 12 SLE 4432 SLE 4442 Table 1 Byte 1 Control B7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 Byte 2 Byte 3 Address Data D7-D0 no effect READ MAIN MEMORY outgoing data processing address address no effect address Operation Mode B6 B5 B4 B3 B2 B1 B0 A7-A0 input data UPDATE MAIN MEMORY no effect READ PROTECTION outgoing MEMORY data processing input data WRITE PROTECTION MEMORY Table 2 SLE 4442 only 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 no effect address address no effect READ SECURITY MEMORY outgoing data processing input data UPDATE SECURITY MEMORY input data COMPARE processing VERIFICATION DATA Semiconductor Group 13 SLE 4432 SLE 4442 2.3.1 Read Main Memory (SLE 4432 and SLE 4442) The command reads out the contents of the main memory (with LSB first) starting at the given byte address (N = 0…255) up to the end of the memory. After the command entry the IFD has to supply sufficient clock pulses. The number of clocks is m = (256 – N) × 8 + 1. The read access to the main memory is always possible. Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Memory Security Memory (only SLE 4442) – – – – Reference Data Byte 3 (D7 … D0) Reference Data Byte 2 (D7 … D0) Reference Data Byte 1 (D7 … D0) Error Counter Data Byte 255 (D7 … D0) – – – : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Protection Bit 31 (D31) – Command: READ MAIN MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 30H B3 0 B2 0 B1 0 B0 0 Address A7…A0 Address 00H…FFH Data D7…D0 No effect No effect Figure 5 Read Main Memory Semiconductor Group 14 SLE 4432 SLE 4442 2.3.2 Read Protection Memory (SLE 4432 and SLE 4442) The command transfers the protection bits under a continuous input of 32 clock pulses to the output. I/O is switched to high impedance Z by an additional pulse. The protection memory can always be read, and indicates the data bytes of the main memory protected against changing. Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Memory Security Memory (only SLE 4442) – – – – Reference Data Byte 3 (D7 … D0) Reference Data Byte 2 (D7 … D0) Reference Data Byte 1 (D7 … D0) Error Counter Data Byte 255 (D7 … D0) – – – : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Protection Bit 31 (D31) – Command: READ PROTECTION MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 34H B3 0 B2 1 B1 0 B0 0 Address A7…A0 No effect No effect Data D7…D0 No effect No effect Figure 6 Read Protection Memory Semiconductor Group 15 SLE 4432 SLE 4442 2.3.3 Update Main Memory (SLE 4432 and SLE 4442) The command programs the addressed EEPROM byte with the data byte transmitted. Depending on the old and new data, one of the following sequences will take place during the processing mode: – erase and write – write without erase – erase without write (5 ms) corresponding to m = 255 clock pulses (2.5 ms) corresponding to m = 124 clock pulses (2.5 ms) corresponding to m = 124 clock pulses (All values at 50 kHz clock rate.) Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Memory Security Memory (only SLE 4442) – – – – Reference Data Byte 3 (D7 … D0) Reference Data Byte 2 (D7 … D0) Reference Data Byte 1 (D7 … D0) Error Counter Data Byte 255 (D7 … D0) – – – : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Protection Bit 31 (D31) – Command: UPDATE MAIN MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 38H B3 1 B2 0 B1 0 B0 0 Address A7…A0 Address 00H…FFH Data D7…D0 Input data Input data Semiconductor Group 16 SLE 4432 SLE 4442 Figure 7 Erase and Write Main Memory Figure 8 Erase or Write Main Memory If the addressed byte is protected against changes (indicated by the associated written protection bit) the I/O is set to high impedance after the clock number 2 of the processing. Semiconductor Group 17 SLE 4432 SLE 4442 2.3.4 Write Protection Memory (SLE 4432 and SLE 4442) The execution of this command contains a comparison of the entered data byte with the assigned byte in the EEPROM. In case of identity the protection bit is written thus making the data information unchangeable. If the data comparison results in data differences writing of the protection bit will be suppressed. Execution times and required clock pulses see UPDATE MAIN MEMORY. Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Memory Security Memory (only SLE 4442) – – – – Reference Data Byte 3 (D7 … D0) Reference Data Byte 2 (D7 … D0) Reference Data Byte 1 (D7 … D0) Error Counter Data Byte 255 (D7 … D0) – – – : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Protection Bit 31 (D31) – Command: WRITE PROTECTION MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 3CH B3 1 B2 1 B1 0 B0 0 Address A7…A0 Address 00H…1FH Data D7…D0 Input data Input data Semiconductor Group 18 SLE 4432 SLE 4442 2.3.5 Read Security Memory (SLE 4442 only) Similar to the read command for the protection memory this command reads out the 4 bytes of the security memory. The number of clock pulses during the outgoing data mode is 32. I/O is switched to high impedance Z by an additional pulse. Without a preceeding successful verification of the PSC the output of the reference bytes is suppressed, that means I/O outputs state L for the reference data bytes. Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Memory Security Memory (only SLE 4442) – – – – Reference Data Byte 3(D7 … D0) Reference Data Byte 2(D7 … D0) Reference Data Byte 1(D7 … D0) Error Counter (0,0,0,0,0,D2,D1,D0) Data Byte 255 (D7 … D0) – – – : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Protection Bit 31 (D31) – Command: READ SECURITY MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 31H B3 0 B2 0 B1 0 B0 1 Address A7…A0 No effect No effect Data D7…D0 No effect No effect Figure 9 Read Security Memory Semiconductor Group 19 SLE 4432 SLE 4442 2.3.6 Update Security Memory (SLE 4442 only) Regarding the reference data bytes this command will only be executed if a PSC has been successfully verified before. Otherwise only each bit of the error counter (Address 0) can be written from “1” to “0”. The execution times and the required clock pulses are the same as described under UPDATE MAIN MEMORY. Command: UPDATE SECURITY MEMORY Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 39H B3 1 B2 0 B1 0 B0 1 Address A7…A0 Address 00H…03H Data D7…D0 Input data Input data 2.3.7 Compare Verification Data (SLE 4442 only) This command can only be executed in combination with an update procedure of the error counter (see PSC verification). The command compares one byte of the entered verification data byte with the corresponding reference data byte. For this procedure clock pulses are necessary during the processing mode. Command: COMPARE VERIFICATION DATA Control B7 Binary Hexadecimal 0 B6 0 B5 1 B4 1 33H B3 0 B2 0 B1 1 B0 1 Address A7…A0 Address 00H…03H Data D7…D0 Input data Input data Figure 10 Compare Verification Data Semiconductor Group 20 SLE 4432 SLE 4442 2.4 PSC Verification (SLE 4442 only) The SLE 4442 requires a correct verification of the Programmable Security Code PSC stored in the Security Memory for altering data if desired. The following procedure has to be carried out exactly as described. Any variation leads to a failure, so that a write/erase access will not be achieved. As long as the procedure has not been successfully concluded the error counter bits can only be changed from “1” to “0” but not erased. At first an error counter bit has to be written to “0” by an UPDATE command (see figure 11) followed by three COMPARE VERIFICATION DATA commands beginning with byte 1 of the reference data. A successful conclusion of the whole procedure can be recognized by being able to erase the error counter which is not automatically erased. Now write/erase access to all memory areas is possible as long as the operating voltage is applied. In case of error the whole procedure can be repeated as long as erased counter bits are available. Having been enabled, the reference data are allowed to be altered like any other information in the EEPROM. The following table gives an overview of the necessary commands for the PSC verification. The sequence of the shaded commands is mandatory. Command Read security Memory Update Security Memory Control B7…B0 31H 39H Address A7…A0 No effect 00H Data D7…D0 No effect Input data Check Error Counter Write free bit in Error Counter input data: 0000 0ddd binary Reference Data Byte 1 Reference Data Byte 2 Reference Data Byte 3 Erase Error Counter Check Error Counter Remark Compare Verification Data Compare Verification Data Compare Verification Data Update Security Memory Read Security Memory 33H 33H 33H 39H 31H 01H 02H 03H 00H No effect Input data Input data Input data FFH No effect As shipped, the PSC is programmed with a code according to individual agreement with the customer. Thus, knowledge of this code is indispensable to alter data. Semiconductor Group 21 SLE 4432 SLE 4442 Figure 11 Verification Procedure Semiconductor Group 22 SLE 4432 SLE 4442 2.5 Reset Modes Reset and Answer-to-Reset (compare 2.2.1) Power on Reset After connecting the operating voltage to VCC, I/O is high impedance Z. By all means, a read access to any address or an Answer-to-Reset must be carried out before data can be altered. 2.6 Break If RST is set to high during CLK in state L any operation is aborted and I/O is switched to high impedance Z. Minimum duration of tRES = 5 µs is necessary to trigger a defined valid reset. After Break the chip is ready for further operations. 2.7 Failures Behavior in case of failures: In case of one of the following failures, the chip sets the I/O to high impedance Z after 8 clock pulses at the latest. Possible failures: – – – – – 2.8 Comparison unsuccessful Wrong command Wrong number of command clock pulses Write/erase access to already protected bytes Rewriting and erasing of a bit in the protection memory Coding of the Chip Due to security purposes every chip is irreversibly coded by a scheme. By this way fraud and misuse is excluded. The relevant data are programmed in the memory area from address 0 to 31. Afterwards the associated protection bits are programmed. As an example, figures 12 and 13 show ATR and Directory Data of Structure 1. When delivered, ATR header, ICM and ICT are programmed. Siemens programs also the AID. The AID (Application IDentifier) consists of 5 byte RID (Registered application provider IDentifier) administered by a national registration authority and of up to 11 byte PIX (Proprietary application Identifier eXtension). There are two possibilities: the customers AID or Siemens AID (only for sample quantities). Depending on the agreement between the customer and Siemens ICCF can be also programmed before delivery. Semiconductor Group 23 SLE 4432 SLE 4442 Figure 12 Synchronous Transmission ATR and Directory Data of Structure 1 Semiconductor Group 24 SLE 4432 SLE 4442 Figure 13 Answer-to-Reset for Synchronous Transmission Coding of Structure 1 Semiconductor Group 25 SLE 4432 SLE 4442 3 3.1 Operational Information Memory Map Protection Memory Security Memory (only SLE 4442) Address Main Memory (decimal) 255 : 32 31 : 3 2 1 0 Data Byte 255 (D7 … D0) : Data Byte 32 (D7 … D0) Data Byte 31 (D7 … D0) : Data Byte 3 (D7 … D0) Data Byte 2 (D7 … D0) Data Byte 1 (D7 … D0) Data Byte 0 (D7 … D0) Protection Bit 31 (D31) : Protection Bit 3 (D3) Protection Bit 2 (D2) Protection Bit 1 (D1) Protection Bit 0 (D0) Reference Data Byte 3 (D7 … D0) Reference Data Byte 2 (D7 … D0) Reference Data Byte 1 (D7 … D0) Error Counter (0,0,0,0,0,D2,D1,D0) The Data bytes 0 to 31 can be protected against further changes by programming the associated protection bit 0 to 31. The SLE 4442 allows data changing only after correct verification of the Reference Data bytes. Reading of the Data bytes and of the associated protection bits is always possible. 3.2 Electrical Characteristics 3.2.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage (any pin) Storage temperature Power dissipation Symbol Limit Values min. max. 6.0 6.0 125 70 V V °C mW – 0.3 – 0.3 – 40 Unit VCC VI Tstg Ptot Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability, including EEPROM data retention and write/erase endurance. In the operating range the functions given in the circuit description are fulfilled. Semiconductor Group 26 SLE 4432 SLE 4442 3.2.2 Operation Range Parameter Supply voltage Supply current Ambient temperature Symbol min. Limit Values typ. 5.0 3 0 max. 5.25 10 70 V mA °C – 4.75 Unit Test Condition VCC ICC TA VCC = 5 V – 3.2.3 DC Characteristics Parameter Symbol min. High level input voltage VIH (I/O, CLK, RST) Low level input voltage (I/O, CLK, RST) 3.5 0 Limit Values typ. max. Unit V V µA mA 50 10 µA pF Test Condition – VCC 0.8 50 VIL – VIH = 5 V VOL = 0.4 V, open drain VOH = 5 V, open drain High level input current IIH (I/O, CLK, RST) Low level output current (I/O) High level output current (I/O) Input capacitance IOL IOH CI 1 Semiconductor Group 27 SLE 4432 SLE 4442 3.2.4 AC Characteristics The AC characteristics refer to the timing diagrams in the following. VIHmin and VILmax are reference levels for measuring timing of signals. Parameter RST High to CLK Setup time CLK Low to RST Hold time RST High time (address reset) RST Low to I/O Valid time RST Low to CLK Setup time CLK Frequency CLK Rise time CLK Fall time CLK High time CLK Low time CLK Low to I/O Valid time Reset time for Break RST High to I/O Clear time (Break) I/O High time (Start Condition) CLK High to I/O Hold time I/O Low to CLK Hold time (Start Condition) I/O Setup to CLK High time CLK Low to I/O Hold time CLK High to I/O Clear time (Stop Condition) CLK Low to I/O Valid time CLK Low to I/O Valid time CLK Low to I/O Clear time Erase time Write time Power on reset time Symbol min. Limit Values typ. max. µs µs 50 2.5 4 7 50 1 1 9 9 2.5 5 2.5 10 4 4 1 1 4 2.5 2.5 2.5 2.5 2.5 100 µs µs µs kHz µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs ms ms µs 4 4 20 Unit Test Condition t10 t11 t12 t13 t14 fCLK tR tF t15 t16 t17 t18 t19 t1 t2 t3 t4 t5 t6 t7 t8 t9 tER tWR tPOR fCLK = 50 kHz fCLK = 50 kHz Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25 °C and the given supply voltage. Semiconductor Group 28 SLE 4432 SLE 4442 3.3 Timing Diagrams Figure 14 Reset and Answer-to-Reset Figure 15 Command Mode Semiconductor Group 29 SLE 4432 SLE 4442 Figure 16 Outgoing Data Mode Figure 17 Processing Mode Semiconductor Group 30 SLE 4432 SLE 4442 Figure 18 Break Semiconductor Group 31 SLE 4432 SLE 4442 4 Package and Dimensions Chip and Package Outlines Wire-Bonded Module M2.2 Semiconductor Group 32 SLE 4432 SLE 4442 Wafer Size: 5" Stepping Size: 1820 × 1850 µm2 Scribe Line: 80 µm Pad Size: 110 × 110 µm2 Chip Dimensions Semiconductor Group 33