S-7600A

S-7600A TCP/IP NETWORK STACK LSI - Revision 1.3 Hardware Specification S-7600A TCP/IP Network Stack LSI Components Marketing Dept. Marketing Section 2 Phone +81-43-211-1028 Fax +81-43-211-8035 8, Nakase 1-chome, Mihama-ku Chiba-shi, Chiba 261-8507, Japan Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 TABLE OF CONTENTS 1. INTRODUCTION........................................................................................................................... 1-1 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 1.7. 2. 3. PRODUCT OVERVIEW ............................................................................................................... 1-1 FEATURES ............................................................................................................................... 1-1 BENEFITS ................................................................................................................................. 1-1 TRADEMARKS ........................................................................................................................... 1-2 DEFINITIONS ............................................................................................................................ 1-2 APPLICABLE DOCUMENTS ......................................................................................................... 1-2 CAUTIONS ................................................................................................................................ 1-2 FUNCTIONAL BLOCK DIAGRAM ............................................................................................... 2-1 TERMINALS.................................................................................................................................. 3-1 3.1. 3.2. 3.3. 3.4. PIN ASSIGNMENT...................................................................................................................... 3-1 PACKAGE DIMENSIONS ............................................................................................................. 3-2 PIN DESCRIPTION ..................................................................................................................... 3-3 PIN CONFIGURATION ................................................................................................................ 3-4 4. ELECTRICAL CHARACTERISTICS............................................................................................. 4-1 4.1. 4.2. 4.3. 4.4. ABSOLUTE MAXIMUM RATINGS .................................................................................................. 4-1 RECOMMENDED OPERATING CONDITIONS ................................................................................. 4-1 DC CHARACTERISTICS ............................................................................................................. 4-2 POWER CURRENT CONSUMPTION ............................................................................................. 4-2 5. MPU INTERFACE ......................................................................................................................... 5-1 5.1. OVERVIEW ............................................................................................................................... 5-1 5.2. PARALLEL INTERFACE ............................................................................................................... 5-1 5.2.1. 68k Family MPU Mode.................................................................................................... 5-2 5.2.1.1. 5.2.1.2. Write Cycle Timing ................................................................................................................5-2 Read Cycle Timing ................................................................................................................5-3 Write Cycle Timing ................................................................................................................5-4 Read Cycle Timing ................................................................................................................5-5 5.2.2. x80 Family MPU Mode.................................................................................................... 5-4 5.2.2.1. 5.2.2.2. 5.3. SERIAL INTERFACE ................................................................................................................... 5-6 5.3.1. Write Cycle Timing.......................................................................................................... 5-6 5.3.2. Read Cycle Timing.......................................................................................................... 5-7 5.4. INTERRUPT............................................................................................................................... 5-8 6. MEMORY REQUIREMENTS ........................................................................................................ 6-1 6.1. 6.2. 6.3. 7. OVERVIEW ............................................................................................................................... 6-1 MEMORY INTERFACE ARCHITECTURE ........................................................................................ 6-1 MEMORY MAP .......................................................................................................................... 6-2 S-7600A REGISTER DEFINITIONS ............................................................................................. 7-1 7.1. OVERVIEW ............................................................................................................................... 7-1 7.2. IAPI REGISTER MAP................................................................................................................. 7-1 7.3. REGISTER DEFINITIONS ............................................................................................................ 7-4 7.3.1. Revision Register (0x00)................................................................................................ 7-4 7.3.2. General Control Register (0x01) .................................................................................... 7-4 7.3.3. Generic Socket Location Register (0x02) ...................................................................... 7-5 7.3.4. Master Interrupt (0x04) .................................................................................................. 7-5 7.3.5. Serial Port Configuration / Status Register (0x08) ......................................................... 7-6 7.3.6. Serial Port Interrupt Register (0x09) .............................................................................. 7-8 7.3.7. Serial Port Interrupt Mask Register (0x0A) .................................................................... 7-8 7.3.8. Serial Port Data Register (0x0B).................................................................................... 7-9 7.3.9. BAUD Rate Divider Registers (0x0C-0x0D)................................................................... 7-9 Seiko Instruments Inc. i TCP/IP Network Stack LSI S-7600A 7.3.10. 7.3.11. 7.3.12. 7.3.13. 7.3.14. 7.3.15. 7.3.16. 7.3.17. 7.3.18. 7.3.19. 7.3.20. 7.3.21. 7.3.22. 7.3.23. 7.3.24. 7.3.25. 7.3.26. 7.3.27. 7.3.28. 7.3.29. 7.3.30. 7.3.31. 7.3.32. 7.3.33. 7.3.34. 8. Hardware Specification Revision 1.3 Our IP Address Registers (0x10-0x13) ...................................................................... 7-9 Clock Divider Registers (0x1C-0x1D) ...................................................................... 7-10 Index Register (0x20) ............................................................................................... 7-10 Type of Service Register (TOS) (0x21) .................................................................... 7-10 Socket Config Status Low Register (0x22)............................................................... 7-11 Socket Status Mid Register (0x23)........................................................................... 7-13 Socket Activate Register (0x24) ............................................................................... 7-14 Socket Interrupt Register (0x26) .............................................................................. 7-14 Socket Data Available Register (0x28)..................................................................... 7-15 Socket Interrupt Mask Low Register (0x2A)............................................................. 7-16 Socket Interrupt Mask High Register (0x2B)............................................................ 7-16 Socket Interrupt Low Register (0x2C) ...................................................................... 7-17 Socket Interrupt High Register (0x2D) ..................................................................... 7-17 Socket Data Register (0x2E).................................................................................... 7-18 TCP Data Send and Buffer Out Length Registers (0x30-0x31) ............................... 7-18 Buffer In Length Registers (0x32-0x33) ................................................................... 7-18 Urgent Data Pointer Registers (0x34-0x35) ............................................................. 7-18 Their Port Registers (0x36-0x37) ............................................................................. 7-19 Our Port Registers (0x38-0x39) ............................................................................... 7-19 Socket Status High Register (0x3A)......................................................................... 7-19 Their IP Address Registers (0x3C-0x3F) ................................................................. 7-20 PPP Control and Status Register (0x60).................................................................. 7-21 PPP Interrupt Code (0x61) ....................................................................................... 7-22 PPP Max Retry, (0x62).............................................................................................. 7-22 PAP String (0x64)..................................................................................................... 7-23 DATA COMMUNICATIONS.......................................................................................................... 8-1 8.1. OVERVIEW ............................................................................................................................... 8-1 8.2. SERIAL PORT REGISTER MAP ................................................................................................... 8-1 8.2.1. Hardware Flow Control (RTS/CTS Handshaking) .......................................................... 8-2 8.2.2. Serial Port Control........................................................................................................... 8-2 8.3. TCP/UDP DATA COMMUNICATIONS .......................................................................................... 8-3 8.3.1. TCP Data Communications ............................................................................................ 8-3 8.3.2. UDP Data Communications ............................................................................................ 8-4 9. RESET FUNCTIONS .................................................................................................................... 9-1 9.1. OVERVIEW ............................................................................................................................... 9-1 9.1.1. Hardware Reset Function ............................................................................................... 9-1 9.1.2. Software Reset Function................................................................................................. 9-1 10. APPLICATION EXAMPLES........................................................................................................ 10-1 10.1.1. In Case of x80 Family MPU with LCD Controller .......................................................... 10-1 10.1.2. In Case of 68k Family MPU with LCD Controller .......................................................... 10-2 10.1.3. In Case of Serial Interface with LCD Controller ............................................................ 10-3 ii Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 LIST OF FIGURES FIGURE 2-1 FIGURE 3-1 FIGURE 3-2 FIGURE 3-3 FIGURE 5-1 FIGURE 5-2 FIGURE 5-3 FIGURE 5-4 FIGURE 5-5 FIGURE 5-6 FIGURE 5-7 FIGURE 6-1 FIGURE 8-1 FIGURE 9-1 FIGURE 9-2 FIGURE 10-1 FIGURE 10-2 FIGURE 10-3 BLOCK DIAGRAM ............................................................................................................... 2-1 PIN ASSIGNMENT .............................................................................................................. 3-1 PACKAGE DIMENSIONS ...................................................................................................... 3-2 CONFIGURATION OF EACH PIN ........................................................................................... 3-4 68K FAMILY MPU W RITE TIMING ....................................................................................... 5-2 68K FAMILY MPU READ TIMING ......................................................................................... 5-3 X80 FAMILY MPU W RITE CYCLE TIMING ............................................................................ 5-4 X80 FAMILY MPU READ CYCLE TIMING.............................................................................. 5-5 SERIAL INTERFACE W RITE TIMING ..................................................................................... 5-6 SERIAL INTERFACE READ TIMING ....................................................................................... 5-7 INT1 INTERRUPT TIMING ................................................................................................... 5-8 MEMORY INTERFACE ARCHITECTURE ................................................................................. 6-1 SERIAL DATA FORMAT ....................................................................................................... 8-1 HARDWARE RESET TIMING ................................................................................................ 9-1 SOFTWARE RESET TIMING ................................................................................................. 9-1 EXAMPLE FOR X80 FAMILY MPU...................................................................................... 10-1 EXAMPLE FOR 68K FAMILY MPU...................................................................................... 10-2 EXAMPLE FOR SERIAL INTERFACE .................................................................................... 10-3 Seiko Instruments Inc. iii TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 LIST OF TABLES TABLE 3-1 PIN ASSIGNMENT .................................................................................................................. 3-1 TABLE 3-2 PIN DESCRIPTION.................................................................................................................. 3-3 TABLE 4-1 ABSOLUTE MAXIMUM RATINGS .............................................................................................. 4-1 TABLE 4-2 RECOMMENDED OPERATING CONDITIONS .............................................................................. 4-1 TABLE 4-3 DC CHARACTERISTICS .......................................................................................................... 4-2 TABLE 4-4 POWER CURRENT CONSUMPTION .......................................................................................... 4-2 TABLE 5-1 INTERFACE SELECTION.......................................................................................................... 5-1 TABLE 5-2 CONNECTION RELATIONSHIP BETWEEN MPU AND PINS .......................................................... 5-1 TABLE 5-3 68K FAMILY MPU W RITE CYCLE TIMING ................................................................................ 5-2 TABLE 5-4 68K FAMILY MPU READ CYCLE TIMING ................................................................................. 5-3 TABLE 5-5 X80 FAMILY MPU W RITE CYCLE TIMING ................................................................................ 5-4 TABLE 5-6 X80 FAMILY MPU READ CYCLE TIMING ................................................................................. 5-5 TABLE 5-7 SERIAL INTERFACE W RITE CYCLE TIMING .............................................................................. 5-6 TABLE 5-8 SERIAL INTERFACE READ CYCLE TIMING ................................................................................ 5-7 TABLE 5-9 INTERRUPT SELECTION TABLE ............................................................................................... 5-8 TABLE 6-1 S-7600A MEMORY MAP (BANK 0) ......................................................................................... 6-2 TABLE 6-2 S-7600A MEMORY MAP (BANK 1) ......................................................................................... 6-2 TABLE 7-1 IAPI REGISTER MAP ............................................................................................................. 7-2 TABLE 7-2 IAPI REGISTER MAP (CONTINUED) ........................................................................................ 7-3 TABLE 7-3 REVISION REGISTER BIT DEFINITIONS .................................................................................... 7-4 TABLE 7-4 REVISION REGISTER DESCRIPTION ........................................................................................ 7-4 TABLE 7-5 GENERAL CONTROL REGISTER BIT DEFINITIONS .................................................................... 7-4 TABLE 7-6 GENERAL CONTROL REGISTER DESCRIPTION......................................................................... 7-4 TABLE 7-7 GENERIC SOCKET LOCATION REGISTER BIT DEFINITIONS ....................................................... 7-5 TABLE 7-8 GENERIC SOCKET LOCATION REGISTER DESCRIPTION ........................................................... 7-5 TABLE 7-9 MASTER INTERRUPT REGISTER BIT DEFINITIONS .................................................................... 7-5 TABLE 7-10 MASTER INTERRUPT REGISTER DESCRIPTIONS (CONTINUED) ............................................... 7-6 TABLE 7-11 CONF STATUS REGISTER BIT DEFINITIONS ........................................................................... 7-6 TABLE 7-12 CONF STATUS REGISTER DESCRIPTION ............................................................................... 7-7 TABLE 7-13 SERIAL PORT INTERRUPT REGISTER BIT DEFINITIONS .......................................................... 7-8 TABLE 7-14 SERIAL PORT INTERRUPT REGISTER DESCRIPTION ............................................................... 7-8 TABLE 7-15 SERIAL PORT INTERRUPT MASK REGISTER BIT DEFINITIONS ................................................. 7-8 TABLE 7-16 SERIAL PORT INTERRUPT MASK REGISTER DESCRIPTION ..................................................... 7-8 TABLE 7-17 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X10) .......................................................... 7-9 TABLE 7-18 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X11) .......................................................... 7-9 TABLE 7-19 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X12) ........................................................ 7-10 TABLE 7-20 OUR IP ADDRESS REGISTER BIT DEFINITIONS (0X13) ........................................................ 7-10 TABLE 7-21 INDEX REGISTER BIT DEFINITION ....................................................................................... 7-10 TABLE 7-22 INDEX REGISTER DESCRIPTION.......................................................................................... 7-10 TABLE 7-23 SOCKET CONFIG STATUS LOW REGISTER BIT DEFINITIONS ................................................ 7-11 TABLE 7-24 SOCKET CONFIG STATUS LOW REGISTER DESCRIPTION ..................................................... 7-12 TABLE 7-25 SOCKET STATUS MID REGISTER BIT DEFINITIONS .............................................................. 7-13 TABLE 7-26 SOCKET STATUS MID REGISTER DESCRIPTION................................................................... 7-13 TABLE 7-27 SOCKET ACTIVATE REGISTER BIT DEFINITIONS .................................................................. 7-14 TABLE 7-28 SOCKET ACTIVATE REGISTER DESCRIPTION....................................................................... 7-14 TABLE 7-29 SOCKET INTERRUPT REGISTER BIT DEFINITIONS ................................................................ 7-14 TABLE 7-30 SOCKET INTERRUPT REGISTER DESCRIPTION .................................................................... 7-15 TABLE 7-31 SOCKET DATA AVAIL REGISTER BIT DEFINITIONS ............................................................... 7-15 TABLE 7-32 SOCKET DATA AVAIL REGISTER DESCRIPTION ................................................................... 7-15 TABLE 7-33 SOCKET INTERRUPT MASK LOW REGISTER BIT DEFINITIONS .............................................. 7-16 TABLE 7-34 SOCKET INTERRUPT MASK LOW REGISTER DESCRIPTION ................................................... 7-16 TABLE 7-35 SOCKET INTERRUPT MASK HIGH REGISTER BIT DEFINITIONS .............................................. 7-16 TABLE 7-36 SOCKET INTERRUPT MASK HIGH REGISTER DESCRIPTION .................................................. 7-16 TABLE 7-37 SOCKET INTERRUPT LOW REGISTER BIT DEFINITIONS ........................................................ 7-17 TABLE 7-38 SOCKET INTERRUPT LOW REGISTER DESCRIPTION............................................................. 7-17 TABLE 7-39 SOCKET INTERRUPT HIGH REGISTER BIT DEFINITIONS ....................................................... 7-17 iv Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 TABLE 7-40 SOCKET INTERRUPT HIGH REGISTER DESCRIPTION ............................................................ 7-18 TABLE 7-41 THEIR PORT REGISTER BIT DEFINITIONS (0X36) ................................................................ 7-19 TABLE 7-42 THEIR PORT REGISTER BIT DEFINITIONS (0X37) ................................................................ 7-19 TABLE 7-43 OUR PORT REGISTER BIT DEFINITIONS (0X38)................................................................... 7-19 TABLE 7-44 OUR PORT REGISTER BIT DEFINITIONS (0X39)................................................................... 7-19 TABLE 7-45 SOCKET STATUS HIGH REGISTER BIT DEFINITIONS ............................................................. 7-19 TABLE 7-46 SOCKET STATUS HIGH REGISTER DESCRIPTION ................................................................. 7-20 TABLE 7-47 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3C) ..................................................... 7-20 TABLE 7-48 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3D) ..................................................... 7-20 TABLE 7-49 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3E)...................................................... 7-20 TABLE 7-50 THEIR IP ADDRESS REGISTER BIT DEFINITIONS (0X3F) ...................................................... 7-20 TABLE 7-51 PPP CONTROL AND STATUS REGISTER BIT DEFINITIONS (0X60) ........................................ 7-21 TABLE 7-52 PPP CONTROL STATUS REGISTER DESCRIPTION ............................................................... 7-21 TABLE 7-53 PPP INTERRUPT CODE REGISTER BIT DEFINITIONS ........................................................... 7-22 TABLE 7-54 PPP INTERRUPT ERROR CODES ........................................................................................ 7-22 TABLE 7-55 PPP MAX RETRY REGISTER.............................................................................................. 7-22 TABLE 7-56 PAP STRING FORMAT ....................................................................................................... 7-23 TABLE 7-57 PAP STRING EXAMPLE...................................................................................................... 7-23 TABLE 8-1 SERIAL PORT REGISTER MAP ................................................................................................ 8-1 TABLE 8-12 HEADER STRUCTURE .......................................................................................................... 8-5 Seiko Instruments Inc. v TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 1. Introduction 1.1. Product Overview The S-7600A is a LSI that integrates TCP/IP network stack. It offers your devices a quicker and easier connectivity to a network with its on-chip serial interface and a static RAM that operates as a buffer. Implementing this LSI into your system can significantly reduce your software development cost. Also its low operating frequency gives benefits to the power consumption. TM The S-7600A also supports a microprocessor interface via the iReady iAPI register set, and connection to Physical Transport Layer Interface. iAPI consists of a set of register and operating definitions that allow any micro controller system to interface with the internal modules. 1.2. Features Industry standard protocols support : TCP/IP (Ver. 4.0) PPP (STD-51-compliant) UDP General purpose sockets : Configured for two sockets MPU interface : 68k/x80(MOTO/Intel) bus interface or Synchronous serial interface Physical Transport Layer Interface : Universal Asynchronous Receiver/Transmitter (UART) Low clock rate : Multiplied four by the bit-rate Operating frequency : 256kHz typical Low power consumption : Full-transmitting Operating current consumption : 0.9mA typ. Non-transmitting Operating current consumption : 150µA typ. Standby current consumption : 1.0µA typ. Stand-by mode : held by RESET signal W ide operating voltage range : 2.4V to 3.6V Easier application development : TM portable iAPI support 1.3. Benefits Off-loads MIPS allowing system to operate with low end and low cost processors. Consumes minimal power-up to 1/100 of competing solution. Seiko Instruments Inc. 1-1 TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 1.4. Trademarks iReady iAPI and iAPI is a trademark of iReady Corporation. All other products and brand names are trademarks and registered trademarks of their respective companies. TM TM 1.5. Definitions IP PPP TCP UDP API Internet Protocol Point-to-Point Protocol Transmission Control Protocol User Datagram Protocol Application Programming Interface 1.6. Applicable Documents S-7600A Functional Specification S-7600A API Application Manual 1.7. Cautions 1. DO NOT apply a voltage or current that exceeds the absolute maximum ratings to terminals. If applied, the IC may malfunction or be destroyed. The standard values are set with sufficient margins, but use the IC within the recommended operating conditions to optimize device quality. Measures against static electricity 2.1 When transporting or storing ICs, use conductive containers or metal coated boxes. 2.2 Check that there is no current leakage in electrical facilities, and be sure to ground them. Also ensure that workbenches and people who handle ICs are grounded. Excessive external noise to the power supply or I/O terminals of CMOS ICs causes latch-up, leading to faults and damage. If latch-up has occurred, immediately turn off the device, eliminate the cause, and turn on the device again. Keep the IC away from mechanical vibration, shock, and sudden changes in temperature. These may cause wires to break. Environment 5.1 Use and store ICs below the absolute maximum rated temperature. 5.2 DO NOT use or store ICs where condensation can occur. 5.3 DO NOT use ICs where they are directly exposed to dust, salt, or acid gas such as SO2. These may cause leaks between element leads and cause corrosion. 5.4 To store ICs for a long time, DO NOT process them. During storage, DO NOT apply any load to ICs. 2. 3. 4. 5. 1-2 Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 2. Functional Block Diagram Figure 2-1 shows a functional block diagram of the S-7600A. There are blocks of the Network Stack and other functions related to it. The S-7600A has the interface for a host MPU and a Physical layer for various data terminal equipment. SD(7:0) CS PSX C86 RS READX WRITEX BUSYX INTCTL INT1 INT2X Network Stack UDP TCP SRAM Interface MPU Interface SRAM 10Kbytes IP PPP CLK RESETX Physical Layer Interface 16-byte 1-byte FIFO BUFFER S2P P2S Figure 2-1 The transport and network layers contain: Two general sockets that provide connectivity between the application layer and the transport layer. TCP/UDP module that allows for reliable (retransmission) and unreliable (no retransmission) datagram deliveries. IP module that provides connectionless packet delivery. PPP module that provides point-to-point connection link between two hosts. Seiko Instruments Inc. DSRX RTSX RXD RI DCD DTRX TXD CTSX Block Diagram 2-1 TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 3. Terminals 3.1. Pin Assignment Figure 3-1 shows Pin Assignment in Package. 36 INTCTRL WRITEX BUSYX READX INT2X 25 INT1 VSS PSX C86 37 SD7 NC TI2 SD6 TI1 VDD SD5 SD4 SD3 SD2 SD1 TI3 CS RS TI4 TI5 TI6 TI7 VDD TO1 TO2 TO3 TO4 TO5 TO6 TO7 24 48 SD0 13 RESETX DSRX DTRX CTSX RTSX TEST DCD RXD CLK 1 Figure 3-1Pin Assignment Table 3-1 shows signal names, listed by Pin Number. Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Pin name RESETX TEST CLK VSS CTSX DSRX RI RXD DCD DTRX RTSX TXD Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 Table 3-1 Pin name TO7 TO6 TO5 TO4 TO3 TO2 TO1 VDD TI7 TI6 TI5 TI4 Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 TXD 12 VSS RI Pin name TI3 RS CS C86 READX VSS PSX WRITEX INTCTRL INT1 INT2X BUSYX Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 Pin name SD7 NC TI2 SD6 TI1 VDD SD5 SD4 SD3 SD2 SD1 SD0 Pin Assignment 3-1 Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 3.2. Package Dimensions S-7600A is housed in a 48-pin QFP package with 0.5mm pin pitch spacing. The package layout is depicted in Figure 3-2. 9.0±0.3 7.0 36 25 37 24 9.0±0.3 7.0 48 13 0.5±0.3 12 1 0.15 +0.10 -0.06 1.40±0.20 0.50 0~ 0.20 +0.10 0.20 -0.05 1.7m ax. UNIT:m m Figure 3-2 Package Dimensions Seiko Instruments Inc. 3-2 TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 3.3. Pin Description The pins and signal descriptions are listed by function in Table 3-2. Name VDD1,VDD2 VSS1,VSS2 RESETX TEST, TI1 to TI7 TO1 to TO7 CLK CTSX DSRX RI RXD DCD DTRX RTSX TXD RS CS C86 Description Positive power supply GND potential Reset input Test input (pull-down resistor is built in) When normal use, connect to VSS or open O Test output When normal use, open I Clock input I Clear to send input I Data set ready input I Ring indicator input I Serial received data input I Data carrier detect input O Data terminal ready output O Request to send output O Serial transmit data output I Register selection input I Chip selection input I MPU interface mode selection input 68k mode : 1 x80 mode : 0 I x80 mode : read requirement input 68k mode : enable input I parallel/serial interface selection input I x80 mode : write requirement input 68k/Serial mode : read/write selection input I INT1/INT2X drive type(CMOS/OD) selection input *OT Interrupt output(active High) from S-7600A chip to MPU *OT Interrupt output(active Low) from S-7600A chip to MPU O busy indicator output *B x80/68k mode : data bus Serial mode : serial data input *B x80/68k mode : data bus Serial mode : serial clock input *B x80/68k mode : data bus Serial mode : serial data output *B Data bus *OT : Tri-state output *B : bi-directional Table 3-2 Pin Description I/O I I Type A B D C C C C C C D D D C C C READX PSX W RITEX INTCTRL INT1 INT2X BUSYX SD7 SD6 SD5 SD0 to SD4 C C C C E E D F F F F 3-3 Seiko Instruments Inc. TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 3.4. Pin Configuration Figure 3-3 shows configuration of each pin. A pad cin B pad cin Vss C pad cin D pad in E pad in F cin pad in oen oen Figure 3-3 Configuration of Each Pin Seiko Instruments Inc. 3-4 TCP/IP Network Stack LSI S-7600A Hardware Specification Revision 1.3 4. Electrical Characteristics 4.1. Absolute Maximum Ratings Parameter Storage temperature Operating temperature Power supply voltage Input voltage Output voltage Table 4-1 Symbol Tsta Topr VDD VIN VOUT Conditions Rating -40 to +125 -40 to +85 Unit °C °C V V V Ta=25°C Ta=25°C Ta=25°C -0.3 to +4.0 VSS-0.3 to VDD+0.3 VSS to VDD Absolute Maximum Ratings 4.2. Recommended Operating Conditions Parameter Operating Frequency range Clock Pulse width Operating voltage range Input voltage VIN Ta=-40 to +85°C 0 VDD V VDD Ta=-40 to +85°C 2.4 3.6 V Pw Ta=-40 to +85°C 80 nS Symbol FOPR Conditions Ta=-40 to +85°C Min. Typ. 0.256 Max. 5 Unit MHz Note 1 Note1: The clock is given by the CLK pin and needs to be as four times or more fast as the BAUD rate. (The multiplier is an integer whose tolerance is