4330-T-B1_B_470

Si4030/31/32-B1 es ig ns Si4030/31/32 ISM T RANSMITTER       Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors nSEL nIRQ XOUT XIN 20 19 18 17 16 TX 2 15 SCLK NC 3 14 SDI GND PAD NC 4 13 SDO NC 5 12 VDD_DIG 7 8 9 GPIO_2 6 10 11 NC Patents pending N ot R ec om Silicon Laboratories’ Si4030/31/32 devices are highly integrated, single-chip wireless ISM transmitters. The high-performance EZRadioPRO® family includes a complete line of transmitters, receivers, and transceivers allowing the RF system designer to choose the optimal wireless part for their application. The Si4030/31/32 offers advanced radio features including continuous frequency coverage from 240–960 MHz with adjustable power output levels of –8 to +13 dBm on the Si4030/31 and +1 to +20 dBm on the Si4032. Power adjustments are made in 3 dB steps. The Si4030/31/32’s high level of integration offers reduced BOM cost while simplifying the overall system design. The Si4032’s Industry leading +20 dBm output power ensures extended range and improved link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX FIFO, and automatic packet handling reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with global regulations including FCC, ETSI, and ARIB regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market. VDD_RF 1 VR_DIG Description Si4030/31/32 GPIO_1 Remote control Home security & alarm Telemetry Personal data logging Toy control Wireless PC peripherals m en de d       Pin Assignments SDN Applications Ordering Information: See page 53. GPIO_0     NC              Ultra low power shutdown mode Wake-up timer Integrated 32 kHz RC or 32 kHz XTAL Integrated voltage regulators Configurable packet handler TX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC –40 to +85 °C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 20-Pin QFN package Low BOM Power-on-reset (POR)   N ew  Frequency range 240–930 MHz (Si4031/32) 900–960 MHz (Si4030) Output Power Range +1 to +20 dBm (Si4032) –8 to +13 dBm (Si4030/31) Low Power Consumption Si4032 85 mA @ +20 dBm Si4030/31 30 mA @ +13 dBm Data Rate = 0.123 to 256 kbps FSK, GFSK, and OOK modulation Power Supply = 1.8 to 3.6 V fo r  D Features Rev 1.1 1/10 Copyright © 2010 by Silicon Laboratories Si4030/31/32 Si4030/31/32-B1 N ot R ec om m en de d fo r N ew D es ig ns Functional Block Diagram 2 Preliminary Rev. 0.1 Si4030/31/32-B1 TABLE O F C ONTENTS Page es ig ns Section N ot R ec om m en de d fo r N ew D 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.5. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.6. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 9. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10. Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12. Pin Descriptions: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Preliminary Rev. 0.1 3 Si4030/31/32-B1 N ot R ec om m en de d fo r N ew D es ig ns 14. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.1. Si4030/31/32 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 15. Package Outline: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 16. PCB Land Pattern: Si4030/31/32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4 Preliminary Rev. 0.1 Si4030/31/32-B1 L I S T OF F IGURES N ot R ec om m en de d fo r N ew D es ig ns Figure 1. SPI Timing.................................................................................................................. 15 Figure 2. SPI Timing—READ Mode ..........................................................................................16 Figure 3. SPI Timing—Burst Write Mode .................................................................................. 16 Figure 4. SPI Timing—Burst Read Mode .................................................................................. 16 Figure 5. State Machine Diagram.............................................................................................. 17 Figure 6. TX Timing................................................................................................................... 21 Figure 7. Frequency Deviation .................................................................................................. 25 Figure 8. FSK vs. GFSK Spectrums..........................................................................................27 Figure 9. Microcontroller Connections....................................................................................... 30 Figure 10. PLL Synthesizer Block Diagram............................................................................... 31 Figure 11. FIFO Threshold ........................................................................................................34 Figure 12. Packet Structure....................................................................................................... 35 Figure 13. Multiple Packets in TX Packet Handler .................................................................... 36 Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37 Figure 15. Manchester Coding Example ...................................................................................37 Figure 16. POR Glitch Parameters............................................................................................ 39 Figure 17. General Purpose ADC Architecture ......................................................................... 41 Figure 18. Temperature Ranges using ADC8 ........................................................................... 43 Figure 19. WUT Interrupt and WUT Operation.......................................................................... 46 Figure 20. Si4031 Reference Design Schematic ...................................................................... 48 Figure 21. 20-Pin Quad Flat No-Lead (QFN) ............................................................................54 Figure 22. PCB Land Pattern .................................................................................................... 55 Preliminary Rev. 0.1 5 Si4030/31/32-B1 L I S T OF TABLES N ot R ec om m en de d fo r N ew D es ig ns Table 1. DC Characteristics1 ......................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8 Table 3. Transmitter AC Electrical Characteristics1 ...................................................................9 Table 4. Auxiliary Block Specifications1 ...................................................................................10 Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 11 Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 11 Table 7. Absolute Maximum Ratings ........................................................................................ 12 Table 8. Operating Modes ........................................................................................................14 Table 9. Serial Interface Timing Parameters ............................................................................15 Table 10. Operating Modes Response Time ............................................................................17 Table 11. Frequency Band Selection ....................................................................................... 23 Table 12. Packet Handler Registers ......................................................................................... 36 Table 13. POR Parameters ...................................................................................................... 39 Table 14. Temperature Sensor Range ..................................................................................... 42 Table 15. Register Descriptions ............................................................................................... 50 Table 16. Package Dimensions ................................................................................................ 54 Table 17. PCB Land Pattern Dimensions ................................................................................. 56 Preliminary Rev. 0.1 6 Si4030/31/32-B1 1. Electrical Specifications Table 1. DC Characteristics1 Min Typ Supply Voltage Range VDD 1.8 3.0 3.6 V Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF2 — 15 50 nA IStandby Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF — 450 800 nA ISleep RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF — 1 — µA ISensor-LBD Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA ISensor-TS Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF2 — 1 — µA IReady Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled — 800 — µA ITune Synthesizer and regulators enabled — 8.5 — mA TX Mode Current —Si4032 ITX_+20 txpow[2:0] = 111 (+20 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. — 85 — mA TX Mode Current —Si4030/31 ITX_+13 txpow[2:0] = 111 (+13 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. — 30 — mA ITX_+1 txpow[2:0] = 011 (+1 dBm) Using Silicon Labs’ Reference Design. TX current consumption is dependent on match and board layout. — 18 — mA N ew fo r m en de d TUNE Mode Current Conditions Max Units es ig ns Symbol D Parameter N ot R ec om Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section on page 13. 2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 13. Preliminary Rev. 0.1 7 Si4030/31/32-B1 Table 2. Synthesizer AC Electrical Characteristics1 Parameter Symbol Conditions Min Typ Max Units — 930 MHz — 960 MHz 156.25 — Hz 312.5 — Hz — 1.6 V FSYN 240 Synthesizer Frequency Range—Si4030 FSYN 900 Synthesizer Frequency Resolution2 FRES-LB Low Band, 240–480 MHz — FRES-HB High Band, 480–960 MHz — fREF_LV When using external reference signal driving XOUT pin, instead of using crystal. Measured peak-to-peak (VPP) 0.7 Synthesizer Settling Time2 tLOCK Measured from exiting Ready mode with XOSC running to any frequency. Including VCO calibration. — 200 — µs Residual FM2 FRMS Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) — 2 4 kHzRMS Phase Noise2 L(fM) F = 10 kHz — –80 — dBc/Hz F = 100 kHz — –90 — dBc/Hz F = 1 MHz — –115 — dBc/Hz F = 10 MHz — –130 — dBc/Hz D N ew fo r m en de d Reference Frequency Input Level2 es ig ns Synthesizer Frequency Range—Si4031/32 N ot R ec om Notes: 1. All specification guaranteed by production test unless otherwise noted. Production test conditions and max limits are listed in the "Production Test Conditions" section on page 13. 2. Guaranteed by qualification. Qualification test conditions are listed in the "Production Test Conditions" section on page 13. 8 Preliminary Rev. 0.1 Si4030/31/32-B1 Table 3. Transmitter AC Electrical Characteristics1 Symbol Conditions Min Typ Max Units — 930 MHz TX Frequency Range—Si4031/32 FTX 240 TX Frequency Range—Si4030 FTX 900 FSK Data Rate2 DRFSK 0.123 DROOK 0.123 OOK Data Rate Modulation Deviation 256 kbps — 40 kbps ±320 kHz ∆f2 240–860 MHz ±0.625 ±160 kHz 0.625 — kHz +1 — +20 dBm –8 — +13 dBm — 3 — dB –40 to +85 C — 2 — dB Measured across any one frequency band — 1 — dB B*T Gaussian Filtering Bandwith Time Product — 0.5 — POB-TX1 POUT = 13 dBm, Frequencies