534JA622080BG

Si 5 34 P R E L I M I N A R Y D A TA S H E E T C R Y S TA L O S C I L L A T O R ( XO) (10 M H Z T O 1 .4 G H Z ) Features Available with any-rate output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz Four selectable output frequencies 3rd generation DSPLL® with superior jitter performance 3x better frequency stability than SAW-based oscillators Internal fixed crystal frequency ensures high reliability and low aging Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant Si5602 Ordering Information: See page 6. Applications SONET/SDH Networking SD/HD video Clock and data recovery FPGA/ASIC clock generation Pin Assignments: See page 5. (Top View) FS[1] 7 NC OE GND 1 2 3 8 FS[0] 6 5 4 VDD Description The Si534 quad frequency XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si534 is available with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, the Si534 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si534 IC-based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. CLK– CLK+ (LVDS/LVPECL/CML) FS[1] 7 NC OE GND 1 2 3 8 FS[0] 6 5 4 VDD Functional Block Diagram VDD CLK– CLK+ NC CLK FS[1] Fixed Frequency XO Any-rate 10–1400 MHz DSPLL® Clock Synthesis FS[0] (CMOS) OE GND Preliminary Rev. 0.4 5/06 Copyright © 2006 by Silicon Laboratories Si534 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5 34 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current IDD Output enabled TriState mode Output Enable (OE)2 VIH VIL Operating Temperature Range TA Min 2.97 2.25 1.71 — — 0.75 x VDD — –40 Typ 3.3 2.5 1.8 90 60 — — — Max 3.63 2.75 1.89 — — — 0.5 85 mA V Units V ºC Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details. 2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Symbol fO Test Condition LVPECL/LVDS/CML CMOS Min 10 10 — –20 –50 Typ — — ±1.5 — — — — — Max 945 160 — +20 +50 ±10 10 20 Units MHz Initial Accuracy fi Measured at +25 °C at time of shipping ppm ppm ppm ms ms Temperature Stability1,3 Aging Powerup Time4 Settling Time After FS[1:0] Change ∆f/fO Frequency drift over projected 15 year life fa tOSC tFRQ — — Both FS[1] and FS[0] changing simultaneously — Notes: 1. See Section 3. "Ordering Information" on page 6 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to fO. 2 Preliminary Rev. 0.4 S i534 Table 3. CLK± Output Levels and Symmetry Parameter LVPECL Output Option1 Symbol VO VOD VSE Test Condition mid-level swing (diff) swing (single-ended) mid-level swing (diff) Min VDD – 1.42 1.1 0.5 1.125 0.32 Typ — Max VDD – 1.25 1.9 0.93 1.275 0.50 Units V VPP VPP V VPP — — 1.20 0.40 LVDS Output Option2 VO VOD CML Output Option2 VO VOD mid-level swing (diff) IOH = 32 mA IOL = 32 mA — 0.70 0.8 x VDD VDD – 0.75 0.95 — — — 1 — — 1.20 VDD V VPP V CMOS Output Option3 VOH VOL — — — 45 0.4 350 — 55 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML CMOS with CL = 15 pF ps ns % Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50 Ω to VDD – 2.0 V. 2. Rterm = 100 Ω (differential). 3. CL = 15 pF Table 4. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)* for FOUT > 500 MHz Phase Jitter (RMS)* for FOUT of 125 to 500 MHz Symbol Test Condition 12 kHz to 20 MHz (OC-48) 50 kHz to 80 MHz (OC-192) 12 kHz to 20 MHz (OC-48) Min — — — Typ 0.27 0.30 0.50 Max — — — Units ps ps φJ φJ *Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information. Table 5. CLK± Output Period Jitter Parameter Period Jitter* for FOUT < 160 MHz Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ 1 5 Max — — Units ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Preliminary Rev. 0.4 3 S i5 34 Table 6. CLK± Output Phase Noise (Typical) Configuration fC Output Offest Frequency (f) 100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz –110 –127 –134 –136 –143 –147 n/a 81.25 MHz LVDS L (f) –100 –115 –119 –123 –135 –144 –147 –87 –102 –107 –111 –121 –135 –142 312.5 MHz LVPECL 1066 MHz LVPECL Units dBc/Hz Table 7. Absolute Maximum Ratings1 Parameter Supply Voltage Input Voltage (any input pin) Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Symbol VDD VI TS ESD TPEAK tP Rating –0.5 to +3.8 –0.5 to VDD + 0.3 –55 to +125 >2500 260 10 Units Volts Volts ºC Volts ºC seconds Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. 2. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Table 8. Environmental Compliance The Si534 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/ Test Method MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016 4 Preliminary Rev. 0.4 S i534 2. Pin Descriptions (Top View) FS[1] 7 NC OE GND 1 2 3 8 FS[0] 6 5 4 VDD FS[1] 7 NC OE GND 1 2 3 8 FS[0] 6 5 4 VDD CLK– CLK+ NC CLK LVDS/LVPECL/CML CMOS Table 9. Pin Descriptions Pin 1 2 3 4 5 6 7 8 Symbol NC OE* GND CLK+ CLK– VDD FS[1]* FS[0]* LVDS/LVPECL/CML Function No connection CMOS Function No connection Output enable Output enable 0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated) 1 = clock output enabled 1 = clock output enabled Electrical and Case Ground Oscillator Output Complementary output Power Supply Voltage Frequency Select MSB Frequency Select LSB Electrical and Case Ground Oscillator Output No connection Power Supply Voltage Frequency Select MSB Frequency Select LSB *Note: FS[1:0] and OE include a 17 kΩ pullup resistor to VDD. See Section “Ordering Information” for details on frequency value ordering. Preliminary Rev. 0.4 5 S i5 34 3. Ordering Information The Si534 XO was designed to support a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si534 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browserbased part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si534 is supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. 534 X X XXXXXX B G R R = Tape & Reel Blank = Trays 534 Quad XO Product Family Operating Temp Range (°C) G –40 to +85 °C Device Revision Letter 1st Option Code Code A B C D E F G H J K VDD 3.3 3.3 3.3 DD 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format LVPECL LVDS CMOS CML LVPECL LVDS CMOS CML CMOS CML 6-digit Frequency Designator Code Four unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for the specified combination of frequencies. Codes > 000100 refer to quad XOs programmed with the lowest frequency value selected when FS[1:0] = 00, and the highest value when FS[1:0] = 11. Six digit codes < 000100 refer to quad XOs programmed with the highest frequency value selected when FS[1:0] = 00, and the lowest value when FS[1:0] = 11. 2nd Option Code Code Temperature Stability (ppm, max, ±) A 50 B 20 Note: CMOS available to 160 MHz. Example Part Number: 534AB000108BGR is a 5 x 7 mm quad XO in a 8 pad package. Since the six digit code (000108) is > 000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 V supply and LVPECL output. Temperature stability is specified as ± 20 ppm. The part is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention 6 Preliminary Rev. 0.4 S i534 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si534. Table 10 lists the values for the dimensions shown in the illustration. Figure 2. Si534 Outline Diagram Table 10. Package Diagram Dimensions (mm) Dimension A b c d D D1 e E E1 L M S R aaa bbb ccc ddd — — — — 4.30 1.07 0.8 6.10 0.97 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP 1.17 7.00 BSC 6.2 2.54 BSC 5.00 BSC 4.40 1.27 1.0 1.815 BSC 0.7 REF — — — — 0.15 0.15 0.10 0.10 4.50 1.47 1.2 6.30 1.37 Max 1.85 1.6 Preliminary Rev. 0.4 7 S i5 34 5. 8-Pin PCB Land Pattern Figure 3 illustrates the 8-pin PCB land pattern for the Si554. Table 11 lists the values for the dimensions shown in the illustration. Figure 3. Si534 PCB Land Pattern Table 11. PCB Land Pettern Dimensions (mm) Dimension D2 D3 e E2 GD GE VD VE X1 X2 Y1 Y2 ZD ZE — — 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 1.545 TYP 2.15 REF 1.3 REF 6.78 6.30 Min 5.08 REF 5.705 REF 2.54 BSC 4.20 REF — — Max Note: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design follows IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 8 Preliminary Rev. 0.4 S i534 DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4 Updated 1. "Electrical Specifications" on page 2. Updated ordering and format of Tables 1–9. Updated LVDS and CML in Table 3, “CLK± Output Levels and Symmetry,” on page 3. Added Table 6, “CLK± Output Phase Noise (Typical),” on page 4. Preliminary Rev. 0.4 9 S i5 34 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: VCXOinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 10 Preliminary Rev. 0.4