590JB148M352DGR

S i 5 9 0 / 5 91 1 ps M AX J I T T E R C RYSTAL O SC ILLA TOR ( XO) (10 M H Z T O 5 25 MH Z ) Features  Available with any-rate output  frequencies from 10 MHz to 525 MHz  3rd generation DSPLL® with superior   jitter performance: 1 ps max jitter  Better frequency stability than SAW based oscillators   Internal fundamental mode crystal ensures high reliability Available CMOS, LVPECL, LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options Industry-standard 5 x 7 mm package and pinout Pb-free/RoHS-compliant –40 to +85 ºC operating temperature range Si5602 Applications   Ordering Information: See page 6.   SONET/SDH (OC-3/12/48) Networking  SD/HD SDI/3G SDI video Test and measurement Storage  FPGA/ASIC clock generation Description The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide a low jitter clock at high frequencies. The Si590/591 is available with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO, where a unique crystal is required for each output frequency, the Si590/591 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si590/591 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Pin Assignments: See page 5. (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si590 (LVDS/LVPECL/CML) OE 1 6 VDD Functional Block Diagram VDD CLK– CLK+ NC 2 5 NC GND 3 4 CLK Si590 (CMOS) 17 k * Any-rate 10–525 MHz DSPLL® Clock Synthesis OE 1 6 VDD OE Fixed Frequency XO NC 2 5 CLK– 17 k * GND 3 4 CLK+ Si591 (LVDS/LVPECL/CML) GND *Note: Output Enable High/Low Options Available – See Ordering Information Preliminary Rev. 0.25 7/09 Copyright © 2009 by Silicon Laboratories Si590/591 S i590/591 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Symbol VDD Test Condition 3.3 V option 2.5 V option 1.8 V option Supply Current IDD Output enabled LVPECL CML LVDS CMOS Tristate mode Output Enable (OE) 2 Min 2.97 2.25 1.71 — — — — — 0.75 x VDD — –40 Typ 3.3 2.5 1.8 110 100 90 80 60 — — — Max 3.63 2.75 1.89 125 110 100 90 75 — 0.5 85 Units V mA VIH VIL TA V ºC Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details. 2. OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pull-down resistor to GND for output enable active low. See 3. "Ordering Information" on page 6. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1,2 Initial Accuracy Symbol fO Test Condition LVPECL/LVDS/CML CMOS Measured at +25 °C at time of shipping Note 3, second option code “C” Note 4, second option code “B” Note 4, second option code “A” second option code “C” Min 10 10 — — — — — — — — Typ — — ±1.5 — — — — — — — Max 525 160 — ±30 ±50 ±100 ±20 ±25 ±50 10 Units MHz ppm ppm ppm ppm ppm ppm ppm ms fi Total Stability Temperature Stability 5 second option code “B” second option code “A” Powerup Time tOSC Notes: 1. See Section 3. "Ordering Information" on page 6 for further details. 2. Specified at time of order by part number. 3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See 3. "Ordering Information" on page 6. 4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See 3. "Ordering Information" on page 6. 5. Time from powerup or tristate mode to fO. 2 Preliminary Rev. 0.25 S i590/591 Table 3. CLK± Output Levels and Symmetry Parameter LVPECL Output Option1 Symbol VO VOD VSE 2 Test Condition mid-level swing (diff) swing (single-ended) mid-level swing (diff) Min VDD – 1.42 1.1 0.55 1.125 0.5 Typ — Max VDD – 1.25 1.9 0.95 1.275 0.9 Units V VPP VPP V VPP — — 1.20 0.7 LVDS Output Option VO VOD CML Output Option2 VO VOD mid-level swing (diff) — 0.70 0.8 x VDD VDD – 0.75 0.95 — — — 2 — — 1.20 VDD V VPP V CMOS Output Option3 VOH VOL — LVPECL/LVDS/CML CMOS with CL = 15 pF — — 45 0.4 350 — 55 ps ns % Rise/Fall time (20/80%) tR, tF Symmetry (duty cycle) SYM LVPECL: LVDS: CMOS: VDD – 1.3 V (diff) 1.25 V (diff) VDD/2 Notes: 1. 50  to VDD – 2.0 V. 2. Rterm = 100  (differential). 3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3 V, 6 mA for VDD = 2.5 V, 3 mA for VDD = 1.8 V. Table 4. CLK± Output Phase Jitter Parameter Phase Jitter (RMS)1 for 50 MHz < FOUT < 525 MHz (LVPECL/LVDS/CML) Phase Jitter (RMS)2 for 50 MHz < FOUT < 160 MHz (CMOS) Symbol Test Condition 12 kHz to 20 MHz Min — Typ 0.5 Max 1.0 Units ps J J 12 kHz to 20 MHz — 0.6 1.0 ps Notes: 1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only. 2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment. 3.3 V supply voltage option only. Table 5. CLK± Output Period Jitter Parameter Period Jitter* Symbol JPER Test Condition RMS Peak-to-Peak Min — — Typ — — Max 3 35 Units ps *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. Preliminary Rev. 0.25 3 S i590/591 Table 6. Absolute Maximum Ratings1 Parameter Maximum Operating Temperature Supply Voltage, 1.8 V Option Supply Voltage, 2.5/3.3 V Option Input Voltage (any input pin) Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Symbol TAMAX VDD VDD VI TS ESD TPEAK tP Rating 85 –0.5 to +1.9 –0.5 to +3.8 –0.5 to VDD + 0.3 –55 to +125 2500 260 20–40 Units ºC V V Volts ºC V ºC seconds Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Table 7. Environmental Compliance The Si590/591 meets the following qualification test requirements. Parameter Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/Test Method MIL-STD-883G, Method 2002.3 B MIL-STD-883G, Method 2007.3 A MIL-STD-883G, Method 203.8 MIL-STD-883G, Method 1014.7 MIL-STD-883G, Method 2015 4 Preliminary Rev. 0.25 S i590/591 2. Pin Descriptions (Top View) NC 1 6 VDD OE 1 6 VDD OE 1 6 VDD OE 2 5 CLK– NC 2 5 NC NC 2 5 CLK– GND 3 4 CLK+ GND 3 4 CLK GND 3 4 CLK+ Si590 LVDS/LVPECL/CML Si590 CMOS Si591 LVDS/LVPECL/CML Table 8. Pinout for Si590 Series Pin 1 2 3 4 5 6 Symbol OE* OE* GND CLK+ CLK– VDD LVDS/LVPECL/CML Function No connection Make no external connection to this pin Output enable Electrical and Case Ground Oscillator Output Complementary Output Power Supply Voltage CMOS Function Output enable No connection Make no external connection to this pin Electrical and Case Ground Oscillator Output No connection Make no external connection to this pin Power Supply Voltage *Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to GND for output enable active low. See 3. "Ordering Information" on page 6. Table 9. Pinout for Si591 Series Pin 1 2 3 4 5 6 Symbol OE* No connection Make no external connection to this pin GND CLK+ CLK– VDD LVDS/LVPECL/CML Function Output enable No connection Make no external connection to this pin Electrical and Case Ground Oscillator Output Complementary output Power Supply Voltage *Note: OE pin includes an internal 17 k pullup resistor to VDD for output enable active high or a 17 k pulldown resistor to GND for output enable active low. See 3. "Ordering Information" on page 6. Preliminary Rev. 0.25 5 S i590/591 3. Ordering Information The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and VDD. Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si590 and Si591 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The Si591 Series supports an alternate OE pinout (pin #1) for LVPECL, LVDS, and CML output formats. See Tables 8 and 9 for the pinout differences between the Si590 and Si591 series. 59x X X XXXMXXX D G R Tape & Reel Packaging Blank = Trays Operating Temp Range (°C) G –40 to +85°C 590 or 591 XO Product Family 1st Option Code VDD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format Output Enable Polarity LVPECL High LVDS High CMOS High CML High LVPECL High LVDS High CMOS High CML High CMOS High CML High LVPECL Low LVDS Low CMOS Low CML Low LVPECL Low LVDS Low CMOS Low CML Low CMOS Low CML Low Part Revision Letter Frequency (e.g., 148M352 is 148.352 MHz) Available frequency range is 10 to 525 MHz. The position of “M” shifts to denote higher or lower frequencies. If the frequency of interest requires greater than 6 digit resolution, a six digit code will be assigned for the specific frequency. A B C D E F G H J K M N P Q R S T U V W 2nd Option Code Code A B C Total Stablility (ppm, max, ±) 100 50 30 Temperature Stablility (ppm, max, ±) 50 25 20 Note: CMOS available to 160 MHz. Example P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. The frequency is 148.352 MHz, with a 3.3 V supply, LVDS output, and Output Enable active high polarity. Overall stability is specifed as ±50 ppm. The device is specified for –40 to +85 °C ambient temperature range operation and is shipped in tape and reel format. Figure 1. Part Number Convention 6 Preliminary Rev. 0.25 S i590/591 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si590/591. Table 10 lists the values for the dimensions shown in the illustration. Figure 2. Si590/591 Outline Diagram Table 10. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L p R aaa bbb ccc ddd eee Min 1.50 1.30 0.50 4.30 Nom 1.65 1.40 0.60 7.00 BSC 4.40 2.54 BSC. 5.00 BSC. 6.20 0.65 1.27 — 0.70 REF 0.15 0.15 0.10 0.10 0.50 Max 1.80 1.50 0.70 4.50 6.10 0.55 1.17 1.80 6.30 0.75 1.37 2.60 Preliminary Rev. 0.25 7 S i590/591 5. Si590/Si591 Mark Specification Figure 3 illustrates the mark specification for the Si590/Si591. Table 11 lists the line information. 6 5 4 SiLabs 123 1234567890 R T T T T Y WW+ 1 2 Figure 3. Mark Specification Table 11. Si53x Top Mark Description Line 1 2 3 Position 1–10 1–10 Trace Code Position 1 Position 2 Position 3–6 Position 7 Position 8–9 Position 10 Pin 1 orientation mark (dot) Product Revision (D) Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9) Calendar Work Week number (1–53), to be assigned by assembly site “+” to indicate Pb-Free and RoHS-compliant Description “SiLabs”+ Part Family Number, 59x (First 3 characters in part number) Si590, Si591: Option1 + Option2 + Freq(7) + Temp Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 8 Preliminary Rev. 0.25 S i590/591 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si590/591. Table 12 lists the values for the dimensions shown in the illustration. Figure 4. Si590/591 PCB Land Pattern . Table 12. PCB Land Pattern Dimensions (mm) Dimension D2 e E2 GD GE VD VE X Y ZD ZE — — 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 2.15 REF 6.78 6.30 Min 5.08 REF 2.54 BSC 4.15 REF — — Max Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). Preliminary Rev. 0.25 9 S i590/591 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.25  Total Stability Maximum changed to ±30 in Table 2 on page 2.  Total Stability Maximum changed to ±30 in Figure 1 on page 6. Preliminary Rev. 0.25 10 S i590/591 NOTES: Preliminary Rev. 0.25 11 S i590/591 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 12 Preliminary Rev. 0.25