C8051F364

C8051F360/1/2/3/4/5/6/7/8/9 Mixed Signal ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (‘F360/1/2/6/7/8/9 only) • Up to 200 ksps • Up to 21 external single-ended or differential inputs • VREF from internal VREF, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor - 10-Bit Current Output DAC (‘F360/1/2/6/7/8/9 only) Two Comparators Memory - 1280 bytes internal data RAM (256 + 1024) - 32 kB (‘F360/1/2/3/4/5/6/7) or 16 kB (‘F368/9) Flash; In-system programmable in 1024-byte Sectors— 1024 bytes are reserved in the 32 kB devices Digital Peripherals - up to 39 Port I/O; All 5 V tolerant with high sink current Hardware enhanced UART, SMBus™, and enhanced SPI™ serial ports Four general purpose 16-bit counter/timers 16-Bit programmable counter array (PCA) with six capture/compare modules Real time clock mode using PCA or timer and external clock source External Memory Interface (EMIF) - Brown-out detector and POR Circuitry On-Chip Debug - On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (no emulator required) Provides breakpoints, single stepping, inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Low cost, complete development kit • • • Programmable hysteresis and response time Configurable as interrupt or reset source Low current (0.4 µA) Clock Sources - Two internal oscillators: • 24.5 MHz with ±2% accuracy supports crystal-less • UART operation 80/40/20/10 kHz low frequency, low power Supply Voltage - Range: 2.7–3.6 V (50 MIPS) 3.0–3.6 V (100 MIPS) - Power saving suspend and shutdown modes High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks 100 MIPS or 50 MIPS throughput with on-chip PLL Expanded interrupt handler 2-cycle 16 x 16 MAC engine Flexible PLL technology External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) Can switch between clock sources on-the-fly; useful in power saving modes Packages - 48-pin TQFP (C8051F360/3) - 32-pin LQFP (C8051F361/4/6/8) - 28-pin QFN (C8051F362/5/7/9) Temperature Range: –40 to +85 °C CROSSBAR External Memory Interface ANALOG PERIPHERALS VOLTAGE COMPARATORS DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 Port 0 Port 1 Port 2 Port 3 Port 3 Port 4 + - + - A M U X 10-bit 200 ksps ADC TEMP SENSOR 10-bit Current DAC ‘F360/1/2/6/7/8/9 only 48-pin only HIGH-SPEED CONTROLLER CORE W DT 16 x 16 MAC 8051 CPU (100 or 50 MIPS) 1024 B SRAM POR FLEXIBLE INTERRUPTS D EBUG CIRCUITRY Internal Oscillator/ LFO/PLL 32/16 kB ISP FLASH Rev. 1.0 7/07 Copyright © 2007 by Silicon Laboratories C8051F36x This information applies to a product under development. Its characteristics and specifications are subject to change without notice. C8051F360/1/2/3/4/5/6/7/8/9 2 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table of Contents 1. System Overview.................................................................................................... 18 1.1. CIP-51™ Microcontroller Core.......................................................................... 22 1.1.1. Fully 8051 Compatible.............................................................................. 22 1.1.2. Improved Throughput ............................................................................... 22 1.1.3. Additional Features .................................................................................. 23 1.2. On-Chip Memory............................................................................................... 24 1.3. On-Chip Debug Circuitry................................................................................... 24 1.4. Programmable Digital I/O and Crossbar ........................................................... 25 1.5. Serial Ports ....................................................................................................... 26 1.6. Programmable Counter Array ........................................................................... 26 1.7. 10-Bit Analog to Digital Converter..................................................................... 27 1.8. Comparators ..................................................................................................... 28 1.9. 10-bit Current Output DAC................................................................................ 30 2. Absolute Maximum Ratings .................................................................................. 32 3. Global Electrical Characteristics .......................................................................... 33 4. Pinout and Package Definitions............................................................................ 36 5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)........................................................... 47 5.1. Analog Multiplexer ............................................................................................ 48 5.2. Temperature Sensor ......................................................................................... 49 5.3. Modes of Operation .......................................................................................... 51 5.3.1. Starting a Conversion............................................................................... 51 5.3.2. Tracking Modes........................................................................................ 52 5.3.3. Settling Time Requirements ..................................................................... 53 5.4. Programmable Window Detector ...................................................................... 58 5.4.1. Window Detector In Single-Ended Mode ................................................. 60 5.4.2. Window Detector In Differential Mode...................................................... 61 6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) .................................... 63 6.1. IDA0 Output Scheduling ................................................................................... 63 6.1.1. Update Output On-Demand ..................................................................... 63 6.1.2. Update Output Based on Timer Overflow ................................................ 64 6.1.3. Update Output Based on CNVSTR Edge................................................. 64 6.2. IDAC Output Mapping....................................................................................... 64 7. Voltage Reference (C8051F360/1/2/6/7/8/9) .......................................................... 67 8. Comparators ........................................................................................................... 70 9. CIP-51 Microcontroller .......................................................................................... 80 9.1. Performance ..................................................................................................... 80 9.2. Programming and Debugging Support ............................................................. 81 9.3. Instruction Set ................................................................................................... 82 9.3.1. Instruction and CPU Timing ..................................................................... 82 9.3.2. MOVX Instruction and Program Memory ................................................. 82 9.4. Memory Organization........................................................................................ 86 9.4.1. Program Memory...................................................................................... 86 9.4.2. Data Memory............................................................................................ 87 Rev. 1.0 3 C8051F360/1/2/3/4/5/6/7/8/9 9.4.3. General Purpose Registers ...................................................................... 87 9.4.4. Bit Addressable Locations........................................................................ 87 9.4.5. Stack ....................................................................................................... 87 9.4.6. Special Function Registers....................................................................... 88 9.4.7. Register Descriptions ............................................................................. 102 9.5. Power Management Modes ............................................................................ 104 9.5.1. Idle Mode................................................................................................ 105 9.5.2. Stop Mode .............................................................................................. 105 9.5.3. Suspend Mode ....................................................................................... 105 10. Interrupt Handler .................................................................................................. 107 10.1.MCU Interrupt Sources and Vectors............................................................... 107 10.2.Interrupt Priorities ........................................................................................... 108 10.3.Interrupt Latency............................................................................................. 108 10.4.Interrupt Register Descriptions ....................................................................... 109 10.5.External Interrupts .......................................................................................... 115 11. Multiply And Accumulate (MAC0) ....................................................................... 117 11.1.Special Function Registers............................................................................. 117 11.2.Integer and Fractional Math............................................................................ 118 11.3.Operating in Multiply and Accumulate Mode .................................................. 119 11.4.Operating in Multiply Only Mode .................................................................... 119 11.5.Accumulator Shift Operations......................................................................... 119 11.6.Rounding and Saturation................................................................................ 120 11.7.Usage Examples ............................................................................................ 120 11.7.1.Multiply and Accumulate Example ......................................................... 120 11.7.2.Multiply Only Example............................................................................ 121 11.7.3.MAC0 Accumulator Shift Example ......................................................... 121 12. Reset Sources....................................................................................................... 128 12.1.Power-On Reset ............................................................................................. 129 12.2.Power-Fail Reset/VDD Monitor ...................................................................... 130 12.3.External Reset ................................................................................................ 131 12.4.Missing Clock Detector Reset ........................................................................ 131 12.5.Comparator0 Reset ........................................................................................ 131 12.6.PCA Watchdog Timer Reset .......................................................................... 132 12.7.Flash Error Reset ........................................................................................... 132 12.8.Software Reset ............................................................................................... 132 13. Flash Memory ....................................................................................................... 135 13.1.Programming the Flash Memory .................................................................... 135 13.1.1.Flash Lock and Key Functions ............................................................... 135 13.1.2.Erasing Flash Pages From Software ..................................................... 136 13.1.3.Writing Flash Memory From Software.................................................... 136 13.1.4.Non-volatile Data Storage ...................................................................... 137 13.2.Security Options ............................................................................................. 138 13.2.1.Summary of Flash Security Options....................................................... 139 13.3.Flash Write and Erase Guidelines .................................................................. 140 13.3.1.VDD Maintenance and the VDD Monitor ............................................... 140 4 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 13.3.2.16.4.2 PSWE Maintenance .................................................................... 141 13.3.3.System Clock ......................................................................................... 141 13.4.Flash Read Timing ......................................................................................... 143 14. Branch Target Cache ........................................................................................... 145 14.1.Cache and Prefetch Operation ....................................................................... 145 14.2.Cache and Prefetch Optimization................................................................... 146 15. External Data Memory Interface and On-Chip XRAM........................................ 153 15.1.Accessing XRAM............................................................................................ 153 15.1.1.16-Bit MOVX Example ........................................................................... 153 15.1.2.8-Bit MOVX Example ............................................................................. 153 15.2.Configuring the External Memory Interface .................................................... 154 15.3.Port Configuration........................................................................................... 154 15.4.Multiplexed and Non-multiplexed Selection.................................................... 157 15.4.1.Multiplexed Configuration....................................................................... 157 15.4.2.Non-multiplexed Configuration............................................................... 158 15.5.Memory Mode Selection................................................................................. 159 15.5.1.Internal XRAM Only ............................................................................... 159 15.5.2.Split Mode without Bank Select.............................................................. 159 15.5.3.Split Mode with Bank Select................................................................... 160 15.5.4.External Only.......................................................................................... 160 15.6.Timing .......................................................................................................... 160 15.6.1.Non-multiplexed Mode ........................................................................... 162 15.6.2.Multiplexed Mode ................................................................................... 165 16. Oscillators ............................................................................................................. 169 16.1.Programmable Internal High-Frequency (H-F) Oscillator ............................... 169 16.1.1. Internal Oscillator Suspend Mode ......................................................... 170 16.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 171 16.2.1.Calibrating the Internal L-F Oscillator..................................................... 172 16.3.External Oscillator Drive Circuit...................................................................... 173 16.4.System Clock Selection.................................................................................. 173 16.5.External Crystal Example ............................................................................... 176 16.6.External RC Example ..................................................................................... 177 16.7.External Capacitor Example ........................................................................... 177 16.8.Phase-Locked Loop (PLL).............................................................................. 178 16.8.1.PLL Input Clock and Pre-divider ............................................................ 178 16.8.2.PLL Multiplication and Output Clock ...................................................... 178 16.8.3.Powering on and Initializing the PLL ...................................................... 179 17. Port Input/Output.................................................................................................. 183 17.1.Priority Crossbar Decoder .............................................................................. 185 17.2.Port I/O Initialization ....................................................................................... 187 17.3.General Purpose Port I/O ............................................................................... 190 18. SMBus ................................................................................................................... 202 18.1.Supporting Documents ................................................................................... 203 18.2.SMBus Configuration...................................................................................... 203 Rev. 1.0 5 C8051F360/1/2/3/4/5/6/7/8/9 18.3.SMBus Operation ........................................................................................... 203 18.3.1.Arbitration............................................................................................... 204 18.3.2.Clock Low Extension.............................................................................. 204 18.3.3.SCL Low Timeout................................................................................... 204 18.3.4.SCL High (SMBus Free) Timeout .......................................................... 205 18.4.Using the SMBus............................................................................................ 205 18.4.1.SMBus Configuration Register............................................................... 206 18.4.2.SMB0CN Control Register ..................................................................... 209 18.4.3.Data Register ......................................................................................... 212 18.5.SMBus Transfer Modes.................................................................................. 213 18.5.1.Master Transmitter Mode ....................................................................... 213 18.5.2.Master Receiver Mode ........................................................................... 214 18.5.3.Slave Receiver Mode ............................................................................. 215 18.5.4.Slave Transmitter Mode ......................................................................... 216 18.6.SMBus Status Decoding................................................................................. 217 19. UART0.................................................................................................................... 220 19.1.Enhanced Baud Rate Generation................................................................... 221 19.2.Operational Modes ......................................................................................... 222 19.2.1.8-Bit UART ............................................................................................. 222 19.2.2.9-Bit UART ............................................................................................. 223 19.3.Multiprocessor Communications .................................................................... 224 20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 234 20.1.Signal Descriptions......................................................................................... 235 20.1.1.Master Out, Slave In (MOSI).................................................................. 235 20.1.2.Master In, Slave Out (MISO).................................................................. 235 20.1.3.Serial Clock (SCK) ................................................................................. 235 20.1.4.Slave Select (NSS) ................................................................................ 235 20.2.SPI0 Master Mode Operation ......................................................................... 236 20.3.SPI0 Slave Mode Operation ........................................................................... 238 20.4.SPI0 Interrupt Sources ................................................................................... 238 20.5.Serial Clock Timing......................................................................................... 239 20.6.SPI Special Function Registers ...................................................................... 241 21. Timers.................................................................................................................... 247 21.1.Timer 0 and Timer 1 ....................................................................................... 248 21.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 248 21.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 249 21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 249 21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 251 21.2.Timer 2 .......................................................................................................... 256 21.2.1.16-bit Timer with Auto-Reload................................................................ 256 21.2.2.8-bit Timers with Auto-Reload................................................................ 257 21.3.Timer 3 .......................................................................................................... 260 21.3.1.16-bit Timer with Auto-Reload................................................................ 260 21.3.2.8-bit Timers with Auto-Reload................................................................ 261 6 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 22. Programmable Counter Array ............................................................................. 264 22.1.PCA Counter/Timer ........................................................................................ 265 22.2.Capture/Compare Modules ............................................................................ 266 22.2.1.Edge-triggered Capture Mode................................................................ 267 22.2.2.Software Timer (Compare) Mode........................................................... 268 22.2.3.High Speed Output Mode....................................................................... 269 22.2.4.Frequency Output Mode ........................................................................ 270 22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 271 22.2.6.16-Bit Pulse Width Modulator Mode....................................................... 272 22.3.Watchdog Timer Mode ................................................................................... 272 22.3.1.Watchdog Timer Operation .................................................................... 273 22.3.2.Watchdog Timer Usage ......................................................................... 274 22.4.Register Descriptions for PCA0...................................................................... 276 23. Revision Specific Behavior ................................................................................. 281 23.1.Revision Identification..................................................................................... 281 23.2.C2D Port Pin Requirements ........................................................................... 283 24. C2 Interface ........................................................................................................... 284 24.1.C2 Interface Registers.................................................................................... 284 24.2.C2 Pin Sharing ............................................................................................... 286 Document Change List ............................................................................................. 287 Contact Information .................................................................................................. 288 Rev. 1.0 7 C8051F360/1/2/3/4/5/6/7/8/9 List of Figures 1. System Overview Figure 1.1. C8051F360/3 Block Diagram ................................................................. 20 Figure 1.2. C8051F361/4/6/8 Block Diagram ........................................................... 21 Figure 1.3. C8051F362/5/7/9 Block Diagram ........................................................... 21 Figure 1.4. Comparison of Peak MCU Execution Speeds ....................................... 22 Figure 1.5. On-Chip Clock and Reset ......................................................................23 Figure 1.6. On-Board Memory Map ......................................................................... 24 Figure 1.7. Development/In-System Debug Diagram .............................................. 25 Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3) ........................................... 26 Figure 1.9. PCA Block Diagram ............................................................................... 27 Figure 1.10. PCA Block Diagram .............................................................................27 Figure 1.11. 10-Bit ADC Block Diagram ................................................................... 28 Figure 1.12. Comparator0 Block Diagram ................................................................ 29 Figure 1.13. Comparator1 Block Diagram ................................................................ 30 Figure 1.14. IDA0 Functional Block Diagram ........................................................... 31 2. Absolute Maximum Ratings 3. Global Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. TQFP-48 Pinout Diagram (Top View) .................................................... 39 Figure 4.2. TQFP-48 Package Diagram ................................................................... 40 Figure 4.3. LQFP-32 Pinout Diagram (Top View) .................................................... 41 Figure 4.4. LQFP-32 Package Diagram ................................................................... 42 Figure 4.5. QFN-28 Pinout Diagram (Top View) ...................................................... 43 Figure 4.6. QFN-28 Package Drawing ..................................................................... 44 Figure 4.7. Typical QFN-28 Landing Diagram ......................................................... 45 Figure 4.8. QFN-28 Solder Paste Recommendation ............................................... 46 5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) Figure 5.1. ADC0 Functional Block Diagram ........................................................... 47 Figure 5.2. Typical Temperature Sensor Transfer Function .................................... 49 Figure 5.3. Temperature Sensor Error with 1-Point Calibration ............................... 50 Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 52 Figure 5.5. ADC0 Equivalent Input Circuits .............................................................. 53 Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ... 60 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 60 Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 61 Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data .......... 61 6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) Figure 6.1. IDA0 Functional Block Diagram ............................................................. 63 Figure 6.2. IDA0 Data Word Mapping ......................................................................64 7. Voltage Reference (C8051F360/1/2/6/7/8/9) Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 67 8. Comparators Figure 8.1. Comparator0 Functional Block Diagram ................................................ 70 8 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Figure 8.2. Comparator1 Functional Block Diagram ............................................... 71 Figure 8.3. Comparator Hysteresis Plot .................................................................. 72 9. CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram .......................................................................... 81 Figure 9.2. Memory Map ......................................................................................... 86 Figure 9.3. SFR Page Stack .................................................................................... 89 Figure 9.4. SFR Page Stack While Using SFR Page 0x0F To Access OSCICN .... 90 Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs .... 91 Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR . 91 Figure 9.7. SFR Page Stack Upon Return From PCA Interrupt .............................. 92 Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt .............. 93 10. Interrupt Handler 11. Multiply And Accumulate (MAC0) Figure 11.1. MAC0 Block Diagram ........................................................................ 117 Figure 11.2. Integer Mode Data Representation ................................................... 118 Figure 11.3. Fractional Mode Data Representation ............................................... 118 Figure 11.4. MAC0 Pipeline ................................................................................... 119 12. Reset Sources Figure 12.1. Reset Sources ................................................................................... 128 Figure 12.2. Power-On and VDD Monitor Reset Timing ....................................... 129 13. Flash Memory Figure 13.1. Flash Program Memory Map ............................................................. 138 14. Branch Target Cache Figure 14.1. Branch Target Cache Data Flow ....................................................... 145 Figure 14.2. Branch Target Cache Organization ................................................... 146 Figure 14.3. Cache Lock Operation ....................................................................... 148 15. External Data Memory Interface and On-Chip XRAM Figure 15.1. Multiplexed Configuration Example ................................................... 157 Figure 15.2. Non-multiplexed Configuration Example ........................................... 158 Figure 15.3. EMIF Operating Modes ..................................................................... 159 Figure 15.4. Non-multiplexed 16-bit MOVX Timing ............................................... 162 Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 163 Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 164 Figure 15.7. Multiplexed 16-bit MOVX Timing ....................................................... 165 Figure 15.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 166 Figure 15.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 167 16. Oscillators Figure 16.1. Oscillator Diagram ............................................................................. 169 Figure 16.2. 32.768 kHz External Crystal Example ............................................... 176 Figure 16.3. PLL Block Diagram ............................................................................ 178 17. Port Input/Output Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 183 Figure 17.2. Port I/O Cell Block Diagram .............................................................. 184 Figure 17.3. Crossbar Priority Decoder with No Pins Skipped .............................. 185 Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped ............................ 186 Rev. 1.0 9 C8051F360/1/2/3/4/5/6/7/8/9 18. SMBus Figure 18.1. SMBus Block Diagram ...................................................................... 202 Figure 18.2. Typical SMBus Configuration ............................................................ 203 Figure 18.3. SMBus Transaction ........................................................................... 204 Figure 18.4. Typical SMBus SCL Generation ........................................................ 207 Figure 18.5. Typical Master Transmitter Sequence ............................................... 213 Figure 18.6. Typical Master Receiver Sequence ................................................... 214 Figure 18.7. Typical Slave Receiver Sequence ..................................................... 215 Figure 18.8. Typical Slave Transmitter Sequence ................................................. 216 19. UART0 Figure 19.1. UART0 Block Diagram ...................................................................... 220 Figure 19.2. UART0 Baud Rate Logic ................................................................... 221 Figure 19.3. UART Interconnect Diagram ............................................................. 222 Figure 19.4. 8-Bit UART Timing Diagram .............................................................. 222 Figure 19.5. 9-Bit UART Timing Diagram .............................................................. 223 Figure 19.6. UART Multi-Processor Mode Interconnect Diagram ......................... 224 20. Enhanced Serial Peripheral Interface (SPI0) Figure 20.1. SPI Block Diagram ............................................................................ 234 Figure 20.2. Multiple-Master Mode Connection Diagram ...................................... 237 Figure 20.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ......................................................................... 237 Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ......................................................................... 237 Figure 20.5. Master Mode Data/Clock Timing ....................................................... 239 Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 240 Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 240 Figure 20.8. SPI Master Timing (CKPHA = 0) ....................................................... 244 Figure 20.9. SPI Master Timing (CKPHA = 1) ....................................................... 244 Figure 20.10. SPI Slave Timing (CKPHA = 0) ....................................................... 245 Figure 20.11. SPI Slave Timing (CKPHA = 1) ....................................................... 245 21. Timers Figure 21.1. T0 Mode 0 Block Diagram ................................................................. 249 Figure 21.2. T0 Mode 2 Block Diagram ................................................................. 250 Figure 21.3. T0 Mode 3 Block Diagram ................................................................. 251 Figure 21.4. Timer 2 16-Bit Mode Block Diagram ................................................. 256 Figure 21.5. Timer 2 8-Bit Mode Block Diagram ................................................... 257 Figure 21.6. Timer 3 16-Bit Mode Block Diagram ................................................. 260 Figure 21.7. Timer 3 8-Bit Mode Block Diagram ................................................... 261 22. Programmable Counter Array Figure 22.1. PCA Block Diagram ........................................................................... 264 Figure 22.2. PCA Counter/Timer Block Diagram ................................................... 265 Figure 22.3. PCA Interrupt Block Diagram ............................................................ 266 Figure 22.4. PCA Capture Mode Diagram ............................................................. 267 Figure 22.5. PCA Software Timer Mode Diagram ................................................. 268 Figure 22.6. PCA High Speed Output Mode Diagram ........................................... 269 10 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Figure 22.7. PCA Frequency Output Mode ........................................................... 270 Figure 22.8. PCA 8-Bit PWM Mode Diagram ........................................................ 271 Figure 22.9. PCA 16-Bit PWM Mode ..................................................................... 272 Figure 22.10. PCA Module 5 with Watchdog Timer Enabled ................................ 273 23. Revision Specific Behavior Figure 23.1. Device Package - TQFP 48 ............................................................... 281 Figure 23.2. Device Package - LQFP 32 ............................................................... 282 Figure 23.3. Device Package - QFN 28 ................................................................. 282 24. C2 Interface Figure 24.1. Typical C2 Pin Sharing ...................................................................... 286 Rev. 1.0 11 C8051F360/1/2/3/4/5/6/7/8/9 List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 19 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 3.2. Index to Electrical Characteristics Tables ............................................... 35 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F36x .......................................................... 36 Table 4.2. TQFP-48 Package Dimensions .............................................................. 40 Table 4.3. LQFP-32 Package Dimensions .............................................................. 42 Table 4.4. QFN-28 Package Dimensions ................................................................ 44 5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) Table 5.1. ADC0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) Table 6.1. IDAC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7. Voltage Reference (C8051F360/1/2/6/7/8/9) Table 7.1. Voltage Reference Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 69 8. Comparators Table 8.1. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9. CIP-51 Microcontroller Table 9.1. CIP-51 Instruction Set Summary ............................................................ 82 Table 9.2. Special Function Register (SFR) Memory Map ...................................... 96 Table 9.3. Special Function Registers ..................................................................... 97 10. Interrupt Handler Table 10.1. Interrupt Summary .............................................................................. 108 11. Multiply And Accumulate (MAC0) Table 11.1. MAC0 Rounding (MAC0SAT = 0) ....................................................... 120 12. Reset Sources Table 12.1. Reset Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13. Flash Memory Table 13.1. Flash Security Summary .................................................................... 139 Table 13.2. Flash Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14. Branch Target Cache 15. External Data Memory Interface and On-Chip XRAM Table 15.1. EMIF Pinout (C8051F360/3) ............................................................... 155 Table 15.2. AC Parameters for External Memory Interface ................................... 168 16. Oscillators Table 16.1. Internal High Frequency Oscillator Electrical Characteristics . . . . . . . 171 Table 16.2. Internal Low Frequency Oscillator Electrical Characteristics . . . . . . . 172 Table 16.3. PLL Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 16.4. PLL Lock Timing Characteristics ........................................................ 182 12 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 17. Port Input/Output Table 17.1. Port I/O DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 201 18. SMBus Table 18.1. SMBus Clock Source Selection .......................................................... 206 Table 18.2. Minimum SDA Setup and Hold Times ................................................ 207 Table 18.3. Sources for Hardware Changes to SMB0CN ..................................... 211 Table 18.4. SMBus Status Decoding ..................................................................... 217 19. UART0 Table 19.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator .............................................. 227 Table 19.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator ............................................... 228 Table 19.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 229 Table 19.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................... 230 Table 19.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ......................................... 231 Table 19.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator ........................................... 232 Table 19.7. Timer Settings for Standard Baud Rates Using the PLL .................... 233 Table 19.8. Timer Settings for Standard Baud Rates Using the PLL .................... 233 20. Enhanced Serial Peripheral Interface (SPI0) Table 20.1. SPI Slave Timing Parameters ............................................................ 246 21. Timers 22. Programmable Counter Array Table 22.1. PCA Timebase Input Options ............................................................. 265 Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 267 Table 22.3. Watchdog Timer Timeout Intervals ..................................................... 275 23. Revision Specific Behavior 24. C2 Interface Rev. 1.0 13 C8051F360/1/2/3/4/5/6/7/8/9 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 54 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 55 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 58 SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 58 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 59 SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . . 59 SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SFR Definition 6.2. IDA0H: IDA0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SFR Definition 8.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 74 SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 75 SFR Definition 8.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SFR Definition 8.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 77 SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 78 SFR Definition 9.1. SFR0CN: SFR Page Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 9.2. SFRPAGE: SFR Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SFR Definition 9.3. SFRNEXT: SFR Next Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 9.4. SFRLAST: SFR Last Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 SFR Definition 9.5. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 9.6. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 9.7. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 SFR Definition 9.8. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SFR Definition 9.9. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SFR Definition 9.10. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SFR Definition 9.11. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SFR Definition 10.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SFR Definition 10.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 112 SFR Definition 10.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 113 SFR Definition 10.5. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . 114 SFR Definition 10.6. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . 114 SFR Definition 10.7. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 116 SFR Definition 11.1. MAC0CF: MAC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 122 SFR Definition 11.2. MAC0STA: MAC0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SFR Definition 11.3. MAC0AH: MAC0 A High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SFR Definition 11.4. MAC0AL: MAC0 A Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 11.5. MAC0BH: MAC0 B High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.6. MAC0BL: MAC0 B Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR Definition 11.7. MAC0ACC3: MAC0 Accumulator Byte 3 . . . . . . . . . . . . . . . . . . 125 SFR Definition 11.8. MAC0ACC2: MAC0 Accumulator Byte 2 . . . . . . . . . . . . . . . . . 125 SFR Definition 11.9. MAC0ACC1: MAC0 Accumulator Byte 1 . . . . . . . . . . . . . . . . . 125 SFR Definition 11.10. MAC0ACC0: MAC0 Accumulator Byte 0 . . . . . . . . . . . . . . . . . 126 SFR Definition 11.11. MAC0OVR: MAC0 Accumulator Overflow . . . . . . . . . . . . . . . . 126 SFR Definition 11.12. MAC0RNDH: MAC0 Rounding Register High Byte . . . . . . . . . 126 SFR Definition 11.13. MAC0RNDL: MAC0 Rounding Register Low Byte . . . . . . . . . 127 SFR Definition 12.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . 131 SFR Definition 12.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 SFR Definition 13.1. PSCTL: Program Store Read/Write Control . . . . . . . . . . . . . . . 142 SFR Definition 13.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 13.3. FLSCL: Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 14.1. CCH0CN: Cache Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 SFR Definition 14.2. CCH0TN: Cache Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SFR Definition 14.3. CCH0LC: Cache Lock Control . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 14.4. CCH0MA: Cache Miss Accumulator . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 14.5. FLSTAT: Flash Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 15.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 155 SFR Definition 15.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 156 SFR Definition 15.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 161 SFR Definition 16.1. OSCICL: Internal Oscillator Calibration. . . . . . . . . . . . . . . . . . . 170 SFR Definition 16.2. OSCICN: Internal Oscillator Control . . . . . . . . . . . . . . . . . . . . . 171 SFR Definition 16.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 172 SFR Definition 16.4. CLKSEL: System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . 174 SFR Definition 16.5. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 175 SFR Definition 16.6. PLL0CN: PLL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 SFR Definition 16.7. PLL0DIV: PLL Pre-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 SFR Definition 16.8. PLL0MUL: PLL Clock Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SFR Definition 16.9. PLL0FLT: PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 188 SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 189 SFR Definition 17.3. P0: Port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SFR Definition 17.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SFR Definition 17.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 191 SFR Definition 17.6. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SFR Definition 17.7. P0MAT: Port0 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SFR Definition 17.8. P0MASK: Port0 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 SFR Definition 17.9. P1: Port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 17.10. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 SFR Definition 17.11. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.12. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.13. P1MAT: Port1 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 SFR Definition 17.14. P1MASK: Port1 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 SFR Definition 17.15. P2: Port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Rev. 1.0 15 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.17. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 196 SFR Definition 17.18. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.19. P2MAT: Port2 Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.20. P2MASK: Port2 Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 SFR Definition 17.21. P3: Port3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 17.22. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 SFR Definition 17.23. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 199 SFR Definition 17.24. P3SKIP: Port3 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 SFR Definition 17.25. P4: Port4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 SFR Definition 17.26. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 200 SFR Definition 18.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 208 SFR Definition 18.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 SFR Definition 18.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SFR Definition 19.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SFR Definition 19.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 226 SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SFR Definition 21.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 SFR Definition 21.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 SFR Definition 21.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 SFR Definition 21.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SFR Definition 21.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SFR Definition 21.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SFR Definition 21.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 SFR Definition 21.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 259 SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 259 SFR Definition 21.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 SFR Definition 21.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 SFR Definition 21.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 263 SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 263 SFR Definition 21.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 SFR Definition 21.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 SFR Definition 22.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 SFR Definition 22.2. PCA0MD: PCA0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 SFR Definition 22.3. PCA0CPMn: PCA0 Capture/Compare Mode . . . . . . . . . . . . . . 278 SFR Definition 22.4. PCA0L: PCA0 Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . 279 SFR Definition 22.5. PCA0H: PCA0 Counter/Timer High Byte . . . . . . . . . . . . . . . . . . 279 SFR Definition 22.6. PCA0CPLn: PCA0 Capture Module Low Byte . . . . . . . . . . . . . . 279 SFR Definition 22.7. PCA0CPHn: PCA0 Capture Module High Byte . . . . . . . . . . . . 280 C2 Register Definition 24.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 C2 Register Definition 24.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 284 C2 Register Definition 24.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 285 C2 Register Definition 24.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 285 C2 Register Definition 24.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 285 Rev. 1.0 17 C8051F360/1/2/3/4/5/6/7/8/9 1. System Overview C8051F36x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • • • • • • • • • • • • • • • High-speed pipelined 8051-compatible microcontroller core (up to 100 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) True 10-bit 200 ksps 16-channel single-ended/differential ADC with analog multiplexer 10-bit Current Output DAC 2-cycle 16 by 16 Multiply and Accumulate Engine Precision programmable 25 MHz internal oscillator Up to 32 kB of on-chip Flash memory—1024 bytes are reserved 1024 bytes of on-chip RAM External Data Memory Interface with 64 kB address space SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer function On-chip Power-On Reset, VDD Monitor, and Temperature Sensor Two on-chip Voltage Comparators up to 39 Port I/O (5 V tolerant) With on-chip Power-On Reset, VDD Monitor, Watchdog Timer, and clock oscillator, the C8051F36x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 3.0 to 3.6 V (100 MIPS) operation or 2.7 to 3.6 V (50 MIPS) operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F36x devices are available in 48-pin TQFP packages, and C8051F36x devices are available in 32-pin LQFP and 28-pin QFN packages (also referred to as MLP or MLF packages). All package types are lead-free (RoHS compliant). See Table 1.1 for ordering part numbers. Block diagrams are included in Figure 1.1, Figure 1.2, and Figure 1.3. 18 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 1.1. Product Selection Guide Calibrated Internal 24.5 MHz Oscillator Programmable Counter Array Lead-free (RoHS Compliant) Internal Voltage Reference 10-bit Current Output DAC External Memory Interface Internal 80 kHz Oscillator Ordering Part Number 2-cycle 16 by 16 MAC Analog Comparators Temperature Sensor 10-bit 200ksps ADC Flash Memory (kB) Digital Port I/Os Timers (16-bit) Enhanced SPI MIPS (Peak) RAM (bytes) SMBus/I2C C8051F360-GQ C8051F361-GQ1 C8051F362-GM2 C8051F363-GQ C8051F364-GQ1 C8051F365-GM2 C8051F366-GQ1 C8051F367-GM2 C8051F368-GQ1 C8051F369-GM2 100 100 100 100 100 100 50 50 50 50 32 1024 32 1024 32 1024 32 1024 32 1024 32 1024 32 1024 32 1024 16 1024 16 1024 — — — — — — — — 4 4 4 4 4 4 4 4 4 4 39 29 25 39 — 29 — 25 — 29 25 29 25 — — — — — — — — — 2 2 2 2 2 2 2 2 2 2 TQFP-48 LQFP-32 QFN-28 TQFP-48 LQFP-32 QFN-28 LQFP-32 QFN-28 LQFP-32 QFN-28 Notes: 1. Pin compatible with the C8051F310-GQ. 2. Pin compatible with the C8051F311-GM. Rev. 1.0 Package 19 UART C8051F360/1/2/3/4/5/6/7/8/9 C2D C2CK/RST Debug / Programming Hardware Reset Port I/O Configuration P0.0 P0.1/TX P0.2/RX P0.3/VREF P0.4/IDA0 P0.5/XTAL1 P0.6/XTAL2 P0.7/CNVSTR P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6/C2D Digital Peripherals CIP-51 8051 Controller Core 32/16 kB ISP FLASH Program Memory 256 Byte RAM UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Crossbar Control Port 0 Drivers Power-On Reset Supply Monitor VDD Priority Crossbar Decoder Port 1 Drivers Power Net 1 kB XRAM GND Port 2 Drivers 2-cycle 16 by 16 Multiply and Accumulate System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator Clock Multiplier SFR Bus External Memory Interface Control Address Data P0 / P4 P2 / P3 / P4 P1 Port 3 Drivers Port 4 Drivers Low Frequency Oscillator VREF VDD A nalog Peripherals 10-bit IDAC VREF P4.4 CP0 CP1 + + - 2 Comparators AIN0–AIN16 VDD Temp Sensor 10-bit 200 ksps ADC C8051F360 only A M U X Figure 1.1. C8051F360/3 Block Diagram 20 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 C2D C2CK/RST Debug / Programming Hardware Reset Port I/O Configuration P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D P3.1 P3.2 P3.3 P3.4 Digital Peripherals CIP-51 8051 Controller Core 32/16 kB ISP FLASH Program Memory 256 Byte RAM UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Port 0 Drivers Power-On Reset Supply Monitor VDD Priority Crossbar Decoder Port 1 Drivers 1 kB XRAM GND 2-cycle 16 by 16 Multiply and Accumulate SFR Bus Crossbar Control Port 2 Drivers Port 3 Drivers System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator Clock Multiplier VREF VDD A nalog Peripherals 10-bit IDAC VREF P0.1 CP0 CP1 + + - 2 Comparators AIN0–AIN20 VDD Temp Sensor Low Frequency Oscillator 10-bit 200 ksps ADC C8051F361/6/8 only A M U X Figure 1.2. C8051F361/4/6/8 Block Diagram C2D C2CK/RST Debug / Programming Hardware Reset Port I/O Configuration P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D Digital Peripherals CIP-51 8051 Controller Core 32/16 kB ISP FLASH Program Memory 256 Byte RAM UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Port 0 Drivers Power-On Reset Supply Monitor VDD Priority Crossbar Decoder Port 1 Drivers 1 kB XRAM GND 2-cycle 16 by 16 Multiply and Accumulate SFR Bus Crossbar Control Port 2 Drivers Port 3 Drivers System Clock Setup XTAL1 XTAL2 External Oscillator Internal Oscillator VREF Analog Peripherals 10-bit IDAC VREF P0.1 CP0 CP1 + + - Clock Multiplier VDD 2 Comparators AIN0–AIN20 VDD Temp Sensor Low Frequency Oscillator 10-bit 200 ksps ADC C8051F362/7/9 only A M U X Figure 1.3. C8051F362/5/7/9 Block Diagram Rev. 1.0 21 C8051F360/1/2/3/4/5/6/7/8/9 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F36x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 1024 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and up to 39 I/O pins. 1.1.2. Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than four system clock cycles. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 With the CIP-51's maximum system clock at 100 MHz, it has a peak throughput of 100 MIPS. Figure 1.4 shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum system clocks. 25 20 MIPS 15 10 5 Silicon Labs Microchip Philips ADuC812 CIP-51 PIC17C75x 80C51 8051 (25 MHz clk) (33 MHz clk) (33 MHz clk) (16 MHz clk) Figure 1.4. Comparison of Peak MCU Execution Speeds 22 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 1.1.3. Additional Features The C8051F36x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD Monitor (forces reset when power supply voltage drops below VRST as given in Table 12.1 on page 134), a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator factory calibrated to 24.5 MHz ±2%. This internal oscillator period may be user programmed in ~0.5% increments. An additional low-frequency oscillator is also available which facilitates low-power operation. An external oscillator drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. If desired, the system clock source may be switched on-the-fly between both internal and external oscillator circuits. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast (up to 25 MHz) internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system clock speeds for increased throughput. VDD Power On Reset Supply Monitor Px.x Px.x Comparator 0 + C0RSEF + - Enable '0' (wired-OR) /RST Missing Clock Detector (oneshot) EN Reset Funnel PCA WDT (Software Reset) Low Frequency Oscillator EN SWRSF Errant FLASH Operation MCD Enable Internal Oscillator System Clock PLL Circuitry CIP-51 Microcontroller Core Clock Select Extended Interrupt Handler WDT Enable S ystem Reset XTAL1 XTAL2 External Oscillator Drive Figure 1.5. On-Chip Clock and Reset Rev. 1.0 23 C8051F360/1/2/3/4/5/6/7/8/9 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 32/16 kB of Flash. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. See Figure 1.6 for the MCU system memory map. PROGRAM MEMORY C8051F360/1/2/3/4/5/6/7 DATA MEMORY INTERNAL DATA ADDRESS SPACE 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Special Function Register's (Direct Addressing Only) RESERVED 0x7C00 0x7BFF FLASH (In-System Programmable in 1024 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable General Purpose Registers L ower 128 RAM (Direct and Indirect Addressing) 0x0000 C8051F368/9 0xFFFF EXTERNAL DATA ADDRESS SPACE RESERVED 0x4000 0x3FFF FLASH (In-System Programmable in 1024 Byte Sectors) Same 1024 bytes as from 0x0000 to 0x03FF, wrapped on 1024-byte boundaries 0x0400 0x03FF 0x0000 XRAM - 1024 Bytes (accessable using MOVX instruction) 0x0000 Figure 1.6. On-Board Memory Map 1.3. On-Chip Debug Circuitry The C8051F36x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications chan- 24 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 nels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F360DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F36x MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the required cables, and wall-mount power supply. The Development Kit requires a PC running Windows98SE or later. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. Silicon Labs Integrated Development Environment WINDOWS 2000 or later Debug Adapter C2 (x2), VDD, GND VDD GND TARGET PCB C8051F360 Figure 1.7. Development/In-System Debug Diagram 1.4. Programmable Digital I/O and Crossbar C8051F36x devices include up to 39 I/O pins (four byte-wide Ports and one 7-bit-wide Port). The C8051F36x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “weak pullups” that are fixed on typical 8051 devices may be globally disabled, providing power savings capabilities. Rev. 1.0 25 C8051F360/1/2/3/4/5/6/7/8/9 The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins. (See Figure 1.8.) On-chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular application. XBR0, XBR1, PnSKIP Registers P0MASK, P0MATCH P1MASK, P1MATCH, P2MASK, P2MATCH Registers Priority Decoder Highest Priority UART SPI (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK PCA Lowest Priority T0, T1 7 8 2 8 P0 (P0.0-P0.7) 8 P1 (Port Latches) (P1.0-P1.7) 8 P2 (P2.0-P2.7) 8 P3 (P3.0-P3.7) P3 I/O Cells 2 4 2 8 P0 I/O Cells PnMDOUT, PnMDIN Registers P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.7 3.5–3.7 available on C8051F360/3 3.1–3.4 available on C8051F360/1/3/4/6/8 Digital Crossbar 4 8 P1 I/O Cells 8 P2 I/O Cell Figure 1.8. Digital Crossbar Diagram (Port 0 to Port 3) 1.5. Serial Ports The C8051F36x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.6. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three programmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8. The external clock source selection is useful for 26 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 real-time clock functionality, where the PCA is clocked by an external source while the internal oscillator drives the system clock. Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software Timer, High Speed Output, 8- or 16-bit Pulse Width Modulator, or Frequency Output. Additionally, Capture/Compare Module 5 offers watchdog timer (WDT) capabilities. Following a system reset, Module 5 is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input may be routed to Port I/O via the Digital Crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 Capture/Compare Module 3 Capture/Compare Module 4 Capture/Compare Module 5 CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI Crossbar Port I/O Figure 1.10. PCA Block Diagram 1.7. 10-Bit Analog to Digital Converter The C8051F360/1/2/6/7/8/9 devices include an on-chip 10-bit SAR ADC with up to 21 channels for the differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as an ADC inputs; additionally, the on-chip Temperature Sensor output and the power supply voltage (VDD) are available as ADC inputs. User firmware may shut down the ADC to save power. Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an external convert start signal (CNVSTR). This flexibility allows the start of conversion to be triggered by software events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indi- Rev. 1.0 27 C8051F360/1/2/3/4/5/6/7/8/9 cated by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data SFRs upon completion of a conversion. Window compare registers for the ADC data can be configured to interrupt the controller when ADC data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within/outside the specified range. P 1.0-1.3 available on C8051F361/2/6/7/8/9 P1.0 AMX0P AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 ADC0CN AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 101 AD0INT AD0TM AD0EN VDD P1.7 P2.0 23-to-1 AMUX P2.7 P3.0 P3.1-3.4 available on C8051F360/1/6/8 Temp Sensor Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow P3.4 (+) 10-Bit SAR P 1.0-1.3 available on C8051F361/2/6/7/8/9 P1.0 P1.7 P2.0 23-to-1 AMUX SYSCLK REF ADC0H (-) ADC ADC0L VDD AD0WINT Window Compare Logic AD0LJST AD0SC4 AD0SC3 AD0SC2 AD0SC1 AMX0N4 AMX0N3 AMX0N2 AMX0N1 P3.1-3.4 available on C8051F360/1/6/8 AMX0N0 P2.7 P3.0 P3.4 VREF GND AD0SC0 AMX0N ADC0LTH ADC0LTL 32 ADC0CF ADC0GTH ADC0GTL Figure 1.11. 10-Bit ADC Block Diagram 1.8. Comparators C8051F36x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and lowpower modes. Positive and negative hysteresis are also configurable. Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source. Figure 1.12 shows the Comparator0 block diagram, and Figure 1.13 shows the Comparator1 block diagram. Note: The first Port I/O pins shown in Figure 1.12 and Figure 1.13 are for the 48-pin (C8051F360/3) devices. The second set of Port I/O pins are for the 32-pin and 28-pin (C8051F361/2/4/5/6/7/8/9) devices. Please refer to the CPTnMX registers (SFR Definition 8.2 and SFR Definition 8.5) for more information. 28 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 CPT0MX CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P1 CMX0P0 P1.4 / P1.0 P2.3 / P1.4 P3.1 / P2.0 P3.5 / P2.4 CP0 + CP0 D SET CPT0CN V DD + Q Q D SET Q Q GND Reset Decision Tree CLR CLR Crossbar (SYNCHRONIZER) CP0A P1.5 / P1.1 P 2.4 / P1.5 P3.2 / P2.1 P3.6 / P2.5 CP0 - CP0RIF CP0FIF 0 1 0 1 CP0EN 0 1 EA 0 1 CP0 Interrupt CPT0MD CP0RIE CP0FIE CP0MD1 CP0MD0 Figure 1.12. Comparator0 Block Diagram Rev. 1.0 29 C8051F360/1/2/3/4/5/6/7/8/9 CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CPT1MX CMX1N1 CMX1N0 CMX1P1 CMX1P0 P2.0 / P1.2 P2.5 / P1.6 P3.3 / P2.2 P3.7 / P2.6 CP1 + CP1 D SET CPT1CN V DD + Q Q D SET Q Q GND CLR CLR Crossbar (SYNCHRONIZER) CP1A P2.1 / P1.3 P 2.6 / P1.7 P3.4 / P2.3 P4.0 / P2.7 CP1FIF CP1 CP1RIF 0 1 0 1 CP1EN 0 1 EA 0 1 CP1 Interrupt CPT1MD CP1RIE CP1FIE CP1MD1 CP1MD0 Figure 1.13. Comparator1 Block Diagram 1.9. 10-bit Current Output DAC The C8051F360/1/2/6/7/8/9 devices includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDA0 output updates on a write to IDA0H, on a Timer overflow, or on an external pin edge. 30 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Timer 0 Timer 1 Timer 2 Timer 3 10 Latch IDA0H CNVSTR IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 IDA0H 8 IDA0 IDA0 IDA0L 2 Figure 1.14. IDA0 Functional Block Diagram Rev. 1.0 31 C8051F360/1/2/3/4/5/6/7/8/9 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on VDD with respect to GND Maximum Total current through VDD or GND Maximum output current sunk by RST or any Port pin Conditions Min –55 –65 –0.3 –0.3 — — Typ — — — — — — Max 125 150 5.8 4.2 500 100 Units °C °C V V mA mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 32 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage SYSCLK (System Clock)1,2 Specified Operating Temperature Range IDD2 Conditions SYSCLK = 0 to 50 MHz SYSCLK > 50 MHz Min 2.7 3.0 — Typ 3.0 3.3 1.5 — — — Max 3.6 3.6 — 100 50 +85 Units V V MHz MHz °C C8051F360/1/2/3/4/5 C8051F366/7/8/9 0 0 –40 Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash) VDD = 3.6 V, F = 100 MHz VDD = 3.6 V, F = 25 MHz VDD = 3.0 V, F = 100 MHz VDD = 3.0 V, F = 25 MHz VDD = 3.0 V, F = 1 MHz VDD = 3.0 V, F = 80 kHz IDD Supply Sensitivity3 F = 25 MHz F = 1 MHz VDD = 3.0 V, F > 20 MHz, T = 25 °C VDD = 3.6 V, F 20 MHz, T = 25 °C — — — — — — — — — — — — 68 21 54 16 0.48 36 56 57 0.45 0.38 0.61 0.51 75 25 60 18 — — — — — — — — mA mA mA mA mA µA %/V %/V mA/MHz mA/MHz mA/MHz mA/MHz IDD Frequency Sensitivity3,4 VDD = 3.0 V, F 1 MHz, T = 25 °C VDD = 3.6 V, F 1 MHz, T = 25 °C IDD Frequency Sensitivity3,5 VDD = 3.0 V, F 20 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 20 MHz, IDD = 15.9 mA - (25 MHz - 20 MHz) * 0.38 mA/MHz = 14 mA. 5. Idle IDD can be estimated for frequencies < 1 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range. When using these numbers to estimate Idle IDD for >1 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 7.2 mA - (25 MHz - 5 MHz) * 0.25 mA/MHz = 2.2 mA. Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. 34 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 3.2. Index to Electrical Characteristics Tables Peripheral Electrical Characteristics ADC0 Electrical Characteristics IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal High Frequency Oscillator Electrical Characteristics Internal Low Frequency Oscillator Electrical Characteristics PLL Frequency Characteristics Port I/O DC Electrical Characteristics Page No. 62 66 69 79 134 144 171 172 182 201 Rev. 1.0 35 C8051F360/1/2/3/4/5/6/7/8/9 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F36x Name VDD Pin Pin Pin ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin) 19, 31, 43 4 3 — — Type Description Power Supply Voltage. Ground. Analog Ground. Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. 4 3 — — GND 18, 30, 42 AGND AV+ RST/ 6 7 8 5 5 D I/O Device Reset. Open-drain output of internal POR or VDD Monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs. D I/O Clock signal for the C2 Debug Interface. C2CK P4.6/ C2D P3.0/ C2D P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 5 4 3 2 1 48 47 46 2 1 32 31 30 29 28 27 2 1 28 27 26 25 24 23 — 9 — — D I/O or Port 4.6. See Section 17 for a complete description. A In D I/O Bi-directional data signal for the C2 Debug Interface. 6 6 D I/O or Port 3.0. See Section 17 for a complete description. A In D I/O Bi-directional data signal for the C2 Debug Interface. D I/O or Port 0.0. See Section 17 for a complete description. A In D I/O or Port 0.1. See Section 17 for a complete description. A In D I/O or Port 0.2. See Section 17 for a complete description. A In D I/O or Port 0.3. See Section 17 for a complete description. A In D I/O or Port 0.4. See Section 17 for a complete description. A In D I/O or Port 0.5. See Section 17 for a complete description. A In D I/O or Port 0.6. See Section 17 for a complete description. A In D I/O or Port 0.7. See Section 17 for a complete description. A In 36 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F36x (Continued) Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 Pin Pin Pin ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin) 45 44 41 40 39 38 37 36 35 34 33 32 29 28 27 26 25 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 — Type Description 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 — D I/O or Port 1.0. See Section 17 for a complete description. A In D I/O or Port 1.1. See Section 17 for a complete description. A In D I/O or Port 1.2. See Section 17 for a complete description. A In D I/O or Port 1.3. See Section 17 for a complete description. A In D I/O or Port 1.4. See Section 17 for a complete description. A In D I/O or Port 1.5. See Section 17 for a complete description. A In D I/O or Port 1.6. See Section 17 for a complete description. A In D I/O or Port 1.7. See Section 17 for a complete description. A In D I/O or Port 2.0. See Section 17 for a complete description. A In D I/O or Port 2.1. See Section 17 for a complete description. A In D I/O or Port 2.2. See Section 17 for a complete description. A In D I/O or Port 2.3. See Section 17 for a complete description. A In D I/O or Port 2.4. See Section 17 for a complete description. A In D I/O or Port 2.5. See Section 17 for a complete description. A In D I/O or Port 2.6. See Section 17 for a complete description. A In D I/O or Port 2.7. See Section 17 for a complete description. A In D I/O or Port 3.0. See Section 17 for a complete description. A In Rev. 1.0 37 C8051F360/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F36x (Continued) Name P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 Pin Pin Pin ‘F360/3 ‘F361/4/6/8 ‘F362/5/7/9 (48-pin) (32-pin) (28-pin) 24 23 22 21 20 17 16 15 14 13 12 11 10 7 8 9 10 — — — — — — — — — — — — — — — — — — — — — — Type Description D I/O or Port 3.1. See Section 17 for a complete description. A In D I/O or Port 3.2. See Section 17 for a complete description. A In D I/O or Port 3.3. See Section 17 for a complete description. A In D I/O or Port 3.4. See Section 17 for a complete description. A In D I/O or Port 3.5. See Section 17 for a complete description. A In D I/O or Port 3.6. See Section 17 for a complete description. A In D I/O or Port 3.7. See Section 17 for a complete description. A In D I/O or Port 4.0. See Section 17 for a complete description. A In D I/O Port 4.1. See Section 17 for a complete description. D I/O Port 4.2. See Section 17 for a complete description. D I/O Port 4.3. See Section 17 for a complete description. D I/O Port 4.4. See Section 17 for a complete description. D I/O Port 4.5. See Section 17 for a complete description. 38 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 GND P1.5 38 P1.0 VDD P0.5 P1.3 P0.6 48 47 46 P0.7 45 44 P1.1 43 42 41 P1.2 40 39 P1.4 P0.4 P0.3 P0.2 P0.1 P0.0 AGND AV+ /RST/C2CK P4.6/C2D 37 P1.6 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 P1.7 P2.0 P2.1 P2.2 P2.3 VDD C8051F360/3 31 30 29 28 27 26 25 GND P2.4 P2.5 P2.6 P2.7 P3.0 P4.5 P4.4 P4.3 13 14 15 16 17 18 19 20 21 22 23 P4.2 P4.1 P4.0 P3.7 GND VDD P3.5 P3.6 P3.4 P3.3 P3.2 Figure 4.1. TQFP-48 Pinout Diagram (Top View) Rev. 1.0 P3.1 24 39 C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.2. TQFP-48 Package Diagram Table 4.2. TQFP-48 Package Dimensions Dimension A A1 A2 b c D D1 e Min — 0.05 0.95 0.17 0.09 Nom — — 1.00 0.22 — 9.00 BSC. 7.00 BSC. 0.50 BSC. Max 1.20 0.15 1.05 0.27 0.20 Dimension E E1 L aaa bbb ccc ddd θ Min Nom 9.00 BSC. 7.00 BSC. 0.60 0.20 0.20 0.08 0.08 3.5° Max 0.45 0.75 0° 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 40 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 32 31 30 29 28 27 26 P0.1 P0.0 GND VDD /RST/C2CK P3.0/C2D P3.1 P3.2 1 2 3 4 5 6 7 8 25 24 23 22 21 20 19 18 17 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 C8051F361/4/6/8 10 11 12 13 14 15 P2.3 P3.3 P3.4 P2.7 P2.6 P2.5 P2.4 Figure 4.3. LQFP-32 Pinout Diagram (Top View) Rev. 1.0 P2.2 16 9 41 C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.4. LQFP-32 Package Diagram Table 4.3. LQFP-32 Package Dimensions Dimension A A1 A2 b c D D1 e Min — 0.05 1.35 0.30 0.09 Nom — — 1.40 0.37 — 9.00 BSC. 7.00 BSC. 0.80 BSC. Max 1.60 0.15 1.45 0.45 0.20 Dimension E E1 L aaa bbb ccc ddd θ Min Nom 9.00 BSC. 7.00 BSC. 0.60 0.20 0.20 0.10 0.20 3.5° Max 0.45 0.75 0° 7° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020B specification for Small Body Components. 42 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 23 P1.0 22 28 27 26 25 24 P0.1 P0.0 GND VDD /RST/C2CK P3.0/C2D P2.7 1 2 3 4 5 6 GND 7 21 20 19 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 C8051F362/5/7/9 18 17 16 15 10 11 12 13 P2.1 P2.6 P2.5 P2.4 P2.3 P2.2 Figure 4.5. QFN-28 Pinout Diagram (Top View) Rev. 1.0 P2.0 14 8 9 43 C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.6. QFN-28 Package Drawing Table 4.4. QFN-28 Package Dimensions Dimension A A1 A3 b D D2 e E Min 0.80 0.03 0.18 2.90 Nom 0.90 0.07 0.25 REF 0.25 5.00 BSC. 3.15 0.50 BSC. 5.00 BSC. Max 1.00 0.11 0.30 3.35 Dimension E2 L aaa bbb ddd eee Z Y Min 2.90 0.45 Nom 3.15 0.55 0.15 0.10 0.05 0.08 0.435 0.18 Max 3.35 0.65 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-243, variation VHHD except for custom features D2, E2, L, Z, and Y which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 44 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.7. Typical QFN-28 Landing Diagram Rev. 1.0 45 C8051F360/1/2/3/4/5/6/7/8/9 Figure 4.8. QFN-28 Solder Paste Recommendation 46 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 5. 10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9) The ADC0 subsystem for the C8051F360/1/2/6/7/8/9 consists of two analog multiplexers (referred to collectively as AMUX0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured to measure P1.0-P3.4 (where available), the Temperature Sensor output, or VDD with respect to P1.0P3.4, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic ‘1’. The ADC0 subsystem is in low power shutdown when this bit is logic ‘0’. P 1.0-1.3 available on C8051F361/2/6/7/8/9 P1.0 AMX0P AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 ADC0CN AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 000 001 010 011 100 101 AD0INT AD0TM AD0EN VDD P1.7 P2.0 23-to-1 AMUX P2.7 P3.0 P3.1-3.4 available on C8051F360/1/6/8 Temp Sensor Start Conversion AD0BUSY (W) Timer 0 Overflow Timer 2 Overflow Timer 1 Overflow CNVSTR Input Timer 3 Overflow P3.4 (+) 10-Bit SAR P 1.0-1.3 available on C8051F361/2/6/7/8/9 P1.0 P1.7 P2.0 23-to-1 AMUX SYSCLK REF ADC0H (-) ADC ADC0L VDD AD0WINT Window Compare Logic AD0LJST AD0SC4 AD0SC3 AD0SC2 AD0SC1 AMX0N4 AMX0N3 AMX0N2 AMX0N1 P3.1-3.4 available on C8051F360/1/6/8 AMX0N0 P2.7 P3.0 P3.4 VREF GND AD0SC0 AMX0N ADC0LTH ADC0LTL 32 ADC0CF ADC0GTH ADC0GTL Figure 5.1. ADC0 Functional Block Diagram Rev. 1.0 47 C8051F360/1/2/3/4/5/6/7/8/9 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: the AMUX0 Port I/O inputs, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: the AMUX0 Port I/O inputs, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode; all other times, ADC0 operates in Differential Mode. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR Definition 5.1 and SFR Definition 5.2. The conversion code format differs between Single-ended and Differential modes. The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion. Data can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers. Inputs are measured from ‘0’ to VREF * 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage VREF x 1023/1024 VREF x 512/1024 VREF x 256/1024 0 Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x03FF 0x0200 0x0100 0x0000 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x4000 0x0000 When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers. Inputs are measured from -VREF to VREF * 511/512. Example codes are shown below for both right-justified and left-justified data. For right-justified data, the unused MSBs of ADC0H are a sign-extension of the data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’. Input Voltage VREF x 511/512 VREF x 256/512 0 –VREF x 256/512 –VREF Right-Justified ADC0H:ADC0L (AD0LJST = 0) 0x01FF 0x0100 0x0000 0xFF00 0xFE00 Left-Justified ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0000 0xC000 0x8000 Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2,3). See Section “17. Port Input/ Output” on page 183 for more Port I/O configuration details. 48 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 5.2. Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (VTEMP) is the positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. (mV) 1200 1100 1000 900 V TEMP = S lope*(TEMP C) + Offset mV 800 700 -50 0 50 100 (Celsius) Figure 5.2. Typical Temperature Sensor Transfer Function The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, gain and/ or offset calibration is recommended. Typically a 1-point calibration includes the following steps: Step 1. Control/measure the ambient temperature (this temperature must be known). Step 2. Power the device, and delay for a few seconds to allow for self-heating. Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input and GND selected as the negative input. Step 4. Calculate the offset and/or gain characteristics, and store these values in non-volatile memory for use with subsequent temperature sensor measurements. Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. Rev. 1.0 49 C8051F360/1/2/3/4/5/6/7/8/9 5.00 5.00 4.00 4.00 3.00 3.00 2.00 2.00 Error (degrees C) 1.00 1.00 0.00 -40.00 -1.00 -20.00 0.00 40.00 20.00 60.00 80.00 0.00 -1.00 -2.00 -2.00 -3.00 -3.00 -4.00 -4.00 -5.00 -5.00 Temperature (degrees C) Figure 5.3. Temperature Sensor Error with 1-Point Calibration 50 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the following: 1. 2. 3. 4. 5. 6. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN A Timer 0 overflow (i.e., timed continuous conversions) A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal A Timer 3 overflow Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "ondemand". During conversion, the AD0BUSY bit is set to logic ‘1’ and reset to logic ‘0’ when the conversion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT is logic ‘1’. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See Section “21. Timers” on page 247 for timer configuration. Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.7 on the C8051F360 devices and Port pin P0.6 on the C8051F361/2/6/7/8/9 devices. When the CNVSTR input is used as the ADC0 conversion source, the corresponding port pin should be skipped by the Digital Crossbar. To configure the Crossbar to skip the port pin, set the appropriate bit to ‘1’ in register P0SKIP. See Section “17. Port Input/Output” on page 183 for details on Port I/O configuration. Rev. 1.0 51 C8051F360/1/2/3/4/5/6/7/8/9 5.3.2. Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic ‘1’, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling Time Requirements” on page 53. A. ADC0 Timing for External Trigger Source CNVSTR (AD0CM[2:0]=100) 1 2 3 4 5 6 7 8 9 10 11 SAR Clocks AD0TM=1 Low Power or Convert Track Convert Low Power Mode Track AD0TM=0 Track or Convert Convert Write '1' to AD0BUSY, Timer 0, Timer 2, Timer 1, Timer 3 Overflow (AD0CM[2:0]=000, 001,010 011, 101) SAR Clocks AD0TM=1 B. ADC0 Timing for Internal Trigger Source 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Low Power or Convert 1 Track 2 3 4 5 6 7 Convert 8 9 10 11 Low Power Mode SAR Clocks AD0TM=0 Track or Convert Convert Track Figure 5.4. 10-Bit ADC Track and Conversion Example Timing 52 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. In low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements. Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output or VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.1 for ADC0 minimum settling time requirements. Equation 5.1. ADC0 Settling Time Requirements 2 t = ln ⎛ ------⎞ × R TOTAL C SAMPLE ⎝ SA⎠ Where: SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds RTOTAL is the sum of the AMUX0 resistance and any external source resistance. n is the ADC resolution in bits (10). n Differential Mode MUX Select Single-Ended Mode MUX Select Px.x RMUX = 5k CSAMPLE = 5pF RCInput= RMUX * CSAMPLE CSAMPLE = 5pF Px.x RMUX = 5k MUX Select Px.x RMUX = 5k CSAMPLE = 5pF RCInput= RMUX * CSAMPLE Figure 5.5. ADC0 Equivalent Input Circuits Rev. 1.0 53 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select SFR Page: all pages SFR Address: 0xBB R R R R/W R/W R/W R/W R/W Bit0 Reset Value – Bit7 – Bit6 – Bit5 AMX0P4 Bit4 AMX0P3 Bit3 AMX0P2 Bit2 AMX0P1 Bit1 AMX0P0 00000000 Bits 7–5: UNUSED. Read = 000b; Write = don’t care. Bits 4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4-0 00000 (1) ADC0 Positive Input P1.0(1) P1.1(1) P1.2(1) P1.3(1) P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1(2) P3.2(2) P3.3(2) P3.4(2) RESERVED Temp Sensor VDD 00001(1) 00010(1) 00011(1) 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001(2) 10010(2) 10011(2) 10100 10101–11101 11110 11111 (2) Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. 54 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select SFR Page: all pages SFR Address: 0xBA R R R R/W R/W R/W R/W R/W Bit0 Reset Value – Bit7 – Bit6 – Bit5 AMX0N4 Bit4 AMX0N3 Bit3 AMX0N2 Bit2 AMX0N1 Bit1 AMX0N0 00000000 Bits 7–5: UNUSED. Read = 000b; Write = don’t care. Bits 4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended mode. For all other Negative Input selections, ADC0 operates in Differential mode. AMX0N4-0 00000(1) 00001(1) 00010(1) 00011(1) 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001(2) 10010(2) 10011(2) 10100(2) 10101–11101 11110 11111 ADC0 Negative Input P1.0(1) P1.1(1) P1.2(1) P1.3(1) P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1(2) P3.2(2) P3.3(2) P3.4(2) RESERVED VREF GND Notes: 1. Only applies to C8051F361/2/6/7/8/9 (32-pin and 28-pin); selection RESERVED on C8051F360 (48-pin) device. 2. Only applies to C8051F360/1/6/8 (48-pin and 32-pin); selection RESERVED on C8051F362/7/9 (28-pin) devices. Rev. 1.0 55 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Page: all pages SFR Address: 0xBC R/W R/W R/W R/W R/W Bit3 R/W Bit2 R/W R/W Reset Value AD0SC4 Bit7 AD0SC3 Bit6 AD0SC2 Bit5 AD0SC1 Bit4 AD0SC0 AD0LJST – Bit1 – Bit0 11111000 Bits 7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in Table 5.1. SYSCLK AD0SC = --------------------- – 1 CLK SAR AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. Bits 1–0: UNUSED. Read = 00b; Write = don’t care. Bit 2: SFR Definition 5.4. ADC0H: ADC0 Data Word MSB SFR Page: all pages SFR Address: 0xBE R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1–0 are the upper 2 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word. SFR Definition 5.5. ADC0L: ADC0 Data Word LSB SFR Page: all pages SFR Address: 0xBD R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always read ‘0’. 56 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.6. ADC0CN: ADC0 Control SFR Page: all pages SFR Address: 0xE8 (bit addressable) R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value R/W R/W AD0EN Bit7 AD0TM Bit6 AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ready for data conversions. Bit 6: AD0TM: ADC0 Track Mode Bit. 0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion is in progress. 1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below). Bit 5: AD0INT: ADC0 Conversion Complete Interrupt Flag. 0: ADC0 has not completed a data conversion since the last time AD0INT was cleared. 1: ADC0 has completed a data conversion. Bit 4: AD0BUSY: ADC0 Busy Bit. Read: 0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic ‘1’ on the falling edge of AD0BUSY. 1: ADC0 conversion is in progress. Write: 0: No Effect. 1: Initiates ADC0 Conversion if AD0CM2-0 = 000b Bit 3: AD0WINT: ADC0 Window Compare Interrupt Flag. 0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bits 2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select. When AD0TM = 0: 000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY. 001: ADC0 conversion initiated on overflow of Timer 0. 010: ADC0 conversion initiated on overflow of Timer 2. 011: ADC0 conversion initiated on overflow of Timer 1. 100: ADC0 conversion initiated on rising edge of external CNVSTR. 101: ADC0 conversion initiated on overflow of Timer 3. 11x: Reserved. When AD0TM = 1: 000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion. 001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion. 010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion. 011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. Bit 7: Rev. 1.0 57 C8051F360/1/2/3/4/5/6/7/8/9 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate when measured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0 Less-Than and ADC0 Greater-Than registers. SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte SFR Page: all pages SFR Address: 0xC4 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: High byte of ADC0 Greater-Than Data Word. SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte SFR Page: all pages SFR Address: 0xC3 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: Low byte of ADC0 Greater-Than Data Word. 58 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte SFR Page: all pages SFR Address: 0xC6 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte SFR Page: all pages SFR Address: 0xC5 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: Low byte of ADC0 Less-Than Data Word. Rev. 1.0 59 C8051F360/1/2/3/4/5/6/7/8/9 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0x03FF AD0WINT not affected 0x0081 VREF x (128/1024) 0x0080 0x007F AD0WINT=1 VREF x (64/1024) 0x0041 0x0040 0x003F ADC0GTH:ADC0GTL VREF x (64/1024) ADC0LTH:ADC0LTL VREF x (128/1024) Input Voltage (Px.x - GND) VREF x (1023/1024) ADC0H:ADC0L 0x03FF AD0WINT=1 0x0081 0x0080 0x007F 0x0041 0x0040 0x003F AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data ADC0H:ADC0L Input Voltage (Px.x - GND) VREF x (1023/1024) 0xFFC0 AD0WINT not affected 0x2040 VREF x (128/1024) 0x2000 0x1FC0 AD0WINT=1 0x1040 VREF x (64/1024) 0x1000 0x0FC0 ADC0GTH:ADC0GTL VREF x (64/1024) ADC0LTH:ADC0LTL VREF x (128/1024) Input Voltage (Px.x - GND) VREF x (1023/1024) ADC0H:ADC0L 0xFFC0 AD0WINT=1 0x2040 0x2000 0x1FC0 0x1040 0x1000 0x0FC0 AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected 0 0x0000 0 0x0000 Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data 60 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 5.4.2. Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF and VREF*(511/512). Output codes are represented as 10-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)). Figure 5.9 shows an example using left-justified data with the same comparison values. ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF AD0WINT not affected 0x0041 VREF x (64/512) 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) 0xFFFF 0xFFFE ADC0GTH:ADC0GTL VREF x (-1/512) ADC0LTH:ADC0LTL VREF x (64/512) Input Voltage (Px.x - Px.x) VREF x (511/512) ADC0H:ADC0L 0x01FF AD0WINT=1 0x0041 0x0040 0x003F 0x0000 0xFFFF 0xFFFE AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected -VREF 0x0200 -VREF 0x0200 Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x7FC0 AD0WINT not affected 0x1040 VREF x (64/512) 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0xFF80 ADC0GTH:ADC0GTL VREF x (-1/512) ADC0LTH:ADC0LTL VREF x (64/512) Input Voltage (Px.x - Px.y) VREF x (511/512) ADC0H:ADC0L 0x7FC0 AD0WINT=1 0x1040 0x1000 0x0FC0 0x0000 0xFFC0 0xFF80 AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT not affected -VREF 0x8000 -VREF 0x8000 Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data Rev. 1.0 61 C8051F360/1/2/3/4/5/6/7/8/9 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified. Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Conversion Rate SAR Conversion Clock Conversion Time in SAR Clocks Track/Hold Acquisition Time Throughput Rate Analog Inputs ADC Input Voltage Range Absolute Pin Voltage with respect to GND Input Capacitance Temperature Sensor Linearity* Slope Slope Error* Offset Offset Error* Power Specifications Power Supply Current (VDD supplied to ADC0) Power Supply Rejection Operating Mode, 200 ksps — — 450 3 900 — µA mV/V (Temp = 0 °C) — — — — — ±0.2 2.18 ±172 802 ±18.5 — — — — — °C mV/ºC µV/ºC mV mV Single Ended (AIN+ – GND) Differential (AIN+ – AIN–) Single Ended or Differential 0 –VREF 0 — — — — 5 VREF VREF VDD — V V V pF — 13 300 — — — — — 3 — — 200 MHz clocks ns ksps Up to the 5th harmonic Differential mode Guaranteed Monotonic — — –12 –5 53 — — 10 ±0.5 ±0.5 3 1 58 –75 75 ±1 ±1 12 5 — — — bits LSB LSB LSB LSB dB dB dB Conditions Min Typ Max Units Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps) *Note: Represents one standard deviation from the mean. Includes ADC offset, gain, and linearity variations. 62 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 6. 10-Bit Current Mode DAC (IDA0, C8051F360/1/2/6/7/8/9) The C8051F360/1/2/6/7/8/9 devices include a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. The IDAC is enabled or disabled with the IDA0EN bit in the IDA0 Control Register (see SFR Definition 6.1). When IDA0EN is set to ‘0’, the IDAC port pin (P0.4 for C8051F360, P0.1 for C8051F361/2/6/7/8/9) behaves as a normal GPIO pin. When IDA0EN is set to ‘1’, the digital output drivers and weak pullup for the IDAC pin are automatically disabled, and the pin is connected to the IDAC output. An internal bandgap bias generator is used to generate a reference current for the IDAC whenever it is enabled. When using the IDAC, the appropriate bit in the P0SKIP register should be set to ‘1’ to force the Crossbar to skip the IDAC pin. 6.1. IDA0 Output Scheduling IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to IDA0H, on a Timer overflow, or on an external pin edge. 6.1.1. Update Output On-Demand In its default mode (IDA0CN.[6:4] = ‘111’) the IDA0 output is updated “on-demand” on a write to the highbyte of the IDA0 data register (IDA0H). It is important to note that writes to IDA0L are held in this mode, and have no effect on the IDA0 output until a write to IDA0H takes place. If writing a full 10-bit word to the IDAC data registers, the 10-bit data word is written to the low byte (IDA0L) and high byte (IDA0H) data registers. Data is latched into IDA0 after a write to the IDA0H register, so the write sequence should be IDA0L followed by IDA0H if the full 10-bit resolution is required. The IDAC can be used in 8-bit mode by initializing IDA0L to the desired value (typically 0x00), and writing data to only IDA0H (see Section 6.2 for information on the format of the 10-bit IDAC data word within the 16-bit SFR space). IDA0H IDA0CN IDA0EN IDA0CM2 IDA0CM1 IDA0CM0 IDA0OMD1 IDA0OMD0 IDA0H 8 10 Latch IDA0 IDA0 IDA0L 2 Figure 6.1. IDA0 Functional Block Diagram CNVSTR Rev. 1.0 Timer 0 Timer 1 Timer 2 Timer 3 63 C8051F360/1/2/3/4/5/6/7/8/9 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow independently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in systems where the IDAC is used to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latency and instruction execution on the timing of the IDAC output. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘000’, ‘001’, ‘010’ or ‘011’, writes to both IDAC data registers (IDA0L and IDA0H) are held until an associated Timer overflow event (Timer 0, Timer 1, Timer 2 or Timer 3, respectively) occurs, at which time the IDA0H:IDA0L contents are copied to the IDAC input latches, allowing the IDAC output to change to the new value. 6.1.3. Update Output Based on CNVSTR Edge The IDAC output can also be configured to update on a rising edge, falling edge, or both edges of the external CNVSTR signal. When the IDA0CM bits (IDA0CN.[6:4]) are set to ‘100’, ‘101’, or ‘110’, writes to both IDAC data registers (IDA0L and IDA0H) are held until an edge occurs on the CNVSTR input pin. The particular setting of the IDA0CM bits determines whether IDAC outputs are updated on rising, falling, or both edges of CNVSTR. When a corresponding edge occurs, the IDA0H:IDA0L contents are copied to the IDAC input latches, allowing the IDAC output to change to the new value. 6.2. IDAC Output Mapping The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are mapped to bits 7 and 6 of the IDA0L register. The data word mapping for the IDAC is shown in Figure 6.2. IDA0H D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDA0L Input Data Word (D9–D0) 0x000 0x001 0x200 0x3FF Output Current IDA0OMD[1:0] = ‘1x’ 0 mA 1/1024 x 2 mA 512/1024 x 2 mA 1023/1024 x 2 mA Output Current IDA0OMD[1:0] = ‘01’ 0 mA 1/1024 x 1 mA 512/1024 x 1 mA 1023/1024 x 1 mA Output Current IDA0OMD[1:0] = ‘00’ 0 mA 1/1024 x 0.5 mA 512/1024 x 0.5 mA 1023/1024 x 0.5 mA Figure 6.2. IDA0 Data Word Mapping The full-scale output current of the IDAC is selected using the IDA0OMD bits (IDA0CN[1:0]). By default, the IDAC is set to a full-scale output current of 2 mA. The IDA0OMD bits can also be configured to provide full-scale output currents of 1 mA or 0.5 mA, as shown in SFR Definition 6.1. 64 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 6.1. IDA0CN: IDA0 Control SFR Page: all pages SFR Address: 0xB9 R/W R/W Bit6 R/W R/W Bit4 R R R/W Bit1 R/W Bit0 Reset Value IDA0EN Bit7 IDA0CM Bit5 – Bit3 – Bit2 IDA0OMD 01110010 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits. 000: DAC output updates on Timer 0 overflow. 001: DAC output updates on Timer 1 overflow. 010: DAC output updates on Timer 2 overflow. 011: DAC output updates on Timer 3 overflow. 100: DAC output updates on rising edge of CNVSTR. 101: DAC output updates on falling edge of CNVSTR. 110: DAC output updates on any edge of CNVSTR. 111: DAC output updates on write to IDA0H. (default) Bits 3–2: UNUSED. Read = 00b. Write = don’t care. Bits 1–0: IDA0OMD[1:0]: IDA0 Output Mode Select bits. 00: 0.5 mA full-scale output current. 01: 1.0 mA full-scale output current. 1x: 2.0 mA full-scale output current. (default) SFR Definition 6.2. IDA0H: IDA0 Data Word MSB SFR Page: all pages SFR Address: 0x97 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: IDA0 Data Word High-Order Bits. Bits 7–0 are the most-significant bits of the 10-bit IDA0 Data Word. Rev. 1.0 65 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB SFR Page: all pages SFR Address: 0x96 R/W Bit7 R/W Bit6 R R R R R R Reset Value — Bit5 — Bit4 — Bit3 — Bit2 — Bit1 — Bit0 00000000 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5–0: UNUSED. Read = 000000b, Write = don’t care. Table 6.1. IDAC Electrical Characteristics –40 to +85 °C, VDD = 3.0 V Full-scale output current set to 2 mA unless otherwise specified. Parameter Resolution Integral Nonlinearity Differential Nonlinearity Output Compliance Range Offset Error Full Scale Error Full Scale Error Tempco VDD Power Supply Rejection Ratio Dynamic Performance Output Settling Time to 1/2 IDA0H:L = 0x3FF to 0x000 LSB Startup Time Gain Variation 1 mA Full Scale Output Current 0.5 mA Full Scale Output Current Power Consumption 2 mA Full Scale Output Current Power Supply Current (VDD 1 mA Full Scale Output Current supplied to IDAC) 0.5 mA Full Scale Output Current — — — 2140 1140 640 — — — µA µA µA — — — — 5 5 ±1 ±1 — — — — µs µs % % 2 mA Full Scale Output Current Guaranteed Monotonic — — — — –15 — — Conditions Static Performance 10 ±0.5 ±0.5 — 0 0 30 6.5 ±2 ±1 VDD – 1.2 — 15 — — bits LSB LSB V LSB LSB ppm/°C µA/V Min Typ Max Units 66 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 7. Voltage Reference (C8051F360/1/2/6/7/8/9) The Voltage reference MUX on the C8051F360/1/2/6/7/8/9 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the VDD power supply voltage (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source or the internal reference, REFSL should be set to ‘0’. To use VDD as the reference source, REFSL should be set to ‘1’. The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor, internal oscillators, and Current DAC. This bias is enabled when any of the aforementioned peripherals are enabled. The bias generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see SFR Definition 7.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are given in Table 7.1. The internal voltage reference circuit consists of a 1.2 V, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal voltage reference can be driven out on the VREF pin by setting the REFBE bit in register REF0CN to a ‘1’ (see SFR Definition 7.1). The maximum load seen by the VREF pin must be less than 200 µA to GND. When using the internal voltage reference, bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the internal reference is not used, the REFBE bit should be cleared to ‘0’. Electrical specifications for the internal voltage reference are given in Table 7.1. Important Note about the VREF Pin: Port pin P0.3 on the C8051F360 device and P0.0 on C8051F361/2/6/7/89 devices is used as the external VREF input and as an output for the internal VREF. When using either an external voltage reference or the internal reference circuitry, the port pin should be configured as an analog pin, and skipped by the Digital Crossbar. To configure the port pin as an analog pin, set the appropriate bit to ‘0’ in register P0MDIN. To configure the Crossbar to skip the VREF port pin, set the appropriate bit to ‘1’ in register P0SKIP. Refer to Section “17. Port Input/Output” on page 183 for REF0CN REFSL TEMPE BIASE REFBE EN IOSCE N EN VREF Bias Generator To ADC, IDAC, Internal Oscillators VDD R1 External Voltage Reference Circuit Temp Sensor To Analog Mux 0 V REF (to ADC) GND VDD 1 REFBE 4.7 µ F + 0.1 µ F EN Recommended Bypass Capacitors Internal Reference Figure 7.1. Voltage Reference Functional Block Diagram Rev. 1.0 67 C8051F360/1/2/3/4/5/6/7/8/9 complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data. SFR Definition 7.1. REF0CN: Reference Control SFR Page: all pages SFR Address: 0xD1 R R R R R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 – Bit4 REFSL Bit3 TEMPE Bit2 BIASE Bit1 REFBE Bit0 00000000 Bits 7–4: UNUSED. Read = 0000b; Write = don’t care. Bit 3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. Bit 2: TEMPE: Temperature Sensor Enable Bit. 0: Internal Temperature Sensor off. 1: Internal Temperature Sensor on. Bit 1: BIASE: Internal Analog Bias Generator Enable Bit. 0: Internal Bias Generator off. 1: Internal Bias Generator on. Bit 0: REFBE: Internal Reference Buffer Enable Bit. 0: Internal Reference Buffer disabled. 1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin. 68 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 7.1. Voltage Reference Electrical Characteristics VDD = 3.0 V; –40 to +85 °C unless otherwise specified. Parameter Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation VREF Turn-on Time 1 VREF Turn-on Time 2 Power Supply Rejection External Reference (REFBE = 0) Input Voltage Range Input Current Sample Rate = 200 ksps; VREF = 3.0 V Power Specifications ADC Bias Generator Reference Bias Generator BIASE = ‘1’ or AD0EN = ‘1’ or IOSCEN = ‘1’ REFBE = ‘1’ or TEMPE = ‘1’ or IDA0EN = ‘1’ — — 100 30 150 50 µA µA 0 — — 3 VDD — V µA Load = 0 to 200 µA to AGND 4.7 µF tantalum, 0.1 µF ceramic bypass 0.1 µF ceramic bypass Conditions Internal Reference (REFBE = 1) 25 °C ambient 2.35 — — — — — — 2.42 — 25 3 7.5 200 1.4 2.50 10 — — — — — V mA ppm/°C µV/µA ms µs mV/V Min Typ Max Units Rev. 1.0 69 C8051F360/1/2/3/4/5/6/7/8/9 8. Comparators C8051F36x devices include two on-chip programmable voltage comparators, Comparator0 and Comparator1, shown in Figure 8.1 and Figure 8.2 (Note: the port pin Comparator inputs differ between C8051F36x devices. The first Port I/O pin shown is for C8051F360/3 devices). The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 and CP1), or an asynchronous “raw” output (CP0A and CP1A). The asynchronous CP0A and CP1A signals are available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “17.2. Port I/O Initialization” on page 187). Comparator0 may also be used as a reset source (see Section “12.5. Comparator0 Reset” on page 131). The Comparator inputs are selected in the CPT0MX and CPT1MX registers (SFR Definition 8.2 and SFR Definition 8.5). The CMXnP1–CMXnP0 bits select the Comparator positive input; the CMXnN1–CMXnN0 bits select the Comparator negative input. Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “17.3. General Purpose Port I/O” on page 190). CP0EN CP0OUT CMX0N3 CMX0N2 CPT0CN CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 VDD CPT0MX CMX0N1 CMX0N0 CMX0P1 CMX0P0 P1.4 / P1.0 P2.3 / P1.4 P3.1 / P2.0 P3.5 / P2.4 CP0 + CP0 D SET + Q Q D SET Q Q GND Reset Decision Tree CLR CLR Crossbar (SYNCHRONIZER) CP0A P1.5 / P1.1 P 2.4 / P1.5 P3.2 / P2.1 P3.6 / P2.5 CP0 - CP0RIF CP0FIF 0 1 0 1 CP0EN 0 1 EA 0 1 CP0 Interrupt CPT0MD CP0RIE CP0FIE CP0MD1 CP0MD0 Figure 8.1. Comparator0 Functional Block Diagram 70 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 CP1EN CP1OUT CPT1CN CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 V DD CPT1MX CMX1N1 CMX1N0 CMX1P1 CMX1P0 P2.0 / P1.2 P2.5 / P1.6 P3.3 / P2.2 P3.7 / P2.6 CP1 + CP1 D SET + Q Q D SET Q Q GND CLR CLR Crossbar (SYNCHRONIZER) CP1A P2.1 / P1.3 P 2.6 / P1.7 P3.4 / P2.3 P4.0 / P2.7 CP1FIF CP1 CP1RIF 0 1 0 1 CP1EN 0 1 EA 0 1 CP1 Interrupt CPT1MD CP1RIE CP1FIE CP1MD1 CP1MD0 Figure 8.2. Comparator1 Functional Block Diagram A Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous outputs are available even in STOP mode (with no system clock active). When disabled, the Comparator outputs (if assigned to a Port I/O pin via the Crossbar) default to the logic low state, and their supply current falls to less than 100 nA. See Section “17.1. Priority Crossbar Decoder” on page 185 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 8.1. The Comparator response time may be configured in software via the CPT0MD and CPT1MD registers (see SFR Definition 8.3 and SFR Definition 8.6). Selecting a longer response time reduces the Comparator supply current. See Table 8.1 for complete timing and power consumption specifications. Rev. 1.0 71 C8051F360/1/2/3/4/5/6/7/8/9 VIN+ VINCP0+ CP0+ CP0 _ OUT CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) INPUTS VINNegative Hysteresis Voltage (Programmed by CP0HYN Bits) VIN+ VOH OUTPUT VOL Negative Hysteresis Disabled Positive Hysteresis Disabled Maximum Positive Hysteresis Maximum Negative Hysteresis Figure 8.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via the Comparator Control registers CPT0CN and CPT1CN. The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The Comparator hysteresis is programmed using Bits3–0 in the Comparator Control registers CPT0CN and CPT1CN (shown in SFR Definition 8.1 and SFR Definition 8.4). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN and CP1HYN bits. As shown in Figure 8.3, settings of 20, 10 or 5 mV of negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP and CP1HYP bits. Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “10. Interrupt Handler” on page 107). The CP0FIF or CP1FIF flag is set to logic ‘1’ upon a Comparator falling-edge occurrence, and the CP0RIF or CP1RIF flag is set to logic ‘1’ upon the Comparator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE or CP1RIE to a logic ‘1’. The Comparator falling-edge interrupt mask is enabled by setting CP0FIE or CP1FIE to a logic ‘1’. The output state of the Comparator can be obtained at any time by reading the CP0OUT or CP1OUT bit. The Comparator is enabled by setting the CP0EN or CP1EN bit to logic ‘1’, and is disabled by clearing this bit to logic ‘0’. Note that false rising edges and falling edges can be detected when the comparator is first powered on or if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic ‘0’ a short time after the comparator is enabled or its mode bits have been changed. This Power Up Time is specified in Table 8.1 on page 79. 72 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.1. CPT0CN: Comparator0 Control SFR Page: all pages SFR Address: 0x9B R/W R R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value CP0EN Bit7 CP0OUT Bit6 CP0RIF Bit5 CP0FIF Bit4 CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000 CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit 6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit 5: CP0RIF: Comparator0 Rising-Edge Flag. Must be cleared by software. 0: No Comparator0 Rising Edge has occurred since this flag was last cleared. 1: Comparator0 Rising Edge has occurred. Bit 4: CP0FIF: Comparator0 Falling-Edge Flag. Must be cleared by software. 0: No Comparator0 Falling-Edge has occurred since this flag was last cleared. 1: Comparator0 Falling-Edge has occurred. Bits 3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits 1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Bit 7: Rev. 1.0 73 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection SFR Page: all pages SFR Address: 0x9F R/W R/W R/W Bit5 R/W Bit4 R/W R/W R/W R/W Reset Value – Bit7 – Bit6 CMX0N1 CMX0N0 – Bit3 – Bit2 CMX0P1 Bit1 CMX0P0 Bit0 11111111 Bits 7–6: UNUSED. Read = 11b, Write = don’t care. Bits 5–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input. CMX0N1 CMX0N0 0 0 1 1 0 1 0 1 C8051F360/3 Negative Input P1.5 P2.4 P3.2 P3.6 C8051F361/2/4/5/6/7/8/9 Negative Input P1.1 P1.5 P2.1 P2.5 Bits 3–2: UNUSED. Read = 11b, Write = don’t care. Bits 1–0: CMX0P3–CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 0 0 1 1 0 1 0 1 C8051F360/3 Positive Input P1.4 P2.3 P3.1 P3.5 C8051F361/2/4/5/6/7/8/9 Positive Input P1.0 P1.4 P2.0 P2.4 74 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection SFR Page: all pages SFR Address: 0x9D R R R/W R/W R R R/W Bit1 R/W Bit0 Reset Value – Bit7 – Bit6 CP0RIE Bit5 CP0FIE Bit4 – Bit3 – Bit2 CP0MD1 CP0MD0 00000010 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge interrupt enabled. Bit 4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. 0: Comparator0 Falling-edge interrupt disabled. 1: Comparator0 Falling-edge interrupt enabled. Bits 3–2: UNUSED. Read = 00b, Write = don’t care. Bits 1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode 0 1 2 3 CP0MD1 0 0 1 1 CP0MD0 0 1 0 1 CP0 Response Time (TYP) 100 ns 175 ns 320 ns 1050 ns Rev. 1.0 75 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.4. CPT1CN: Comparator1 Control SFR Page: all pages SFR Address: 0x9A R/W R R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value CP1EN Bit7 CP1OUT Bit6 CP1RIF Bit5 CP1FIF Bit4 CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit 6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage on CP1+ > CP1–. Bit 5: CP1RIF: Comparator1 Rising-Edge Flag. Must be cleared by software. 0: No Comparator1 Rising Edge has occurred since this flag was last cleared. 1: Comparator1 Rising Edge has occurred. Bit 4: CP1FIF: Comparator1 Falling-Edge Flag. Must be cleared by software. 0: No Comparator1 Falling-Edge has occurred since this flag was last cleared. 1: Comparator1 Falling-Edge has occurred. Bits 3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits. 00: Positive Hysteresis Disabled. 01: Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits 1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. Bit 7: 76 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.5. CPT1MX: Comparator1 MUX Selection SFR Page: all pages SFR Address: 0x9E R/W R/W R/W Bit5 R/W Bit4 R/W R/W R/W R/W Reset Value – Bit7 – Bit6 CMX1N1 CMX1N0 – Bit3 – Bit2 CMX1P1 Bit1 CMX1P0 Bit0 11111111 Bits 7–6: UNUSED. Read = 11b, Write = don’t care. Bits 5–4: CMX1N1–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. CMX1N1 CMX1N0 0 0 1 1 0 1 0 1 C8051F360/3 Negative Input P2.1 P2.6 P3.4 P4.0 C8051F361/2/4/5/6/7/8/9 Negative Input P1.3 P1.7 P2.3 P2.7 Bits 3–2: UNUSED. Read = 11b, Write = don’t care. Bits 1–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P1 CMX1P0 0 0 1 1 0 1 0 1 C8051F360/3 Positive Input P2.0 P2.5 P3.3 P3.7 C8051F361/2/4/5/6/7/8/9 Positive Input P1.2 P1.6 P2.2 P2.6 Rev. 1.0 77 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 8.6. CPT1MD: Comparator1 Mode Selection SFR Page: all pages SFR Address: 0x9C R R R/W R/W R R R/W Bit1 R/W Bit0 Reset Value – Bit7 – Bit6 CP1RIE Bit5 CP1FIE Bit4 – Bit3 – Bit2 CP1MD1 CP1MD0 00000010 Bits 7–6: UNUSED. Read = 00b, Write = don’t care. Bit 5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable. 0: Comparator1 Rising-edge interrupt disabled. 1: Comparator1 Rising-edge interrupt enabled. Bit 4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable. 0: Comparator1 Falling-edge interrupt disabled. 1: Comparator1 Falling-edge interrupt enabled. Bits 3–2: UNUSED. Read = 00b, Write = don’t care. Bits 1–0: CP1MD1–CP1MD0: Comparator1 Mode Select These bits select the response time for Comparator1. Mode 0 1 2 3 CP1MD1 0 0 1 1 CP1MD0 0 1 0 1 CP1 Response Time (TYP) 100 ns 175 ns 320 ns 1050 ns 78 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 8.1. Comparator Electrical Characteristics VDD = 3.0 V, –40 to +85 °C unless otherwise noted. Parameter Response Time: Mode 0, Vcm* = 1.5 V Response Time: Mode 1, Vcm* = 1.5 V Response Time: Mode 2, Vcm* = 1.5 V Response Time: Mode 3, Vcm* = 1.5 V Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 Negative Hysteresis 2 Negative Hysteresis 3 Negative Hysteresis 4 Inverting or Non-Inverting Input Voltage Range Input Capacitance Input Bias Current Input Offset Voltage Power Supply Power Supply Rejection Power-up Time Mode 0 Supply Current at DC Mode 1 Mode 2 Mode 3 Conditions CPx+ – CPx– = 100 mV CPx+ – CPx– = –100 mV CPx+ – CPx– = 100 mV CPx+ – CPx– = –100 mV CPx+ – CPx– = 100 mV CPx+ – CPx– = –100 mV CPx+ – CPx– = 100 mV CPx+ – CPx– = –100 mV CPxHYP1–0 = 00 CPxHYP1–0 = 01 CPxHYP1–0 = 10 CPxHYP1–0 = 11 CPxHYN1–0 = 00 CPxHYN1–0 = 01 CPxHYN1–0 = 10 CPxHYN1–0 = 11 Min — — — — — — — — — — 1 6 12 — 1 6 12 –0.25 — — –5 — — — — — — Typ 100 250 175 500 320 1100 1050 5200 1.26 0 5 10 20 0 5 10 20 — 4 0.001 — 0.3 10 11.4 4.6 1.9 0.4 Max — — — — — — — — 5 1 10 20 30 1 10 20 30 VDD + 0.25 — — +5 — — 20 10 5 2.5 Units ns ns ns ns ns ns ns ns mV/V mV mV mV mV mV mV mV mV V pF nA mV mV/V µs µA µA µA µA *Note: Vcm is the common-mode voltage on CPx+ and CPx–. Rev. 1.0 79 C8051F360/1/2/3/4/5/6/7/8/9 9. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see description in Section 21), one full-duplex UART (see description in Section 19), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 9.4.6), and up to four byte-wide and one 7-bit-wide I/O Ports (see description in Section 17). The CIP-51 also includes on-chip debug hardware (see description in Section 24), and interfaces directly with the MCU’s analog and digital subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram). - Fully Compatible with MCS-51 Instruction Set - 100 or 50 MIPS Peak Using the On-Chip PLL - 256 Bytes of Internal RAM - 8/4 Byte-Wide I/O Ports The CIP-51 includes the following features: - Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic 9.1. Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 100 MHz, it has a peak throughput of 100 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute Number of Instructions 1 26 2 50 2/3 5 3 14 3/4 7 4 3 4/5 1 5 2 8 1 80 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 DATA BUS D8 D8 D8 D8 D8 ACCUMULATOR B REGISTER STACK POINTER DATA BUS TMP1 TMP2 PSW ALU D8 D8 SRAM ADDRESS REGISTER D8 SRAM (256 X 8) D8 DATA BUS SFR_ADDRESS BUFFER D8 DATA POINTER D8 D8 SFR BUS INTERFACE SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER DATA BUS PROGRAM COUNTER (PC) D8 MEM_ADDRESS MEM_CONTROL MEMORY INTERFACE PRGM. ADDRESS REG. A16 MEM_WRITE_DATA MEM_READ_DATA PIPELINE RESET CLOCK STOP IDLE POWER CONTROL REGISTER D8 D8 CONTROL LOGIC INTERRUPT INTERFACE SYSTEM_IRQs D8 EMULATION_IRQ Figure 9.1. CIP-51 Block Diagram 9.2. Programming and Debugging Support A C2-based serial interface is provided for in-system programming of the Flash program memory and communication with on-chip debug support logic. The re-programmable Flash can also be read and changed by the application software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware breakpoints and watch points, starting, stopping and single stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This method of on-chip debug is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other on-chip resources. The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer. The IDE's debugger and programmer interface to the CIP-51 via its C2 interface to provide fast and efficient in-system device programming and debugging. Third party macro assemblers and C compilers are also available. Rev. 1.0 81 C8051F360/1/2/3/4/5/6/7/8/9 9.3. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set; standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes, addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051. 9.3.1. Instruction and CPU Timing In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle timing. All instruction timings are specified in terms of clock cycles. Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 9.3.2. MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip XRAM, and accessing on-chip program Flash memory. The Flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see Section “13. Flash Memory” on page 135). The External Memory Interface provides a fast access to off-chip XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section “15. External Data Memory Interface and On-Chip XRAM” on page 153 for details. Table 9.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri Description Arithmetic Operations Add register to A Add direct byte to A Add indirect RAM to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect RAM to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect RAM from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect RAM Bytes 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 Clock Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 82 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A RL A RLC A RR A RRC A SWAP A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct Description Decrement A Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust A Logical Operations AND Register to A AND direct byte to A AND indirect RAM to A AND immediate to A AND A to direct byte AND immediate to direct byte OR Register to A OR direct byte to A OR indirect RAM to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR Register to A Exclusive-OR direct byte to A Exclusive-OR indirect RAM to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Rotate A left Rotate A left through Carry Rotate A right Rotate A right through Carry Swap nibbles of A Data Transfer Move Register to A Move direct byte to A Move indirect RAM to A Move immediate to A Move A to Register Move direct byte to Register Move immediate to Register Move A to direct byte Move Register to direct byte Move direct byte to direct byte Bytes 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 Clock Cycles 1 1 2 2 1 4 8 1 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1 1 1 1 1 2 2 2 1 2 2 2 2 3 Rev. 1.0 83 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX @Ri, A MOVX A, @DPTR MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR Description Move indirect RAM to direct byte Move immediate to direct byte Move A to indirect RAM Move direct byte to indirect RAM Move immediate to indirect RAM Load DPTR with 16-bit constant Move code byte relative DPTR to A Move code byte relative PC to A Move external data (8-bit address) to A Move A to external data (8-bit address) Move external data (16-bit address) to A Move A to external data (16-bit address) Push direct byte onto stack Pop direct byte from stack Exchange Register with A Exchange direct byte with A Exchange indirect RAM with A Exchange low nibble of indirect RAM with A Boolean Manipulation Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of direct bit to Carry OR direct bit to carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clear bit Program Branching Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to DPTR Bytes 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 1 2 1 2 2 2 2 2 2 2 2 2 3 3 3 2 3 1 1 2 3 2 1 Clock Cycles 2 3 2 2 2 3 3 3 3 3 3 3 2 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 2/3* 2/3* 3/4* 3/4* 3/4* 3* 4* 5* 5* 3* 4* 3* 3* 84 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel Description Bytes Clock Cycles 2/3* 2/3* 3/4* 3/4* Jump if A equals zero 2 Jump if A does not equal zero 2 Compare direct byte to A and jump if not equal 3 Compare immediate to A and jump if not equal 3 Compare immediate to Register and jump if not CJNE Rn, #data, rel 3 3/4* equal Compare immediate to indirect and jump if not CJNE @Ri, #data, rel 3 4/5* equal DJNZ Rn, rel Decrement Register and jump if not zero 2 2/3* DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/4* NOP No operation 1 1 * Branch instructions will incur a cache-miss penalty if the branch target location is not already stored in the Branch Target Cache. See Section “14. Branch Target Cache” on page 145 for more details. Notes on Registers, Operands and Addressing Modes: Rn - Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (2s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x000x7F) or an SFR (0x80-0xFF). #data - 8-bit constant #data16 - 16-bit constant bit - Direct-accessed bit in Data RAM or SFR addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 64K-byte program memory space. There is one unused opcode (0xA5) that performs the same function as NOP. All mnemonics copyrighted © Intel Corporation 1980. Rev. 1.0 85 C8051F360/1/2/3/4/5/6/7/8/9 9.4. Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. There are 256 bytes of internal data memory and 32k bytes (C8051F360/1/2/3/4/5/6/7) or 16k bytes (C8051F368/9) of internal program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in Figure 9.2. PROGRAM MEMORY C8051F360/1/2/3/4/5/6/7 DATA MEMORY INTERNAL DATA ADDRESS SPACE 0xFF 0x80 0x7F Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Special Function Register's (Direct Addressing Only) RESERVED 0x7C00 0x7BFF FLASH (In-System Programmable in 1024 Byte Sectors) 0x30 0x2F 0x20 0x1F 0x00 Bit Addressable General Purpose Registers L ower 128 RAM (Direct and Indirect Addressing) 0x0000 C8051F368/9 0xFFFF EXTERNAL DATA ADDRESS SPACE RESERVED 0x4000 0x3FFF FLASH (In-System Programmable in 1024 Byte Sectors) Same 1024 bytes as from 0x0000 to 0x03FF, wrapped on 1024-byte boundaries 0x0400 0x03FF 0x0000 XRAM - 1024 Bytes (accessable using MOVX instruction) 0x0000 Figure 9.2. Memory Map 9.4.1. Program Memory The CIP-51 core has a 64 kB program memory space. The C8051F360/1/2/3/4/5/6/7 implement 32 kB of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x7BFF. Addresses above 0x7BFF are reserved on the 32 kB devices. The C8051F368/9 implement 16 kB of Flash from addresses 0x0000 to 0x3FFF. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for nonvolatile data storage. Refer to Section “13. Flash Memory” on page 135 for further details. 86 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 9.4.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFR’s. Instructions that use direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51. 9.4.3. General Purpose Registers The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.8). This allows fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers. 9.4.4. Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22.3h moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag. 9.4.5. Stack A programmer's stack can be located anywhere in the 256 byte data memory. The stack area is designated using the Stack Pointer (SP, address 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07; therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, Rev. 1.0 87 C8051F360/1/2/3/4/5/6/7/8/9 and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. 9.4.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFR’s). The SFR’s provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFR’s found in a typical 8051 implementation as well as implementing additional SFR’s used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFR’s implemented in the CIP-51 System Controller. The SFR registers are accessed whenever the direct addressing mode is used to access memory locations from 0x80 to 0xFF. SFR’s with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well as byte-addressable. All other SFR’s are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 9.3, for a detailed description of each register. 9.4.6.1. SFR Paging The CIP-51 features SFR paging, allowing the device to map many SFR’s into the 0x80 to 0xFF memory address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to 256 SFR’s. The C8051F36x family of devices utilizes two SFR pages: 0 and F. SFR pages are selected using the Special Function Register Page Selection register, SFRPAGE (see SFR Definition 9.2). The procedure for reading and writing an SFR is as follows: 1. Select the appropriate SFR page number using the SFRPAGE register. 2. Use direct accessing mode to read or write the special function register (MOV instruction). 9.4.6.2. Interrupts and SFR Paging When an interrupt occurs, the SFR Page Register will automatically switch to SFR page 0, where all registers containing the interrupt flag bits are accessible. The automatic SFR Page switch function conveniently removes the burden of switching SFR pages from the interrupt service routine. Upon execution of the RETI instruction, the SFR page is automatically restored to the SFR Page in use prior to the interrupt. This is accomplished via a three-byte SFR Page Stack. The top byte of the stack is SFRPAGE, the current SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The third, or bottom byte of the SFR Page Stack is SFRLAST. On interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte, and the value of SFRNEXT is pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page containing the flag bit associated with the interrupt. On a return from interrupt, the SFR Page Stack is popped resulting in the value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR page context without software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the stack is placed in SFRNEXT register. If desired, the values stored in SFRNEXT and SFRLAST may be modified during an interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETI instruction (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of the stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack. 88 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFRPGCN Bit Interrupt Logic SFRPAGE CIP-51 SFRNEXT SFRLAST Figure 9.3. SFR Page Stack Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This function defaults to ‘enabled’ upon reset. In this way, the autoswitching function will be enabled unless disabled in software. A summary of the SFR locations (address and SFR page) is provided in Table 9.2. in the form of an SFR memory map. Each memory location in the map has an SFR page row, denoting the page in which that SFR resides. Note that certain SFR’s are accessible from ALL SFR pages, and are denoted by the background shading in the table. For example, the Port I/O registers P0, P1, P2, and P3 all have a shaded background, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE register value. Rev. 1.0 89 C8051F360/1/2/3/4/5/6/7/8/9 9.4.6.3. SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to OSCICN (SFR “OSCICN”, located at address 0xB6 on SFR Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC0) window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service routine (ISR), so its interrupt is enabled and is set to high priority. The ADC0 is monitoring a voltage that is less important, but to minimize the software overhead its window comparator is being used with an associated ISR that is set to low priority. At this point, the SFR page is set to access the OSCICN SFR (SFRPAGE = 0x0F). See Figure 9.4 below. SFR Page Stack SFR's 0x0F SFRPAGE (OSCICN) SFRNEXT SFRLAST Figure 9.4. SFR Page Stack While Using SFR Page 0x0F To Access OSCICN While CIP-51 executes in-line code (writing values to OSCICN in this example), ADC0 Window Comparator Interrupt occurs. The CIP-51 vectors to the ADC0 Window Comparator ISR and pushes the current SFR Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. SFR page 0x00 is then automatically placed in the SFRPAGE register. SFRPAGE is considered the “top” of the SFR Page Stack. Software can now access the ADC0 SFR’s. Software may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC0 ISR to access SFR’s that are not on SFR Page 0x00. See Figure 9.5 below. 90 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Page 0x00 Automatically pushed on stack in SFRPAGE on ADC0 interrupt 0 x00 SFRPAGE SFRPAGE pushed to SFRNEXT (ADC0) 0x0F SFRNEXT (OSCICN) SFRLAST Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs While in the ADC0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place SFR page 0x00 into the SFRPAGE register. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 0x00 for ADC0) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in this case SFR Page 0x0F for OSCICN) is pushed down to the SFRLAST register, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 9.6 below. SFR Page 0x00 Automatically pushed on stack in SFRPAGE on PCA interrupt 0x00 SFRPAGE SFRPAGE pushed to SFRNEXT (PCA) 0x00 SFRNEXT (ADC0) 0x0F SFRLAST (OSCICN) SFRNEXT pushed to SFRLAST Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR Rev. 1.0 91 C8051F360/1/2/3/4/5/6/7/8/9 On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC0 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC0 ISR can continue to access SFR’s as it did prior to the PCA interrupt. Likewise, the contents of SFRLAST are moved to the SFRNEXT register. Recall this was the SFR Page value 0x0F being used to access OSCICN before the ADC0 interrupt occurred. See Figure 9.7 below. SFR Page 0x00 Automatically popped off of the stack on return from interrupt 0x00 SFRPAGE SFRNEXT popped to SFRPAGE (ADC0) 0x0F SFRNEXT (OSCICN) SFRLAST SFRLAST popped to SFRNEXT Figure 9.7. SFR Page Stack Upon Return From PCA Interrupt 92 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 On the execution of the RETI instruction in the ADC0 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the OSCICN SFR bits as it did prior to the interrupts occurring. See Figure 9.8 below. SFR Page 0x00 Automatically popped off of the stack on return from interrupt 0x0F SFRPAGE SFRNEXT popped to SFRPAGE (OSCICN) SFRNEXT SFRLAST Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to the SFR Page stack can be useful to enable real-time operating systems to control and manage context switching between multiple tasks. Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 9.1. Rev. 1.0 93 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.1. SFR0CN: SFR Page Control SFR Page: F SFR Address: 0xE5 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value Reserved Reserved Reserved Reserved Reserved Reserved Reserved SFRPGEN 00000001 Bits 7–1: RESERVED. Read = 0000000b. Must Write 0000000b. Bit 0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and automatically switch to SFR page 0. This bit is used to control this autopaging function. 0: SFR Automatic Paging disabled. C8051 core will not automatically change to SFR page 0. 1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will automatically switch to SFR page 0. SFR Definition 9.2. SFRPAGE: SFR Page SFR Page: all pages SFR Address: 0xA7 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: SFR Page Bits: Byte Represents the SFR Page the C8051 MCU uses when reading or modifying SFR’s. Write: Sets the SFR Page. Read: Byte is the SFR page the C8051 MCU is using. When enabled in the SFR Page Control Register (SFR0CN), the C8051 will automatically switch to SFR Page 0x00 and return to the previous SFR page upon return from interrupt (unless SFR Stack was altered before a returning from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and push/pop events of this stack are caused by interrupts (and not by reading/writing to the SFRPAGE register) 94 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.3. SFRNEXT: SFR Next Register SFR Page: all pages SFR Address: 0x85 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third entry. The SFR stack bytes may be used alter the context in the SFR Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from interrupts cause pushes and pops of the SFR Page Stack. Write: Sets the SFR Page contained in the second byte of the SFR Stack. This will cause the SFRPAGE SFR to have this SFR page value upon a return from interrupt. Read: Returns the value of the SFR page contained in the second byte of the SFR stack. This is the value that will go to the SFR Page register upon a return from interrupt. SFR Definition 9.4. SFRLAST: SFR Last Register SFR Page: all pages SFR Address: 0x86 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third entry. The SFR stack bytes may be used alter the context in the SFR Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from interrupts cause pushes and pops of the SFR Page Stack. Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt. Read: Returns the value of the SFR page contained in the last entry of the SFR stack. Rev. 1.0 95 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.2. Special Function Register (SFR) Memory Map ADDRESS SFR Page 0(8) SPI0CN B ADC0CN ACC PCA0CN PSW TMR2CN SMB0CN IP P3 IE P2 SCON0 P1 TCON P0 0(8) bit-addressable 1(9) PCA0L MAC0BL P0MDIN 2(A) PCA0H MAC0BH P1MDIN 3(B) 4(C) 5(D) 6(E) 7(F) VDM0CN EMI0TC RSTSRC EIE2 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F 0 F PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 P0MAT P2MDIN P0MASK P3MDIN PCA0CPL5 PCA0CPH5 PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 P1MAT XBR0 PCA0MD REF0CN CCH0TN SMB0CF IDA0CN P2MAT PLL0MUL PLL0DIV SPI0CFG SBUF0 TMR3CN TMOD SP 1(9) P1MASK XBR1 IT01CF SFR0CN EIE1 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3 MAC0OVR CCH0LC CCH0MA P0SKIP P1SKIP P2SKIP TMR2RLL SMB0DAT AMX0N P2MASK PLL0FLT EMI0CN SPI0CKR CPT1CN TMR3RLL TL0 DPL 2(A) TMR2RLH ADC0GTL AMX0P PLL0CN SPI0DAT CPT0CN TMR3RLH TL1 DPH 3(B) TMR2L ADC0GTH ADC0CF FLSTAT MAC0AL P0MDOUT CPT1MD TMR3L TH0 CCH0CN 4(C) TMR2H ADC0LTL ADC0L P4 OSCLCN MAC0AH P1MDOUT CPT0MD TMR3H TH1 SFRNEXT 5(D) EIP1 ADC0LTH ADC0H FLSCL OSCXCN MAC0CF P3SKIP MAC0STA EIP2 EMI0CF OSCICL FLKEY OSCICN MAC0RNDL MAC0RNDH P4MDOUT P3MDOUT P2MDOUT CPT1MX IDA0L CKCON SFRLAST 6(E) SFRPAGE CPT0MX IDA0H PSCTL CLKSEL PCON 7(F) shaded SFRs are accessible on all SFR Pages regardless of the contents of SFRPAGE 96 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register ACC ADC0CF ADC0CN ADC0GTH ADC0GTL ADC0H ADC0L ADC0LTH ADC0LTL AMX0N AMX0P B CCH0CN CCH0LC CCH0MA CCH0TN CKCON CLKSEL CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD CPT1MX DPH DPL EIE1 EIE2 EIP1 EIP2 Address 0xE0 0xBC 0xE8 0xC4 0xC3 0xBE 0xBD 0xC6 0xC5 0xBA 0xBB 0xF0 0x84 0xD2 0xD3 0xC9 0x8E 0x8F 0x9B 0x9D 0x9F 0x9A 0x9C 0x9E 0x83 0x82 0xE6 0xE7 0xCE 0xCF SFR Page All Pages Accumulator Description Page No. page 104 page 561 page 571 page 581 page 581 page 561 page 561 page 591 page 591 page 551 page 541 page 104 page 149 page 151 page 152 page 150 page 254 page 174 page 73 page 75 page 74 page 76 page 78 page 77 page 102 page 102 page 112 page 114 page 113 page 114 All Pages ADC0 Configuration All Pages ADC0 Control All Pages ADC0 Greater-Than High Byte All Pages ADC0 Greater-Than Low Byte All Pages ADC0 Data Word High Byte All Pages ADC0 Data Word Low Byte All Pages ADC0 Less-Than High Byte All Pages ADC0 Less-Than Low Byte All Pages AMUX0 Negative Channel Select All Pages AMUX0 Positive Channel Select All Pages B Register F F F F F Cache Control Cache Lock Cache Miss Accumulator Cache Tuning System Clock Select All Pages Clock Control All Pages Comparator0 Control All Pages Comparator0 Configuration All Pages Comparator0 MUX Selection All Pages Comparator1 Control All Pages Comparator1 Configuration All Pages Comparator1 MUX Selection All Pages Data Pointer High Byte All Pages Data Pointer Low Byte All Pages Extended Interrupt Enable 1 All Pages Extended Interrupt Enable 2 F F Extended Interrupt Priority 1 Extended Interrupt Priority 2 Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. Rev. 1.0 97 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register EMI0CF EMI0CN EMI0TC FLKEY FLSCL FLSTAT IDA0CN IDA0H IDA0L IE IP IT01CF MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3 MAC0AH MAC0AL MAC0BH MAC0BL MAC0CF MAC0OVR MAC0RNDH MAC0RNDL MAC0STA OSCICL OSCICN OSCLCN OSCXCN P0 P0MASK Address 0xC7 0xAA 0xF7 0xB7 0xB6 0xAC 0xB9 0x97 0x96 0xA8 0xB8 0xE4 0xD2 0xD3 0xD4 0xD5 0xA5 0xA4 0xF2 0xF1 0xD7 0xD6 0xAF 0xAE 0xCF 0xBF 0xB7 0xAD 0xB6 0x80 0xF4 SFR Page F F 0 0 F All Pages EMIF Control Description EMIF Configuration EMIF Timing Control Flash Lock and Key Flash Scale Flash Status Page No. page 1562 page 1552 page 1612 page 142 page 143 page 152 page 651 page 651 page 661 page 110 page 111 page 116 page 126 page 125 page 125 page 125 page 123 page 124 page 124 page 124 page 122 page 126 page 126 page 127 page 123 page 170 page 171 page 172 page 175 page 190 page 192 All Pages IDAC0 Control All Pages IDAC0 High Byte All Pages IDAC0 Low Byte All Pages Interrupt Enable All Pages Interrupt Priority All Pages INT0/INT1 Configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F 0 MAC0 Accumulator Byte 0 (LSB) MAC0 Accumulator Byte 1 MAC0 Accumulator Byte 2 MAC0 Accumulator Byte 3 (MSB) MAC0 A Register High Byte MAC0 A Register Low Byte MAC0 B Register High Byte MAC0 B Register Low Byte MAC0 Configuration MAC0 Accumulator Overflow MAC0 Rounding Register High Byte MAC0 Rounding Register Low Byte MAC0 Status Register Internal Oscillator Calibration Internal Oscillator Control Internal L-F Oscillator Control External Oscillator Control Port 0 Mask All Pages Port 0 Latch Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. 98 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register P0MAT P0MDIN P0MDOUT P0SKIP P1 P1MASK P1MAT P1MDIN P1MDOUT P1SKIP P2 P2MASK P2MAT P2MDIN P2MDOUT P2SKIP P3 P3MDIN P3MDOUT P3SKIP P4 P4MDOUT PCA0CN PCA0CPH0 PCA0CPH1 PCA0CPH2 PCA0CPH3 PCA0CPH4 PCA0CPH5 PCA0CPL0 PCA0CPL1 Address 0xF3 0xF1 0xA4 0xD4 0x90 0xE2 0xE1 0xF2 0xA5 0xD5 0xA0 0xB2 0xB1 0xF3 0xA6 0xD6 0xB0 0xF4 0xAF 0xD7 0xB5 0xAE 0xD8 0xFC 0xEA 0xEC 0xEE 0xFE 0xF6 0xFB 0xE9 SFR Page 0 F F F 0 0 F F F 0 0 F F F F F F F Port 0 Match Description Page No. page 192 page 191 page 191 page 192 page 193 page 195 page 194 page 193 page 194 page 194 page 195 page 197 page 197 page 196 page 196 page 197 page 198 page 198 page 199 page 199 page 200 page 200 page 276 page 280 page 280 page 280 page 280 page 280 page 280 page 279 page 279 Port 0 Input Mode Port 0 Output Mode Configuration Port 0 Skip Port 1 Mask Port 1 Match Port 1 Input Mode Port 1 Output Mode Configuration Port 1 Skip Port 2 Mask Port 2 Match Port 2 Input Mode Port 2 Output Mode Configuration Port 2 Skip Port 3 Input Mode Port 3 Output Mode Configuration Port 3 Skip Port 4 Output Mode Configuration All Pages Port 1 Latch All Pages Port 2 Latch All Pages Port 3 Latch All Pages Port 4 Latch All Pages PCA Control All Pages PCA Module 0 Capture/Compare High Byte All Pages PCA Module 1 Capture/Compare High Byte All Pages PCA Module 2 Capture/Compare High Byte All Pages PCA Module 3 Capture/Compare High Byte All Pages PCA Module 4 Capture/Compare High Byte All Pages PCA Module 5 Capture/Compare High Byte All Pages PCA Module 0 Capture/Compare Low Byte All Pages PCA Module 1 Capture/Compare Low Byte Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. Rev. 1.0 99 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register PCA0CPL2 PCA0CPL3 PCA0CPL4 PCA0CPL5 PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 PCA0H PCA0L PCA0MD PCON PLL0CN PLL0DIV PLL0FLT PLL0MUL PSCTL PSW REF0CN RSTSRC SBUF0 SCON0 SFR0CN SFRLAST SFRNEXT SFRPAGE SMB0CF SMB0CN SMB0DAT Address 0xEB 0xED 0xFD 0xF5 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xFA 0xF9 0xD9 0x87 0xB3 0xA9 0xB2 0xB1 0x8F 0xD0 0xD1 0xEF 0x99 0x98 0xE5 0x86 0x85 0xA7 0xC1 0xC0 0xC2 SFR Page Description Page No. page 279 page 279 page 279 page 279 page 278 page 278 page 278 page 278 page 278 page 278 page 279 page 279 page 277 page 106 page 180 page 180 page 181 page 181 page 142 page 103 page 681 page 133 page 226 page 225 page 94 page 95 page 95 page 94 page 208 page 210 page 212 All Pages PCA Module 2 Capture/Compare Low Byte All Pages PCA Module 3 Capture/Compare Low Byte All Pages PCA Module 4 Capture/Compare Low Byte All Pages PCA Module 5 Capture/Compare Low Byte All Pages PCA Module 0 Mode All Pages PCA Module 1 Mode All Pages PCA Module 2 Mode All Pages PCA Module 3 Mode All Pages PCA Module 4 Mode All Pages PCA Module 5 Mode All Pages PCA Counter High Byte All Pages PCA Counter Low Byte All Pages PCA Mode All Pages Power Control F F F F 0 PLL Control PLL Divider PLL Filter PLL Multiplier Flash Write/Erase Control All Pages Program Status Word All Pages Voltage Reference Control All Pages Reset Source All Pages UART 0 Data Buffer All Pages UART 0 Control F SFR Page Control All Pages SFR Stack Last Page All Pages SFR Stack Next Page All Pages SFR Page Select All Pages SMBus Configuration All Pages SMBus Control All Pages SMBus Data Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. 100 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register SP SPI0CFG SPI0CKR SPI0CN SPI0DAT TCON TH0 TH1 TL0 TL1 TMOD TMR2CN TMR2H TMR2L TMR2RLH TMR2RLL TMR3CN TMR3H TMR3L TMR3RLH TMR3RLL VDM0CN XBR0 XBR1 Address 0x81 0xA1 0xA2 0xF8 0xA3 0x88 0x8C 0x8D 0x8A 0x8B 0x89 0xC8 0xCD 0xCC 0xCB 0xCA 0x91 0x95 0x94 0x93 0x92 0xFF 0xE1 0xE2 SFR Page All Pages Stack Pointer Description Page No. page 102 page 241 page 243 page 242 page 243 page 252 page 255 page 255 page 255 page 255 page 253 page 258 page 259 page 259 page 259 page 259 page 262 page 263 page 263 page 263 page 263 page 131 page 188 page 189 All Pages SPI Configuration All Pages SPI Clock Rate Control All Pages SPI Control All Pages SPI Data All Pages Timer/Counter Control All Pages Timer/Counter 0 High Byte All Pages Timer/Counter 1 High Byte All Pages Timer/Counter 0 Low Byte All Pages Timer/Counter 1 Low Byte All Pages Timer/Counter Mode All Pages Timer/Counter 2 Control All Pages Timer/Counter 2 High Byte All Pages Timer/Counter 2 Low Byte All Pages Timer 2 Reload Register High Byte All Pages Timer 2 Reload Register Low Byte All Pages Timer 3 Control All Pages Timer 3 High Byte All Pages Timer 3 Low Byte All Pages Timer 3 Reload Register High Byte All Pages Timer 3 Reload Register Low Byte All Pages VDD Monitor Control F Port I/O Crossbar Control 0 F Port I/O Crossbar Control 1 Notes: 1. Refers to a register in the C8051F360/1/2/6/7/8/9 only. 2. Refers to a register in the C8051F360/3 only. Rev. 1.0 101 C8051F360/1/2/3/4/5/6/7/8/9 9.4.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic ‘1’. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic ‘0’, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included in the sections of the data sheet associated with their corresponding system function. SFR Definition 9.5. SP: Stack Pointer SFR Page: all pages SFR Address: 0x81 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000111 Bits 7–0: SP: Stack Pointer. The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before every PUSH operation. The SP register defaults to 0x07 after reset. SFR Definition 9.6. DPL: Data Pointer Low Byte SFR Page all pages SFR Address: 0x82 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: DPL: Data Pointer Low. The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. SFR Definition 9.7. DPH: Data Pointer High Byte SFR Page: all pages SFR Address: 0x83 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. 102 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.8. PSW: Program Status Word SFR Page: all pages SFR Address: 0xD0 (bit addressable) R/W R/W R/W R/W R/W R Reset Value R/W R/W CY Bit7 AC Bit6 F0 Bit5 RS1 Bit4 RS0 Bit3 OV Bit2 F1 Bit1 PARITY Bit0 00000000 Bit 7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations. Bit 6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations. Bit 5: F0: User Flag 0. This is a bit-addressable, general purpose flag for use under software control. Bits 4–3: RS1–RS0: Register Bank Select. These bits select which register bank is used during register accesses. RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 Address 0x00–0x07 0x08–0x0F 0x10–0x17 0x18–0x1F Bit 2: Bit 1: Bit 0: OV: Overflow Flag. This bit is set to 1 under the following circumstances: • An ADD, ADDC, or SUBB instruction causes a sign-change overflow. • A MUL instruction results in an overflow (result is greater than 255). • A DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases. F1: User Flag 1. This is a bit-addressable, general purpose flag for use under software control. PARITY: Parity Flag. This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. Rev. 1.0 103 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.9. ACC: Accumulator SFR Page: all pages SFR Address: 0xE0 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W ACC.7 Bit7 ACC.6 Bit6 ACC.5 Bit5 ACC.4 Bit4 ACC.3 Bit3 ACC.2 Bit2 ACC.1 Bit1 ACC.0 Bit0 00000000 Bits 7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9.10. B: B Register SFR Page: all pages SFR Address: 0xF0 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W B.7 Bit7 B.6 Bit6 B.5 Bit5 B.4 Bit4 B.3 Bit3 B.2 Bit2 B.1 Bit1 B.0 Bit0 00000000 Bits 7–0: B: B Register. This register serves as a second accumulator for certain arithmetic operations. 9.5. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Definition 9.11 describes the Power Control Register (PCON) used to control the CIP51's power management modes. Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses, draw little power whenever they are not in use. Turning off the Flash memory saves power, similar to entering Idle mode. Turning off the oscillator saves even more power, but requires a reset to restart the MCU. The C8051F36x devices feature an additional low-power SUSPEND mode, which stops the internal oscillator until an awakening event occurs. See Section “16.1.1. Internal Oscillator Suspend Mode” on page 170 for more information. 104 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 9.5.1. Idle Mode Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog and digital peripherals can remain active during Idle mode. Idle mode is terminated when an enabled interrupt or RST is asserted. The assertion of an enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000. If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section 22.3 for more information on the use and configuration of the WDT. Note: Any instruction which sets the IDLE bit should be immediately followed by an instruction which has two or more opcode bytes. For example: // in ‘C’: PCON |= 0x01; PCON = PCON; ; in assembly: ORL PCON, #01h MOV PCON, PCON // Set IDLE bit // ... Followed by a 3-cycle Dummy Instruction ; Set IDLE bit ; ... Followed by a 3-cycle Dummy Instruction If the instruction following the write to the IDLE bit is a single-byte instruction and an interrupt occurs during the execution of the instruction of the instruction which sets the IDLE bit, the CPU may not wake from IDLE mode when a future interrupt occurs. 9.5.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program execution at address 0x0000. If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs. 9.5.3. Suspend Mode The C8051F36x devices feature a low-power SUSPEND mode, which stops the internal oscillator until an awakening event occurs. See Section “16.1.1. Internal Oscillator Suspend Mode” on page 170. Rev. 1.0 105 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 9.11. PCON: Power Control SFR Page: all pages SFR Address: 0x87 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W R/W Reset Value Reserved Reserved Reserved Reserved Reserved Reserved STOP Bit1 IDLE Bit0 00000000 Bits 7–3: RESERVED. Read = 000000b. Must Write 000000b. Bit 1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. 1: CIP-51 forced into power-down mode. (Turns off oscillator). Bit 0: IDLE: IDLE Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’. 1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, and all peripherals remain active.) 106 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 10. Interrupt Handler The C8051F36x family includes an extended interrupt system supporting a total of 16 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic ‘1’. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic ‘1’ regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the Interrupt Enable and Extended Interrupt Enable SFRs. However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic ‘1’ before the individual interrupt enables are recognized. Setting the EA bit to logic ‘0’ disables all interrupt sources regardless of the individual interruptenable settings. Note that interrupts which occur when the EA bit is set to logic ‘0’ will be held in a pending state, and will not be serviced until the EA bit is set back to logic ‘1’. Note: Any instruction that clears a bit to disable an interrupt should be immediately followed by an instruction that has two or more opcode bytes. Using EA (global interrupt enable) as an example: // in 'C': EA = 0; // clear EA bit. EA = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode. For example, if an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears a bit to disable an interrupt source), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. However, a read of the enable bit will return a '0' inside the interrupt service routine. When the bit-clearing opcode is followed by a multi-cycle instruction, the interrupt will not be taken. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 10.1. MCU Interrupt Sources and Vectors The C8051F36x MCUs support 16 interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic ‘1’. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order, and control bits are summarized in Table 10.1 on page 108. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Rev. 1.0 107 C8051F360/1/2/3/4/5/6/7/8/9 10.2. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP, EIP1, or EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 10.1. 10.3. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. Additional clock cycles will be required if a cache miss occurs (see Section 14 for more details). If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) is when the CPU is performing an RETI instruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Table 10.1. Interrupt Summary Bit addressable? Cleared by HW? Interrupt Source Interrupt Priority Pending Flag Vector Order Enable Flag Priority Control Reset External Interrupt 0 (/INT0) Timer 0 Overflow External Interrupt 1 (/INT1) Timer 1 Overflow UART0 Timer 2 Overflow 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B Top 0 1 2 3 4 5 None IE0 (TCON.1) TF0 (TCON.5) IE1 (TCON.3) TF1 (TCON.7) RI0 (SCON0.0) TI0 (SCON0.1) TF2H (TMR2CN.7) TF2L (TMR2CN.6) SPIF (SPI0CN.7) WCOL (SPI0CN.6) MODF (SPI0CN.5) RXOVRN (SPI0CN.4) SI (SMB0CN.0) N/A AD0WINT (ADC0CN.5) AD0INT (ADC0STA.5) N/A N/A Y Y Y Y Y Y Y Y Y Y N N Always Always Enabled Highest EX0 (IE.0) PX0 (IP.0) ET0 (IE.1) PT0 (IP.1) EX1 (IE.2) PX1 (IP.2) ET1 (IE.3) PT1 (IP.3) ES0 (IE.4) PS0 (IP.4) ET2 (IE.5) ESPI0 (IE.6) ESMB0 (EIE1.0) N/A EWADC0 (EIE1.2) EADC0 (EIE1.3) PT2 (IP.5) PSPI0 (IP.6) PSMB0 (EIP1.0) N/A PWADC0 (EIP1.2) PADC0 (EIP1.3) SPI0 0x0033 6 Y N SMB0 RESERVED ADC0 Window Comparator ADC0 End of Conversion 0x003B 0x0043 0x004B 0x0053 7 8 9 10 Y N N/A N/A Y Y N N 108 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 10.1. Interrupt Summary (Continued) Bit addressable? Cleared by HW? Interrupt Source Interrupt Priority Pending Flag Vector Order Enable Flag Priority Control Programmable Counter Array Comparator0 Comparator1 Timer 3 Overflow RESERVED Port Match 0x005B 0x0063 0x006B 0x0073 0x007B 0x0083 11 12 13 14 15 16 CF (PCA0CN.7) CCFn (PCA0CN.n) CP0FIF (CPT0CN.4) CP0RIF (CPT0CN.5) CP1FIF (CPT1CN.4) CP1RIF (CPT1CN.5) TF3H (TMR3CN.7) TF3L (TMR3CN.6) N/A N/A Y N N N N N N N N/A N/A N/A N/A EPCA0 (EIE1.4) ECP0 (EIE1.5) ECP1 (EIE1.6) ET3 (EIE1.7) N/A EMAT (EIE2.1) PPCA0 (EIP1.4) PCP0 (EIP1.5) PCP1 (EIP1.6) PT3 (EIP1.7) N/A PMAT (EIP2.1) 10.4. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Rev. 1.0 109 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.1. IE: Interrupt Enable SFR Page: all pages SFR Address: 0xA8 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W EA Bit7 ESPI0 Bit6 ET2 Bit5 ES0 Bit4 ET1 Bit3 EX1 Bit2 ET0 Bit1 EX0 Bit0 00000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: EA: Global Interrupt Enable. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of the SPI0 interrupts. 0: Disable all SPI0 interrupts. 1: Enable interrupt requests generated by SPI0. ET2: Enable Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable interrupt requests generated by the TF2L or TF2H flags. ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable all Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag. EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the /INT1 input. ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. 110 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.2. IP: Interrupt Priority SFR Page: all pages SFR Address: 0xB8 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R R/W – Bit7 PSPI0 Bit6 PT2 Bit5 PS0 Bit4 PT1 Bit3 PX1 Bit2 PT0 Bit1 PX0 Bit0 10000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: UNUSED. Read = 1b, Write = don't care. PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. 1: SPI0 interrupt set to high priority level. PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority level. 1: Timer 2 interrupt set to high priority level. PS0: UART0 Interrupt Priority Control. This bit sets the priority of the UART0 interrupt. 0: UART0 interrupt set to low priority level. 1: UART0 interrupt set to high priority level. PT1: Timer 1 Interrupt Priority Control. This bit sets the priority of the Timer 1 interrupt. 0: Timer 1 interrupt set to low priority level. 1: Timer 1 interrupt set to high priority level. PX1: External Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 0: External Interrupt 1 set to low priority level. 1: External Interrupt 1 set to high priority level. PT0: Timer 0 Interrupt Priority Control. This bit sets the priority of the Timer 0 interrupt. 0: Timer 0 interrupt set to low priority level. 1: Timer 0 interrupt set to high priority level. PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. Rev. 1.0 111 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.3. EIE1: Extended Interrupt Enable 1 SFR Page: all pages SFR Address: 0xE6 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value ET3 Bit7 ECP1 Bit6 ECP0 Bit5 EPCA0 Bit4 EADC0 Bit3 EWADC0 Bit2 – Bit1 ESMB0 Bit0 00000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. ECP1: Enable Comparator1 (CP1) Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 interrupts. 1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags. ECP0: Enable Comparator0 (CP0) Interrupt. This bit sets the masking of the CP0 interrupt. 0: Disable CP0 interrupts. 1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags. EPCA0: Enable Programmable Counter Array (PCA0) Interrupt. This bit sets the masking of the PCA0 interrupts. 0: Disable all PCA0 interrupts. 1: Enable interrupt requests generated by PCA0. EADC0: Enable ADC0 Conversion Complete Interrupt. This bit sets the masking of the ADC0 Conversion Complete interrupt. 0: Disable ADC0 Conversion Complete interrupt. 1: Enable interrupt requests generated by the AD0INT flag. EWADC0: Enable ADC0 Window Comparison Interrupt. This bit sets the masking of the ADC0 Window Comparison interrupt. 0: Disable ADC0 Window Comparison interrupt. 1: Enable interrupt requests generated by the AD0WINT flag. UNUSED. Read = 0b. Write = don’t care. ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. 112 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.4. EIP1: Extended Interrupt Priority 1 SFR Page: F SFR Address: 0xCE R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PT3 Bit7 PCP1 Bit6 PCP0 Bit5 PPCA0 Bit4 PADC0 Bit3 PWADC0 Bit2 – Bit1 PSMB0 Bit0 00000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. PCP1: Comparator1 (CP1) Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 interrupt set to low priority level. 1: CP1 interrupt set to high priority level. PCP0: Comparator0 (CP0) Interrupt Priority Control. This bit sets the priority of the CP0 interrupt. 0: CP0 interrupt set to low priority level. 1: CP0 interrupt set to high priority level. PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control. This bit sets the priority of the PCA0 interrupt. 0: PCA0 interrupt set to low priority level. 1: PCA0 interrupt set to high priority level. PADC0: ADC0 Conversion Complete Interrupt Priority Control. This bit sets the priority of the ADC0 Conversion Complete interrupt. 0: ADC0 Conversion Complete interrupt set to low priority level. 1: ADC0 Conversion Complete interrupt set to high priority level. PWADC0: ADC0 Window Comparison Interrupt Priority Control. This bit sets the priority of the ADC0 Window Comparison interrupt. 0: ADC0 Window Comparison interrupt set to low priority level. 1: ADC0 Window Comparison interrupt set to high priority level. UNUSED. Read = 0b. Write = don’t care. PSMB0: SMBus (SMB0) Interrupt Priority Control. This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. Rev. 1.0 113 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.5. EIE2: Extended Interrupt Enable 2 SFR Page: all pages SFR Address: 0xE7 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 – Bit4 – Bit3 – Bit2 EMAT Bit1 – Bit0 00000000 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: EMAT: Enable Port Match Interrupt. This bit sets the masking of the Port Match interrupt. 0: Disable the Port Match interrupt. 1: Enable the Port Match interrupt. Bit 0: UNUSED. Read = 0b. Write = don’t care. SFR Definition 10.6. EIP2: Extended Interrupt Priority 2 SFR Page: F SFR Address: 0xCF R/W R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 – Bit4 – Bit3 – Bit2 PMAT Bit1 – Bit0 00000000 Bits 7–2: UNUSED. Read = 000000b. Write = don’t care. Bit 1: PMAT: Port Match Interrupt Priority Control. This bit sets the priority of the Port Match interrupt. 0: Port Match interrupt set to low priority level. 1: Port Match interrupt set to high priority level. Bit 0: UNUSED. Read = 0b. Write = don’t care. 114 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 10.5. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “21.1. Timer 0 and Timer 1” on page 248) select level or edge sensitive. The table below lists the possible configurations. IT0 1 1 0 0 IN0PL 0 1 0 1 /INT0 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive IT1 1 1 0 0 IN1PL 0 1 0 1 /INT1 Interrupt Active low, edge sensitive Active high, edge sensitive Active low, level sensitive Active high, level sensitive /INT0 and /INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 10.7). Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and /INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see Section “17.1. Priority Crossbar Decoder” on page 185 for complete details on configuring the Crossbar). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag remains logic ‘1’ while the input is active as defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic ‘0’ while the input is inactive. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. Rev. 1.0 115 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 10.7. IT01CF: INT0/INT1 Configuration SFR Page: all pages SFR Address: 0xE4 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value IN1PL Bit7 IN1SL2 Bit6 IN1SL1 Bit5 IN1SL0 Bit4 IN0PL Bit3 IN0SL2 Bit2 IN0SL1 Bit1 IN0SL0 Bit0 00000001 Note: Refer to SFR Definition 21.1. “TCON: Timer Control” on page 252 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits 6–4: IN1SL2-0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN1SL2-0 000 001 010 011 100 101 110 111 Bit 3: /INT1 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 IN0PL: /INT0 Polarity 0: /INT0 interrupt is active low. 1: /INT0 interrupt is active high. Bits 2–0: INT0SL2-0: /INT0 Port Pin Selection Bits These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by setting to ‘1’ the corresponding bit in register P0SKIP). IN0SL2-0 000 001 010 011 100 101 110 111 /INT0 Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 116 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 11. Multiply And Accumulate (MAC0) The C8051F36x devices include a multiply and accumulate engine which can be used to speed up many mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or fractional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles. A rounding engine provides a rounded 16-bit fractional result after an additional (third) SYSCLK cycle. MAC0 also contains a 1-bit arithmetic shifter that will left or right-shift the contents of the 40-bit accumulator in a single SYSCLK cycle. Figure 11.1 shows a block diagram of the MAC0 unit and its associated Special Function Registers. MAC0 A Register MAC0AH MAC0AL MAC0 B Register MAC0BH MAC0BL MAC0MS MAC0FM 16 x 16 Multiply 1 0 0 40 bit Add MAC0OVR MAC0 Accumulator MAC0ACC3 MAC0ACC2 MAC0ACC1 MAC0ACC0 1 bit Shift Rounding Engine Flag Logic MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS MAC0CF MAC0STA Figure 11.1. MAC0 Block Diagram 11.1. Special Function Registers There are thirteen Special Function Register (SFR) locations associated with MAC0. Two of these registers are related to configuration and operation, while the other eleven are used to store multi-byte input and output data for MAC0. The Configuration register MAC0CF (SFR Definition 11.1) is used to configure and control MAC0. The Status register MAC0STA (SFR Definition 11.2) contains flags to indicate overflow conditions, as well as zero and negative results. The 16-bit MAC0A (MAC0AH:MAC0AL) and MAC0B (MAC0BH:MAC0BL) registers are used as inputs to the multiplier. The MAC0 Accumulator register is 40 bits long, and consists of five SFRs: MAC0OVR, MAC0ACC3, MAC0ACC2, MAC0ACC1, and MAC0ACC0. The primary results of a MAC0 operation are stored in the Accumulator registers. If they are needed, the rounded results are stored in the 16-bit Rounding Register MAC0RND (MAC0RNDH:MAC0RNDL). Rev. 1.0 MAC0HO MAC0Z MAC0SO MAC0N MAC0 Rounding Register MAC0RNDH MAC0RNDL 117 C8051F360/1/2/3/4/5/6/7/8/9 11.2. Integer and Fractional Math MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as 16-bit, 2’s complement, integer values. After the operation, the accumulator will contain a 40-bit, 2’s complement, integer value. Figure 11.2 shows how integers are stored in the SFRs. MAC0A and MAC0B Bit Weighting High Byte -(215) 214 213 212 211 210 29 28 27 26 25 Low Byte 24 23 22 21 20 MAC0 Accumulator Bit Weighting MAC0OVR -(239) 238 233 232 MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0 231 230 229 228 24 23 22 21 20 Figure 11.2. Integer Mode Data Representation When the MAC0FM bit is set to ‘1’, the inputs are treated at 16-bit, 2’s complement, fractional values. The decimal point is located between bits 15 and 14 of the data word. After the operation, the accumulator will contain a 40-bit, 2’s complement, fractional value, with the decimal point located between bits 31 and 30. Figure 11.3 shows how fractional numbers are stored in the SFRs. MAC0A, and MAC0B Bit Weighting High Byte -1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 Low Byte 2-11 2-12 2-13 2-14 2-15 MAC0 Accumulator Bit Weighting MAC0OVR -(28) 27 22 21 MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0 20 2-1 2-2 2-3 2-27 2-28 2-29 2-30 2-31 MAC0RND Bit Weighting High Byte * -2 1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 Low Byte 2-11 2-12 2-13 2-14 2-15 * The MAC0RND register contains the 16 LSBs of a two's complement number. The MAC0N Flag can be used to determine the sign of the MAC0RND register. Figure 11.3. Fractional Mode Data Representation 118 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 11.3. Operating in Multiply and Accumulate Mode MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to ‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A and MAC0B registers, and adds the result to the contents of the 40-bit MAC0 accumulator. Figure 11.4 shows the MAC0 pipeline. There are three stages in the pipeline, each of which takes exactly one SYSCLK cycle to complete. The MAC operation is initiated with a write to the MAC0BL register. After the MAC0BL register is written, MAC0A and MAC0B are multiplied on the first SYSCLK cycle. During the second stage of the MAC0 pipeline, the results of the multiplication are added to the current accumulator contents, and the result of the addition is stored in the MAC0 accumulator. The status flags in the MAC0STA register are set after the end of the second pipeline stage. During the second stage of the pipeline, the next multiplication can be initiated by writing to the MAC0BL register, if it is desired. The rounded (and optionally, saturated) result is available in the MAC0RNDH and MAC0RNDL registers at the end of the third pipeline stage. If the MAC0CA bit (MAC0CF.3) is set to ‘1’ when the MAC operation is initiated, the accumulator and all MAC0STA flags will be cleared during the next cycle of the controller’s clock (SYSCLK). The MAC0CA bit will clear itself to ‘0’ when the clear operation is complete. MAC0 Operation Begins Accumulator Results Available Rounded Results Available Write MAC0BL Multiply Add Write MAC0BL Round Multiply Add Round Next MAC0 Operation May Be Initiated Here Figure 11.4. MAC0 Pipeline 11.4. Operating in Multiply Only Mode MAC0 operates in Multiply Only mode when the MAC0MS bit (MAC0CF.0) is set to ‘1’. Multiply Only mode is identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of zero before being stored in the MAC0 accumulator (i.e. it overwrites the current accumulator contents). The result of the multiplication is available in the MAC0 accumulator registers at the end of the second MAC0 pipeline stage (two SYSCLKs after writing to MAC0BL). As in MAC mode, the rounded result is available in the MAC0 Rounding Registers after the third pipeline stage. Note that in Multiply Only mode, the MAC0HO flag is not affected. 11.5. Accumulator Shift Operations MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accumulator left or right by one bit. The accumulator shift is initiated by writing a ‘1’ to the MAC0SC bit (MAC0CF.5), and takes one SYSCLK cycle (the rounded result is available in the MAC0 Rounding Registers after a second SYSCLK cycle, and MAC0SC is cleared to ‘0’). The direction of the arithmetic shift is controlled by the MAC0SD bit (MAC0CF.4). When this bit is cleared to ‘0’, the MAC0 accumulator will shift left. When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not affected by shift operations. Rev. 1.0 119 C8051F360/1/2/3/4/5/6/7/8/9 11.6. Rounding and Saturation A Rounding Engine is included, which can be used to provide a rounded result when operating on fractional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31–16 of the accumulator, as shown in Table 11.1. Rounding occurs during the third stage of the MAC0 pipeline, after any shift operation, or on a write to the LSB of the accumulator. The rounded results are stored in the rounding registers: MAC0RNDH (SFR Definition 11.12) and MAC0RNDL (SFR Definition 11.13). The accumulator registers are not affected by the rounding engine. Although rounding is primarily used for fractional data, the data in the rounding registers is updated in the same way when operating in integer mode. Table 11.1. MAC0 Rounding (MAC0SAT = 0) Accumulator Bits 15–0 (MAC0ACC1:MAC0ACC0) Greater Than 0x8000 Less Than 0x8000 Equal To 0x8000 Equal To 0x8000 Accumulator Bits 31–16 (MAC0ACC3:MAC0ACC2) Anything Anything Odd (LSB = 1) Even (LSB = 0) Rounding Direction Up Down Up Down Rounded Results (MAC0RNDH:MAC0RNDL) (MAC0ACC3:MAC0ACC2) + 1 (MAC0ACC3:MAC0ACC2) (MAC0ACC3:MAC0ACC2) + 1 (MAC0ACC3:MAC0ACC2) The rounding engine can also be used to saturate the results stored in the rounding registers. If the MAC0SAT bit is set to ‘1’ and the rounding register overflows, the rounding registers will saturate. When a positive overflow occurs, the rounding registers will show a value of 0x7FFF when saturated. For a negative overflow, the rounding registers will show a value of 0x8000 when saturated. If the MAC0SAT bit is cleared to ‘0’, the rounding registers will not saturate. 11.7. Usage Examples This section details some software examples for using MAC0. Section 11.7.1 shows a series of two MAC operations using fractional numbers. Section 11.7.2 shows a single operation in Multiply Only mode with integer numbers. The last example, shown in Section 11.7.3, demonstrates how the left-shift and right-shift operations can be used to modify the accumulator. All of the examples assume that all of the flags in the MAC0STA register are initially set to ‘0’. 11.7.1. Multiply and Accumulate Example The example below implements the equation: ( 0.5 × 0.25 ) + ( 0.5 × – 0.25 ) = 0.125 – 0.125 = 0.0 MOV MOV MOV MOV MOV MOV MOV NOP NOP NOP MAC0CF, MAC0AH, MAC0AL, MAC0BH, MAC0BL, MAC0BH, MAC0BL, #0Ah #40h #00h #20h #00h #E0h #00h ; Set to Clear Accumulator, Use fractional numbers ; Load MAC0A register with 4000 hex = 0.5 decimal ; ; ; ; Load This Load This MAC0B register line initiates MAC0B register line initiates with 2000 hex = 0.25 decimal the first MAC operation with E000 hex = -0.25 decimal the second MAC operation ; After this instruction, the Accumulator should be equal to 0, ; and the MAC0STA register should be 0x04, indicating a zero ; After this instruction, the Rounding register is updated 120 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 11.7.2. Multiply Only Example The example below implements the equation: 4660 × – 292 = – 1360720 MOV MOV MOV MOV MOV NOP NOP MAC0CF, MAC0AH, MAC0AL, MAC0BH, MAC0BL, #01h #12h #34h #FEh #DCh ; Use integer numbers, and multiply only mode (add to zero) ; Load MAC0A register with 1234 hex = 4660 decimal ; Load MAC0B register with FEDC hex = -292 decimal ; This line initiates the Multiply operation ; ; ; ; After this instruction, the Accumulator should be equal to FFFFEB3CB0 hex = -1360720 decimal. The MAC0STA register should be 0x01, indicating a negative result. After this instruction, the Rounding register is updated NOP 11.7.3. MAC0 Accumulator Shift Example The example below shifts the MAC0 accumulator left one bit, and then right two bits: MOV MOV MOV MOV MOV MOV NOP NOP MOV MOV NOP NOP MAC0OVR, #40h MAC0ACC3, #88h MAC0ACC2, #44h MAC0ACC1, #22h MAC0ACC0, #11h MAC0CF, #20h ; The next few instructions load the accumulator with the value ; 4088442211 Hex. MAC0CF, #30h MAC0CF, #30h ; ; ; ; ; ; ; Initiate a Left-shift After this instruction, the accumulator should be 0x8110884422 The rounding register is updated after this instruction Initiate a Right-shift Initiate a second Right-shift After this instruction, the accumulator should be 0xE044221108 The rounding register is updated after this instruction Rev. 1.0 121 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.1. MAC0CF: MAC0 Configuration SFR Page: 0 SFR Address: 0xD7 R R R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value – Bit7 – Bit6 MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000 Bits 7–6: UNUSED: Read = 00b, Write = don’t care. Bit 5: MAC0SC: Accumulator Shift Control. When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK cycle. The direction of the shift (left or right) is controlled by the MAC0SD bit. This bit is cleared to ‘0’ by hardware when the shift is complete. Bit 4: MAC0SD: Accumulator Shift Direction. This bit controls the direction of the accumulator shift activated by the MAC0SC bit. 0: MAC0 Accumulator will be shifted left. 1: MAC0 Accumulator will be shifted right. Bit 3: MAC0CA: Clear Accumulator. This bit is used to reset MAC0 before the next operation. When set to ‘1’, the MAC0 Accumulator will be cleared to zero and the MAC0 Status register will be reset during the next SYSCLK cycle. This bit will be cleared to ‘0’ by hardware when the reset is complete. Bit 2: MAC0SAT: Saturate Rounding Register. This bit controls whether the Rounding Register will saturate. If this bit is set and a Soft Overflow occurs, the Rounding Register will saturate. This bit does not affect the operation of the MAC0 Accumulator. See Section 11.6 for more details about rounding and saturation. 0: Rounding Register will not saturate. 1: Rounding Register will saturate. Bit 1: MAC0FM: Fractional Mode. This bit selects between Integer Mode and Fractional Mode for MAC0 operations. 0: MAC0 operates in Integer Mode. 1: MAC0 operates in Fractional Mode. Bit 0: MAC0MS: Mode Select This bit selects between MAC Mode and Multiply Only Mode. 0: MAC (Multiply and Accumulate) Mode. 1: Multiply Only Mode. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. 122 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.2. MAC0STA: MAC0 Status SFR Page: 0 SFR Address: 0xCF R R R R R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 – Bit4 MAC0HO Bit3 MAC0Z Bit2 MAC0SO Bit1 MAC0N Bit0 00000100 Bit Addressable Bits 7–4: UNUSED: Read = 0000b, Write = don’t care. Bit 3: MAC0HO: Hard Overflow Flag. This bit is set to ‘1’ whenever an overflow out of the MAC0OVR register occurs during a MAC operation (i.e. when MAC0OVR changes from 0x7F to 0x80 or from 0x80 to 0x7F). The hard overflow flag must be cleared in software by directly writing it to ‘0’, or by resetting the MAC logic using the MAC0CA bit in register MAC0CF. Bit 2: MAC0Z: Zero Flag. This bit is set to ‘1’ if a MAC0 operation results in an Accumulator value of zero. If the result is non-zero, this bit will be cleared to ‘0’. Bit 1: MAC0SO: Soft Overflow Flag. This bit is set to ‘1’ when a MAC operation causes an overflow into the sign bit (bit 31) of the MAC0 Accumulator. If the overflow condition is corrected after a subsequent MAC operation, this bit is cleared to ‘0’. Bit 0: MAC0N: Negative Flag. If the MAC Accumulator result is negative, this bit will be set to ‘1’. If the result is positive or zero, this flag will be cleared to ‘0’. Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.3. MAC0AH: MAC0 A High Byte SFR Page: 0 SFR Address: 0xA5 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: High Byte (bits 15–8) of MAC0 A Register. Rev. 1.0 123 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.4. MAC0AL: MAC0 A Low Byte SFR Page: 0 SFR Address: 0xA4 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Low Byte (bits 7–0) of MAC0 A Register. SFR Definition 11.5. MAC0BH: MAC0 B High Byte SFR Page: 0 SFR Address: 0xF2 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: High Byte (bits 15–8) of MAC0 B Register. SFR Definition 11.6. MAC0BL: MAC0 B Low Byte SFR Page: 0 SFR Address: 0xF1 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Low Byte (bits 7–0) of MAC0 B Register. A write to this register initiates a Multiply or Multiply and Accumulate operation. Note:The contents of this register should not be changed by software during the first MAC0 pipeline stage. 124 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.7. MAC0ACC3: MAC0 Accumulator Byte 3 SFR Page: 0 SFR Address: 0xD5 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Byte 3 (bits 31–24) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.8. MAC0ACC2: MAC0 Accumulator Byte 2 SFR Page: 0 SFR Address: 0xD4 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Byte 2 (bits 23–16) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.9. MAC0ACC1: MAC0 Accumulator Byte 1 SFR Page: 0 SFR Address: 0xD3 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Byte 1 (bits 15–8) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. Rev. 1.0 125 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.10. MAC0ACC0: MAC0 Accumulator Byte 0 SFR Page: 0 SFR Address: 0xD2 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Byte 0 (bits 7–0) of MAC0 Accumulator. Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.11. MAC0OVR: MAC0 Accumulator Overflow SFR Page: 0 SFR Address: 0xD6 R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: MAC0 Accumulator Overflow Bits (bits 39–32). Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 11.12. MAC0RNDH: MAC0 Rounding Register High Byte SFR Page: 0 SFR Address: 0xAF R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: High Byte (bits 15–8) of MAC0 Rounding Register. 126 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 11.13. MAC0RNDL: MAC0 Rounding Register Low Byte SFR Page: 0 SFR Address: 0xAE R Bit7 R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value 00000000 Bits 7–0: Low Byte (bits 7–0) of MAC0 Rounding Register. Rev. 1.0 127 C8051F360/1/2/3/4/5/6/7/8/9 12. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • • • • CIP-51 halts program execution Special Function Registers (SFRs) are initialized to their defined reset values External Port pins are forced to a known state Interrupts and timers are disabled. All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data memory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered. The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator. Refer to Section “16. Oscillators” on page 169 for information on selecting and configuring the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source (Section “22.3. Watchdog Timer Mode” on page 272 details the use of the Watchdog Timer). Program execution begins at location 0x0000. VDD Power On Reset Supply Monitor Px.x Px.x Comparator 0 + C0RSEF + - Enable '0' (wired-OR) /RST Missing Clock Detector (oneshot) EN Reset Funnel PCA WDT (Software Reset) SWRSF EN MCD Enable System Clock CIP-51 Microcontroller Core Extended Interrupt Handler WDT Enable Errant FLASH Operation System Reset Figure 12.1. Reset Sources 128 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 12.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 12.2. plots the power-on and VDD Monitor reset timing. For ramp times less than 1 ms, the power-on reset delay (TPORDelay) is typically less than 0.3 ms. Note: The maximum VDD ramp time is 1 ms; slower ramp times may cause the device to be released from reset before VDD reaches the VRST level. On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic ‘1’. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets). Since all resets cause program execution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be undefined after a power-on reset. The VDD Monitor is enabled following a power-on reset. volts VDD VRST 2.70 2.55 2.0 1.0 VD D t Logic HIGH /RST TPORDelay VDD Monitor Reset Logic LOW Power-On Reset Figure 12.2. Power-On and VDD Monitor Reset Timing Rev. 1.0 129 C8051F360/1/2/3/4/5/6/7/8/9 12.2. Power-Fail Reset/VDD Monitor When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 12.2). When VDD returns to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The VDD Monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. For example, if the VDD Monitor is disabled and a software reset is performed, the VDD Monitor will still be disabled after the reset. To protect the integrity of Flash contents, the VDD Monitor must be enabled and selected as a reset source if software contains routines which erase or write Flash memory. If the VDD Monitor is not enabled, any erase or write performed on Flash memory will cause a Flash Error device reset. The VDD Monitor must be enabled before it is selected as a reset source. Selecting the VDD Monitor as a reset source before it is enabled and stabilized may cause a system reset. The procedure for configuring the VDD Monitor as a reset source is shown below: Step 1. Enable the VDD Monitor (VDMEN bit in VDM0CN = ‘1’). Step 2. Wait for the VDD Monitor to stabilize (approximately 5 µs). Note: This delay should be omitted if software contains routines which erase or write Flash memory. Step 3. Select the VDD Monitor as a reset source (PORSF bit in RSTSRC = ‘1’). See Table 12.1 for complete electrical characteristics of the VDD Monitor. Note: Software should take care not to inadvertently disable the VDD Monitor as a reset source when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source. 130 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 12.1. VDM0CN: VDD Monitor Control SFR Page: all pages SFR Address: 0xFF R/W R Bit6 R Bit5 R Bit4 R Bit3 R Bit2 R Bit1 R Bit0 Reset Value VDMEN Bit7 VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable VDMEN: VDD Monitor Enable. This bit turns the VDD Monitor circuit on/off. The VDD Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC (SFR Definition 12.2). The VDD Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the VDD Monitor as a reset source before it has stabilized may generate a system reset. 0: VDD Monitor Disabled. 1: VDD Monitor Enabled. Bit 6: VDD STAT: VDD Status. This bit indicates the current power supply status (VDD Monitor output). 0: VDD is at or below the VDD Monitor threshold. 1: VDD is above the VDD Monitor threshold. Bits 5–0: RESERVED. Read = Variable. Write = don’t care. Bit 7: 12.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST pin may be necessary to avoid erroneous noise-induced resets. See Table 12.1 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. 12.4. Missing Clock Detector Reset The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise, this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables it. The state of the RST pin is unaffected by this reset. 12.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the noninverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by this reset. Rev. 1.0 131 C8051F360/1/2/3/4/5/6/7/8/9 12.6. PCA Watchdog Timer Reset The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to prevent software from running out of control during a system malfunction. The PCA WDT function can be enabled or disabled by software as described in Section “22.3. Watchdog Timer Mode” on page 272; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to ‘1’. The state of the RST pin is unaffected by this reset. 12.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • • • • • A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX write operation targets an address above address 0x7BFF. A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address above address 0x7BFF. A Program read is attempted above user code space. This occurs when user code attempts to branch to an address above 0x7BFF. A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section “13.2. Security Options” on page 138). A Flash write or erase is attempted while the VDD Monitor is disabled. The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by this reset. 12.8. Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ following a software forced reset. The state of the RST pin is unaffected by this reset. 132 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 12.2. RSTSRC: Reset Source SFR Page: all pages SFR Address: 0xEF R R Bit6 R/W Bit5 R/W R Bit3 R/W Bit2 R/W R Reset Value – Bit7 FERROR C0RSEF SWRSF Bit4 WDTRSF MCDRSF PORSF Bit1 PINRSF Bit0 Variable Note:For bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instructions read and modify the source enable only. [This applies to bits: C0RSEF, SWRSF, MCDRSF, PORSF]. Bit 7: Bit 6: Bit 5: UNUSED. Read = 0b. Write = don’t care. FERROR: Flash Error Indicator. 0: Source of last reset was not a Flash read/write/erase error. 1: Source of last reset was a Flash read/write/erase error. C0RSEF: Comparator0 Reset Enable and Flag. 0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset source. 1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source (active-low). SWRSF: Software Reset Force and Flag. 0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect. 1: Read: Source of last reset was a write to the SWRSF bit. Write: Forces a system reset. WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not a WDT timeout. 1: Source of last reset was a WDT timeout. MCDRSF: Missing Clock Detector Flag. 0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing Clock Detector disabled. 1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. PORSF: Power-On Reset Force and Flag. This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the VDD Monitor as a reset source. Note: writing ‘1’ to this bit before the VDD Monitor is enabled and stabilized may cause a system reset. See register VDM0CN (SFR Definition 12.1) 0: Read: Last reset was not a power-on or VDD Monitor reset. Write: VDD Monitor is not a reset source. 1: Read: Last reset was a power-on or VDD Monitor reset; all other reset flags indeterminate. Write: VDD Monitor is a reset source. PINRSF: HW Pin Reset Flag. 0: Source of last reset was not RST pin. 1: Source of last reset was RST pin. Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: Rev. 1.0 133 C8051F360/1/2/3/4/5/6/7/8/9 Table 12.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter RST Output Low Voltage RST Input High Voltage RST Input Low Voltage RST Input Pullup Impedance VDD POR Threshold (VRST) Missing Clock Detector Timeout Reset Time Delay Minimum RST Low Time to Generate a System Reset VDD Monitor Supply Current Conditions IOL = 8.5 mA, VDD = 2.7 V to 3.6 V Min — 0.7 x VDD — — 2.40 Typ — — — 100 2.55 220 — — 19 Max 0.6 — 0.7 — 2.70 600 — — 40 Units V V V kΩ V µs µs µs µA Time from last system clock rising edge to reset initiation Delay between release of any reset source and code execution at location 0x0000 100 40 15 — 134 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 13. Flash Memory All devices include either 32 kB (C8051F360/1/2/3/4/5/6/7) or 16 kB (C8051F368/9) of on-chip, reprogrammable Flash memory for program code or non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface, or by software using the MOVX write instructions. Once cleared to logic ‘0’, a Flash bit must be erased to set it back to logic ‘1’. Bytes should be erased (set to 0xFF) before being reprogrammed. Flash write and erase operations are automatically timed by hardware for proper execution. During a Flash erase or write, the FLBUSY bit in the FLSTAT register is set to ‘1’ (see SFR Definition 14.5). During this time, instructions that are located in the prefetch buffer or the branch target cache can be executed, but the processor will stall until the erase or write is completed if instruction data must be fetched from Flash memory. Interrupts that have been pre-loaded into the branch target cache can also be serviced at this time, if the current code is also executing from the prefetch engine or cache memory. Any interrupts that are not pre-loaded into cache, or that occur while the core is halted, will be held in a pending state during the Flash write/erase operation, and serviced in priority order once the Flash operation has completed. Refer to Table 13.2 for the electrical characteristics of the Flash memory. 13.1. Programming the Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device. For details on the C2 commands to program Flash memory, see Section “24. C2 Interface” on page 284. For detailed guidelines on writing or erasing Flash from firmware, please see Section “13.3. Flash Write and Erase Guidelines” on page 140. The Flash memory can be programmed from software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic ‘1’. This directs the MOVX writes to Flash memory instead of to XRAM, which is the default target. The PSWE bit remains set until cleared by software. To avoid errant Flash writes, it is recommended that interrupts be disabled while the PSWE bit is logic ‘1’. Flash memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless of the state of PSWE. Note: To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled in any system that includes code that writes and/or erases Flash memory from software. Furthermore, there should be no delay between enabling the VDD Monitor and enabling the VDD Monitor as a reset source. Any attempt to write or erase Flash memory while the VDD Monitor disabled will cause a Flash Error device reset. A write to Flash memory can clear bits but cannot set them; only an erase operation can set bits in Flash. A byte location to be programmed must be erased before a new value can be written. Write/Erase timing is automatically controlled by hardware. Note that on the 32 k Flash devices, 1024 bytes beginning at location 0x7C00 are reserved. Flash writes and erases targeting the reserved area should be avoided. 13.1.1. Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and Rev. 1.0 135 C8051F360/1/2/3/4/5/6/7/8/9 erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly. The Flash lock resets after each write or erase; the key codes must be written again before a following Flash operation can be performed. The FLKEY register is detailed in SFR Definition 13.2. 13.1.2. Erasing Flash Pages From Software The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands. Before writing to Flash memory using MOVX, Flash write operations must be enabled by: (1) the PSWE and PSEE bits must be set to ‘1’ (this directs the MOVX writes to target Flash memory); and (2) Writing the Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared by software. A write to Flash memory can clear bits to logic ‘0’ but cannot set them; only an erase operation can set bits to logic ‘1’ in Flash. A byte location to be programmed should be erased before a new value is written. The Flash memory is organized in 1024-byte pages. The erase operation applies to an entire page (setting all bytes in the page to 0xFF). To erase an entire 1024-byte page, perform the following steps: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Disable interrupts (recommended). Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Set PSEE (PSCTL.1) to enable Flash erases. Set PSWE (PSCTL.0) to redirect MOVX commands to write to Flash. Use the MOVX instruction to write a data byte to any location within the page to be erased. Step 7. Clear PSEE to disable Flash erases. Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 9. Re-enable interrupts. 13.1.3. Writing Flash Memory From Software Bytes in Flash memory can be written one byte at a time, or in small blocks. The CHBLKW bit in register CCH0CN (SFR Definition 14.1) controls whether a single byte or a block of bytes is written to Flash during a write operation. When CHBLKW is cleared to ‘0’, the Flash will be written one byte at a time. When CHBLKW is set to ‘1’, the Flash will be written in blocks of four bytes for addresses in code space. Block writes are performed in the same amount of time as single byte writes, which can save time when storing large amounts of data to Flash memory. For single-byte writes to Flash, bytes are written individually, and the Flash write is performed after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is as follows: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. Disable interrupts. Clear CHBLKW (register CCH0CN) to select single-byte write mode. Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Set PSWE (register PSCTL) to redirect MOVX commands to write to Flash. Clear the PSEE bit (register PSCTL). Use the MOVX instruction to write a data byte to the desired location (repeat as necessary). Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 9. Re-enable interrupts. 136 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Steps 3–8 must be repeated for each byte to be written For block Flash writes, the Flash write procedure is only performed after the last byte of each block is written with the MOVX write instruction. When writing to addresses located in any of the four code banks, a Flash write block is four bytes long, from addresses ending in 00b to addresses ending in 11b. Writes must be performed sequentially (i.e. addresses ending in 00b, 01b, 10b, and 11b must be written in order). The Flash write will be performed following the MOVX write that targets the address ending in 11b. The Flash write will be performed following the MOVX write that targets the address ending in 1b. If any bytes in the block do not need to be updated in Flash, they should be written to 0xFF. The recommended procedure for writing Flash in blocks is as follows: Disable interrupts. Set CHBLKW (register CCH0CN) to select block write mode. Write the first key code to FLKEY: 0xA5. Write the second key code to FLKEY: 0xF1. Set PSWE (register PSCTL) to redirect MOVX commands to write to Flash. Clear the PSEE bit (register PSCTL). Using the MOVX instruction, write the first data byte to the first block location (ending in 00b). Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 9. Write the first key code to FLKEY: 0xA5. Step 10. Write the second key code to FLKEY: 0xF1. Step 11. Set PSWE (register PSCTL) to redirect MOVX commands to write to Flash. Step 12. Clear the PSEE bit (register PSCTL). Step 13. Using the MOVX instruction, write the second data byte to the second block location (ending in 01b). Step 14. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 15. Write the first key code to FLKEY: 0xA5. Step 16. Write the second key code to FLKEY: 0xF1. Step 17. Set PSWE (register PSCTL) to redirect MOVX commands to write to Flash. Step 18. Clear the PSEE bit (register PSCTL). Step 19. Using the MOVX instruction, write the third data byte to the third block location (ending in 10b). Step 20. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 21. Write the first key code to FLKEY: 0xA5. Step 22. Write the second key code to FLKEY: 0xF1. Step 23. Set PSWE (register PSCTL) to redirect MOVX commands to write to Flash. Step 24. Clear the PSEE bit (register PSCTL). Step 25. Using the MOVX instruction, write the fourth data byte to the last block location (ending in 11b). Step 26. Clear the PSWE bit to redirect MOVX commands to the XRAM data space. Step 27. Re-enable interrupts. Steps 3-26 must be repeated for each block to be written. Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Step 7. 13.1.4. Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written and erased using the MOVX write instruction (as described in Section 13.1.2 and Section 13.1.3) and read using the MOVC instruction. Note: MOVX read instructions always target XRAM. Rev. 1.0 137 C8051F360/1/2/3/4/5/6/7/8/9 13.2. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before software can erase Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface. A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security mechanism allows the user to lock n 1024-byte Flash pages, starting at page 0 (addresses 0x0000 to 0x03FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked (all bits of the Lock Byte are ‘1’) and locked when any other Flash pages are locked (any bit of the Lock Byte is ‘0’). See the example below for an C8051F360. Security Lock Byte: 1’s Complement: Flash pages locked: Addresses locked: 11111101b 00000010b 3 (First two Flash pages + Lock Byte Page) 0x0000 to 0x07FF (first two Flash pages) and 0x7800 to 0x7BFF (Lock Byte Page) 'F368/9 R eserved 0x4000 ‘F360/1/2/3/4/5/6/7 R eserved 0x7C00 0x7BFF 0x7BFE 0x7800 Lock Byte Locked when any other Flash pages are locked Lock Byte 0x3FFF 0x3FFE 0x3C00 Unlocked Flash Pages Access limit set according to the Flash security lock byte Unlocked Flash Pages Flash memory organized in 1024-byte pages 0x0000 0x0000 Figure 13.1. Flash Program Memory Map 138 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 13.2.1. Summary of Flash Security Options The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security features of the C8051F36x devices. Table 13.1. Flash Security Summary Action C2 Debug Interface Permitted Not Permitted Permitted Not Permitted Permitted Not Permitted Permitted Only C2DE Not Permitted Not Permitted Not Permitted User Firmware executing from: an unlocked page Permitted FEDR Permitted FEDR Permitted FEDR FEDR FEDR FEDR FEDR FEDR a locked page Permitted Permitted Permitted Permitted Permitted Permitted FEDR FEDR FEDR FEDR FEDR Read, Write or Erase unlocked pages (except page with Lock Byte) Read, Write or Erase locked pages (except page with Lock Byte) Read or Write page containing Lock Byte (if no pages are locked) Read or Write page containing Lock Byte (if any page is locked) Read contents of Lock Byte (if no pages are locked) Read contents of Lock Byte (if any page is locked) Erase page containing Lock Byte (if no pages are locked) Erase page containing Lock Byte - Unlock all pages (if any page is locked) Lock additional pages (change '1's to '0's in the Lock Byte) Unlock individual pages (change '0's to '1's in the Lock Byte) Read, Write or Erase Reserved Area C2DE - C2 Device Erase (Erases all Flash pages including the page containing the Lock Byte) FEDR - Not permitted; Causes Flash Error Device Reset (FERROR bit in RSTSRC is '1' after reset) - All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset). - Locking any Flash page also locks the page containing the Lock Byte. - Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase. - If user code writes to the Lock Byte, the Lock does not take effect until the next device reset. Rev. 1.0 139 C8051F360/1/2/3/4/5/6/7/8/9 13.3. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modifying code can result in alteration of Flash memory contents causing a system failure that is only recoverable by re-Flashing the code in the device. To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and enabled as a reset source on C8051F36x devices for the Flash to be successfully modified. If either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset will be generated when the firmware attempts to modify the Flash. The following guidelines are recommended for any system that contains routines which write or erase Flash from code. 13.3.1. VDD Maintenance and the VDD Monitor 1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings table are not exceeded. 2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet this rise time specification, then add an external VDD brownout circuit to the /RST pin of the device that holds the device in reset until VDD reaches VRST and re-asserts /RST if VDD drops below VRST. Please see Table 12.1, “Reset Electrical Characteristics,” on page 134 for more information on the VDD Monitor Threshold voltage (VRST). 3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-based systems, this will involve modifying the startup code added by the 'C' compiler. See your compiler documentation for more details. Make certain that there are no delays in software between enabling the VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. Note: On C8051F36x devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write or erase Flash without generating a Flash Error Device Reset. 4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions should be placed just after the instruction to set PSWE to a '1', but before the Flash write or erase operation instruction. 5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect. 6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas to check are initialization code which enables other reset sources, such as the Missing Clock Detector or Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC" can quickly verify this. 140 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 13.3.2. 16.4.2 PSWE Maintenance 7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one routine in code that sets both PSWE and PSEE both to a '1' to erase Flash pages. 8. Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address updates and loop maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code examples showing this can be found in AN201, "Writing to Flash from Firmware", available from the Silicon Laboratories web site. 9. Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has been reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority order after the Flash operation has been completed and interrupts have been re-enabled by software. 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions regarding how to explicitly locate variables in different memory areas. 11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine called with an illegal address does not result in modification of the Flash. 13.3.3. System Clock 12. If operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. If the system is operating in an electrically noisy environment, use the internal oscillator or use an external CMOS clock. 13. If operating from the external oscillator, switch to the internal oscillator during Flash write or erase operations. The external oscillator can continue to run, and the CPU can switch back to the external oscillator after the Flash operation has completed. Rev. 1.0 141 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 13.1. PSCTL: Program Store Read/Write Control SFR Page: 0 SFR Address: 0x8F R/W R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 – Bit4 – Bit3 – Bit2 PSEE Bit1 PSWE Bit0 00000000 Bits 7–2: UNUSED. Read = 000000b, Write = don't care. Bit 1: PSEE: Program Store Erase Enable. Setting this bit allows an entire page of the Flash program memory to be erased provided the PSWE bit is also set. After setting this bit, a write to Flash memory using the MOVX instruction will erase the entire page that contains the location addressed by the MOVX instruction. The value of the data byte written does not matter. Note: The Flash page containing the Read Lock Byte and Write/Erase Lock Byte cannot be erased by software. 0: Flash program memory erasure disabled. 1: Flash program memory erasure enabled. Bit 0: PSWE: Program Store Write Enable. Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction. The location must be erased prior to writing data. 0: Write to Flash program memory disabled. MOVX write operations target External RAM. 1: Write to Flash program memory enabled. MOVX write operations target Flash memory. SFR Definition 13.2. FLKEY: Flash Lock and Key SFR Page: 0 SFR Address: 0xB7 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: FLKEY: Flash Lock and Key Register Write: This register provides a lock and key function for Flash erasures and writes. Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. Flash writes and erases are automatically disabled after the next write or erase is complete. If any writes to FLKEY are performed incorrectly, or if a Flash write or erase operation is attempted while these operations are disabled, the Flash will be permanently locked from writes or erasures until the next device reset. If an application never writes to Flash, it can intentionally lock the Flash by writing a non-0xA5 value to FLKEY from software. Read: When read, bits 1-0 indicate the current Flash lock state. 00: Flash is write/erase locked. 01: The first key code has been written (0xA5). 10: Flash is unlocked (writes/erases allowed). 11: Flash writes/erases disabled until the next reset. 142 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 13.4. Flash Read Timing On reset, the C8051F36x Flash read timing is configured for operation with system clocks up to 25 MHz. If the system clock will not be increased above 25 MHz, then the Flash timing registers may be left at their reset value. For every Flash read or fetch, the system provides an internal Flash read strobe to the Flash memory. The Flash read strobe lasts for one or two system clock cycles, based on the FLRT bits (FLSCL.4 and FLSCL.5). If the system clock is greater than 25 MHz, the FLRT bit must be changed to the appropriate setting. Otherwise, data read or fetched from Flash may not represent the actual contents of Flash. When the Flash read strobe is asserted, Flash memory is active. When it is de-asserted, Flash memory is in a low power state. The recommended procedure for updating FLRT is: Step 1. Step 2. Step 3. Step 4. Select SYSCLK to 25 MHz or less. Disable the prefetch engine (CHPFEN = ‘0’ in CCH0CN register). Set the FLRT bits to the appropriate setting for the SYSCLK. Enable the prefetch engine (CHPFEN = ‘1’ in CCH0CN register). SFR Definition 13.3. FLSCL: Flash Memory Control SFR Page: 0 SFR Address: 0xB6 R/W R/W R/W R/W R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value – Bit7 – Bit6 Bit5 FLRT Bit4 Reserved Reserved Reserved Reserved 00000000 Bits 7–6: UNUSED. Read = 00b. Write = don’t care. Bits 5–4: FLRT: Flash Read Time. These bits should be programmed to the smallest allowed value, according to the system clock speed. 00: SYSCLK < 25 MHz. 01: SYSCLK < 50 MHz. 10: SYSCLK < 75 MHz. 11: SYSCLK < 100 MHz. Bits 3–0: RESERVED. Read = 0000b. Must Write 0000b. Important Note: When changing the FLRT bits to a lower setting (e.g. when changing from a value of 11b to 00b), cache reads, cache writes, and the prefetch engine should be disabled using the CCH0CN register (see SFR Definition 14.1). Rev. 1.0 143 C8051F360/1/2/3/4/5/6/7/8/9 Table 13.2. Flash Electrical Characteristics VDD = 2.7 to 3.6 V; –40 to +85 °C. Parameter Flash Size Endurance Erase Cycle Time Write Cycle Time *Note: 1024 Bytes at location 0x7C00 to 0x7FFF are reserved. Conditions C8051F360/1/2/3/4/5/6/7 C8051F368/9 Min 20 k 8 37 Typ 32768* 16384 250 k 10 47 Max Units Bytes Erase/Write 12 57 ms µs 144 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 14. Branch Target Cache The C8051F36x device families incorporate a 32x4 byte branch target cache with a 4-byte prefetch engine. Because the access time of the Flash memory is 40 ns, and the minimum instruction time is 10 ns (C8051F360/1/2/3/4/5/6/7) or 20 ns (C8051F368/9), the branch target cache and prefetch engine are necessary for full-speed code execution. Instructions are read from Flash memory four bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine alone allows instructions to be executed at full speed. When a code branch occurs, a search is performed for the branch target (destination address) in the cache. If the branch target information is found in the cache (called a “cache hit”), the instruction data is read from the cache and immediately returned to the CIP-51 with no delay in code execution. If the branch target is not found in the cache (called a “cache miss”), the processor may be stalled for up to four clock cycles while the next set of four instructions is retrieved from Flash memory. Each time a cache miss occurs, the requested instruction data is written to the cache if allowed by the current cache settings. A data flow diagram of the interaction between the CIP-51 and the Branch Target Cache and Prefetch Engine is shown in Figure 14.1. Instruction Data CIP-51 Flash Memory Prefetch Engine Branch Target Cache Instruction Address Figure 14.1. Branch Target Cache Data Flow 14.1. Cache and Prefetch Operation The branch target cache maintains two sets of memory locations: “slots” and “tags”. A slot is where the cached instruction data from Flash is stored. Each slot holds four consecutive code bytes. A tag contains the 13 most significant bits of the corresponding Flash address for each four-byte slot. Thus, instruction data is always cached along four-byte boundaries in code space. A tag also contains a “valid bit”, which indicates whether a cache location contains valid instruction data. A special cache location (called the linear tag and slot), is reserved for use by the prefetch engine. The cache organization is shown in Figure 14.2. Each time a Flash read is requested, the address is compared with all valid cache tag locations (including the linear tag). If any of the tag locations match the requested address, the data from that slot is immediately provided to the CIP-51. If the requested address matches a location that is currently being read by the prefetch engine, the CIP-51 will be stalled until the read is complete. If a match is not found, the current prefetch operation is abandoned, and a new prefetch operation is initiated for the requested instruction data. When the prefetch operation is finished, the CIP-51 begins executing the instructions that were retrieved, and the prefetch engine begins reading the next four-byte word from Flash memory. If the newly-fetched data also meets the criteria necessary to be cached, it will be written to the cache in the slot indicated by the current replacement algorithm. Rev. 1.0 145 C8051F360/1/2/3/4/5/6/7/8/9 The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When CHALGM is cleared to ‘0’, the cache will use the rebound algorithm to replace cache locations. The rebound algorithm replaces locations in order from the beginning of cache memory to the end, and then from the end of cache memory to the beginning. When CHALGM is set to ‘1’, the cache will use the pseudo-random algorithm to replace cache locations. The pseudo-random algorithm uses a pseudo-random number to determine which cache location to replace. The cache can be manually emptied by writing a ‘1’ to the CHFLUSH bit (CCH0CN.4). Valid Bit Prefetch Data VL V0 V1 V2 Address LINEAR TAG TAG 0 TAG 1 TAG 2 Data LINEAR SLOT SLOT 0 SLOT 1 SLOT 2 Cache Data V27 V28 V29 V30 V31 TAG 27 TAG 28 TAG 29 TAG 30 TAG 31 SLOT 27 SLOT 28 SLOT 29 SLOT 30 SLOT 31 A14 A2 A1 A0 0 0 1 0 1 Byte 0 Byte 1 Byte 2 Byte 3 S LOT = 4 Instruction Data Bytes TAG = 13 MSBs of Absolute FLASH Address 0 1 1 Figure 14.2. Branch Target Cache Organization 14.2. Cache and Prefetch Optimization By default, the branch target cache is configured to provide code speed improvements for a broad range of circumstances. In most applications, the cache control registers should be left in their reset states. Sometimes it is desirable to optimize the execution time of a specific routine or critical timing loop. The branch target cache includes options to exclude caching of certain types of data, as well as the ability to pre-load and lock time-critical branch locations to optimize execution speed. The most basic level of cache control is implemented with the Cache Miss Penalty Threshold bits, CHMSTH (CCH0TN.1–0). If the processor is stalled during a prefetch operation for more clock cycles than the number stored in CHMSTH, the requested data will be cached when it becomes available. The CHMSTH bits are set to zero by default, meaning that any time the processor is stalled, the new data will be cached. If, for example, CHMSTH is equal to 2, any cache miss causing a delay of 3 or 4 clock cycles will be cached, while a cache miss causing a delay of 1–2 clock cycles will not be cached. 146 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Certain types of instruction data or certain blocks of code can also be excluded from caching. The destinations of RETI instructions are, by default, excluded from caching. To enable caching of RETI destinations, the CHRETI bit (CCH0CN.3) can be set to ‘1’. It is generally not beneficial to cache RETI destinations unless the same instruction is likely to be interrupted repeatedly (such as a code loop that is waiting for an interrupt to happen). Instructions that are part of an interrupt service routine (ISR) can also be excluded from caching. By default, ISR instructions are cached, but this can be disabled by clearing the CHISR bit (CCH0CN.2) to ‘0’. The other information that can be explicitly excluded from caching are the data returned by MOVC instructions. Clearing the CHMOV bit (CCH0CN.1) to ‘0’ will disable caching of MOVC data. If MOVC caching is allowed, it can be restricted to only use slot 0 for the MOVC information (excluding cache push operations). The CHFIXM bit (CCH0TN.2) controls this behavior. Further cache control can be implemented by disabling all cache writes. Cache writes can be disabled by clearing the CHWREN bit (CCH0CN.7) to ‘0’. Although normal cache writes (such as those after a cache miss) are disabled, data can still be written to the cache with a cache push operation. Disabling cache writes can be used to prevent a non-critical section of code from changing the cache contents. Note that regardless of the value of CHWREN, a Flash write or erase operation automatically removes the affected bytes from the cache. Cache reads and the prefetch engine can also be individually disabled. Disabling cache reads forces all instructions data to execute from Flash memory or from the prefetch engine. To disable cache reads, the CHRDEN bit (CCH0CN.6) can be cleared to ‘0’. Note that when cache reads are disabled, cache writes will still occur (if CHWREN is set to ‘1’). Disabling the prefetch engine is accomplished using the CHPFEN bit (CCH0CN.5). When this bit is cleared to ‘0’, the prefetch engine will be disabled. If both CHPFEN and CHRDEN are ‘0’, code will execute at a fixed rate, as instructions become available from the Flash memory. Cache locations can also be pre-loaded and locked with time-critical branch destinations. For example, in a system with an ISR that must respond as fast as possible, the entry point for the ISR can be locked into a cache location to minimize the response latency of the ISR. Up to 30 locations can be locked into the cache at one time. Instructions are locked into cache by enabling cache push operations with the CHPUSH bit (CCH0LC.7). When CHPUSH is set to ‘1’, a MOVC instruction will cause the four-byte segment containing the data byte to be written to the cache slot location indicated by CHSLOT (CCH0LC.4-0). CHSLOT is them decremented to point to the next lockable cache location. This process is called a cache push operation. Cache locations that are above CHSLOT are “locked”, and cannot be changed by the processor core, as shown in Figure 14.3. Cache locations can be unlocked by using a cache pop operation. A cache pop is performed by writing a ‘1’ to the CHPOP bit (CCH0LC.6). When a cache pop is initiated, the value of CHSLOT is incremented. This unlocks the most recently locked cache location, but does not remove the information from the cache. Note that a cache pop should not be initiated if CHSLOT is equal to 11110b. Doing so may have an adverse effect on cache performance. Important: Although locking cache location 1 is not explicitly disabled by hardware, the entire cache will be unlocked when CHSLOT is equal to 00000b. Therefore, cache locations 1 and 0 must remain unlocked at all times. Rev. 1.0 147 C8051F360/1/2/3/4/5/6/7/8/9 Lock Status TAG 0 TAG 1 Cache Push Operations Decrement CHSLOT TAG 2 SLOT 0 SLOT 1 SLOT 2 UNLOCKED UNLOCKED UNLOCKED UNLOCKED TAG 26 CHSLOT = 27 TAG 27 TAG 28 Cache Pop Operations Increment CHSLOT TAG 29 TAG 30 T AG 31 SLOT 26 SLOT 27 SLOT 28 SLOT 29 SLOT 30 SLOT 31 UNLOCKED UNLOCKED LOCKED LOCKED LOCKED LOCKED Figure 14.3. Cache Lock Operation 148 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.1. CCH0CN: Cache Control SFR Page: F SFR Address: 0x84 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W R/W R/W Bit1 R/W Bit0 Reset Value CHWREN CHRDEN CHPFEN CHFLSH Bit 7: CHRETI Bit3 CHISR Bit2 CHMOVC CHBLKW 11100110 Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: CHWREN: Cache Write Enable. This bit enables the processor to write to the cache memory. 0: Cache contents are not allowed to change, except during Flash writes/erasures or cache locks. 1: Writes to cache memory are allowed. CHRDEN: Cache Read Enable. This bit enables the processor to read instructions from the cache memory. 0: All instruction data comes from Flash memory or the prefetch engine. 1: Instruction data is obtained from cache (when available). CHPFEN: Cache Prefetch Enable. This bit enables the prefetch engine. 0: Prefetch engine is disabled. 1: Prefetch engine is enabled. CHFLSH: Cache Flush. When written to a ‘1’, this bit clears the cache contents. This bit always reads ‘0’. CHRETI: Cache RETI Destination Enable. This bit enables the destination of a RETI address to be cached. 0: Destinations of RETI instructions will not be cached. 1: RETI destinations will be cached. CHISR: Cache ISR Enable. This bit allows instructions which are part of an Interrupt Service Routine (ISR) to be cached. 0: Instructions in ISRs will not be loaded into cache memory. 1: Instructions in ISRs can be cached. CHMOVC: Cache MOVC Enable. This bit allows data requested by a MOVC instruction to be loaded into the cache memory. 0: Data requested by MOVC instructions will not be cached. 1: Data requested by MOVC instructions will be loaded into cache memory. CHBLKW: Block Write Enable. This bit allows block writes to Flash memory from software. 0: Each byte of a software Flash write is written individually. 1: Flash bytes are written in groups of four (for code space writes). Rev. 1.0 149 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.2. CCH0TN: Cache Tuning SFR Page: F SFR Address: 0xC9 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value CHMSCTL CHALGM CHFIXM CHMSTH 00000100 Bits 7–4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4–1). These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first be latched by reading the CHMSCTH bits in the CCH0MA Register (See SFR Definition 14.4). Bit 3: CHALGM: Cache Algorithm Select. This bit selects the cache replacement algorithm. 0: Cache uses Rebound algorithm. 1: Cache uses Pseudo-random algorithm. Bit 2: CHFIXM: Cache Fix MOVC Enable. This bit forces MOVC writes to the cache memory to use slot 0. 0: MOVC data is written according to the current algorithm selected by the CHALGM bit. 1: MOVC data is always written to cache slot 0. Bits 1–0: CHMSTH: Cache Miss Penalty Threshold. These bits determine when missed instruction data will be cached. If data takes longer than CHMSTH clocks to obtain, it will be cached. 150 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.3. CCH0LC: Cache Lock Control SFR Page: F SFR Address: 0xD2 R/W R/W Bit6 R Bit5 R Bit4 R Bit3 R R Bit1 R Bit0 Reset Value CHPUSH Bit7 CHPOP RESERVED CHSLOT Bit2 00011111 Bit 7: CHPUSH: Cache Push Enable. This bit enables cache push operations, which will lock information in cache slots using MOVC instructions. 0: Cache push operations are disabled. 1: Cache push operations are enabled. When a MOVC read is executed, the requested 4byte segment containing the data is locked into the cache at the location indicated by CHSLOT, and CHSLOT is decremented. Note:No more than 30 cache slots should be locked at one time, since the entire cache will be unlocked when CHSLOT is equal to 0. Bit 6: CHPOP: Cache Pop. Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT = 11110b. “Pop”ing more Cache slots than have been “Push”ed will have indeterminate results on the Cache performance. Bit 5: RESERVED. Read = 0b. Must Write 0b. Bits 4–0: CHSLOT: Cache Slot Pointer. These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are locked, and will not be changed by the processor, except when CHSLOT equals 0. Rev. 1.0 151 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 14.4. CCH0MA: Cache Miss Accumulator SFR Page: F SFR Address: 0xD3 R R/W Bit6 R/W Bit5 R/W Bit4 R/W R/W Bit2 R/W Bit1 R/W Bit0 Reset Value CHMSOV Bit7 CHMSCTH Bit3 00000000 Bit 7: CHMSOV: Cache Miss Penalty Overflow. This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was last written. 0: The Cache Miss Penalty Accumulator has not overflowed since it was last written. 1: An overflow of the Cache Miss Penalty Accumulator has occurred since it was last written. Bits 6–0: CHMSCTH: Cache Miss Penalty Accumulator (bits 11–5) These are bits 11-5 of the Cache Miss Penalty Accumulator. The next four bits (bits 4-1) are stored in CHMSCTL in the CCH0TN register. The Cache Miss Penalty Accumulator is incremented every clock cycle that the processor is delayed due to a cache miss. This is primarily used as a diagnostic feature, when optimizing code for execution speed. Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator. Reading from CHMSCTH returns the current value of CHMSTCH, and latches bits 4-1 into CHMSTCL so that they can be read. Because bit 0 of the Cache Miss Penalty Accumulator is not available, the Cumulative Miss Penalty is equal to 2 * (CCHMSTCH:CCHMSTCL). SFR Definition 14.5. FLSTAT: Flash Status SFR Page: F SFR Address: 0xAC R Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value Reserved Reserved Reserved Reserved Reserved Reserved Reserved FLBUSY 00000000 Bit 7–1: Bit 0: RESERVED. Read = 0000000b. Must Write 0000000b. FLBUSY: Flash Busy This bit indicates when a Flash write or erase operation is in progress. 0: Flash is idle or reading. 1: Flash write/erase operation is currently in progress. 152 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15. External Data Memory Interface and On-Chip XRAM For C8051F36x devices, 1k Bytes of RAM are included on-chip and mapped into the external data memory space (XRAM). Additionally, an External Memory Interface (EMIF) is available on the C8051F360/3 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN, shown in SFR Definition 15.1). Note: the MOVX instruction can also be used for writing to the FLASH memory. See Section “13. Flash Memory” on page 135 for details. The MOVX instruction accesses XRAM by default. 15.1. Accessing XRAM The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which contains the effective address of the XRAM location to be read from or written to. The second method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM address. Examples of both of these methods are given below. 15.1.1. 16-Bit MOVX Example The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A: MOV MOVX DPTR, #1234h A, @DPTR ; load DPTR with 16-bit address to read (0x1234) ; load contents of 0x1234 into accumulator A The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately, the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains the lower 8-bits of DPTR. 15.1.2. 8-Bit MOVX Example The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A. MOV MOV MOVX EMI0CN, #12h R0, #34h a, @R0 ; load high byte of address into EMI0CN ; load low byte of address into R0 (or R1) ; load contents of 0x1234 into accumulator A Rev. 1.0 153 C8051F360/1/2/3/4/5/6/7/8/9 15.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps: 1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is most common), and skip the associated pins in the crossbar. 2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic ‘1’). 3. Select Multiplexed mode or Non-multiplexed mode. 4. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 5. Set up timing to interface with off-chip memory or peripherals. Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed mode selection, and Mode bits are located in the EMI0CF register shown in SFR Definition 15.2. 15.3. Port Configuration The External Memory Interface appears on Ports 1, 2 (non-multiplexed mode only), 3, and 4 when it is used for off-chip memory access. When the EMIF is used in multiplexed mode, the Crossbar should be configured to skip over the ALE control line (P0.0) using the P0SKIP register. The other control lines, /RD (P4.4) and /WR (P4.5), are not available on the Crossbar and do not need to be skipped. For more information about configuring the Crossbar, see Section “17.3. General Purpose Port I/O” on page 190. The EMIF pinout is shown in Table 15.1 on page 155. The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “17. Port Input/Output” on page 183 for more information about the Crossbar and Port operation and configuration. The Port latches should be explicitly configured to ‘park’ the External Memory Interface pins in a dormant state, most commonly by setting them to a logic ‘1’. During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be configured for push-pull mode. 154 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 15.1. EMIF Pinout (C8051F360/3) Multiplexed Mode Signal Name /RD /WR ALE D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/A7 A8 A9 A10 A11 A12 A13 A14 A15 – – – – – – – – Port Pin P4.4 P4.5 P0.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 – – – – – – – – Non Multiplexed Mode Signal Name /RD /WR ALE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Port Pin P4.4 P4.5 P0.0 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 SFR Definition 15.1. EMI0CN: External Memory Interface Control SFR Page: all pages SFR Address: 0xAA R/W R/W R/W R/W R/W R/W R/W R/W Bit0 Reset Value PGSEL7 Bit7 PGSEL6 Bit6 PGSEL5 Bit5 PGSEL4 Bit4 PGSEL3 Bit3 PGSEL2 Bit2 PGSEL1 Bit1 PGSEL0 00000000 Bits 7–0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM. 0x00: 0x0000 to 0x00FF 0x01: 0x0100 to 0x01FF ... 0xFE: 0xFE00 to 0xFEFF 0xFF: 0xFF00 to 0xFFFF Rev. 1.0 155 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 15.2. EMI0CF: External Memory Configuration SFR Page: F SFR Address: 0xC7 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 EMD2 Bit4 EMD1 Bit3 EMD0 Bit2 EALE1 Bit1 EALE0 Bit0 00000011 Bits 7–5: UNUSED. Read = 000b. Write = don’t care. Bit 4: EMD2: EMIF Multiplex Mode Select. 0: EMIF operates in multiplexed address/data mode. 1: EMIF operates in non-multiplexed mode (separate address and data pins). Bits 3–2: EMD1–0: EMIF Operating Mode Select. These bits control the operating mode of the External Memory Interface. 00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip memory space. 01: Split Mode without Bank Select: Accesses below the 1 k boundary are directed on-chip. Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte. Note that in order to access off-chip space, EMI0CN must be set to a page that is not contained in the on-chip address space. 10: Split Mode with Bank Select: Accesses below the 1 k boundary are directed on-chip. Accesses above the 1 k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of EMI0CN to determine the high-byte of the address. 11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU. Bits 1–0: EALE1–0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0). 00: ALE high and ALE low pulse width = 1 SYSCLK cycle. 01: ALE high and ALE low pulse width = 2 SYSCLK cycles. 10: ALE high and ALE low pulse width = 3 SYSCLK cycles. 11: ALE high and ALE low pulse width = 4 SYSCLK cycles. 156 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 15.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The external latch is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Interface logic. An example of a Multiplexed Configuration is shown in Figure 15.1. In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state of the ALE signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During this phase, the address latch is configured such that the ‘Q’ outputs reflect the states of the ‘D’ inputs. When ALE falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. Later in the second phase, the Data Bus controls the state of the AD[7:0] port at the time /RD or /WR is asserted. See Section “15.6.2. Multiplexed Mode” on page 165 for more information. A[15:8] ADDRESS BUS 74HC373 G ADDRESS/DATA BUS VDD D Q A[15:8] E M I F ALE AD[7:0] A[7:0] 64 K X 8 SRAM I/O[7:0] CE WE OE (Optional) 8 /WR /RD Figure 15.1. Multiplexed Configuration Example Rev. 1.0 157 C8051F360/1/2/3/4/5/6/7/8/9 15.4.2. Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 15.2. See Section “15.6.1. Non-multiplexed Mode” on page 162 for more information about Non-multiplexed operation. E M I F A[15:0] ADDRESS BUS VDD A[15:0] (Optional) 8 D[7:0] /WR /RD DATA BUS 64 K X 8 SRAM I/O[7:0] CE WE OE Figure 15.2. Non-multiplexed Configuration Example 158 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 15.3, based on the EMIF Mode bits in the EMI0CF register (SFR Definition 15.2). These modes are summarized below. More information about the different modes can be found in Section “15.6. Timing” on page 160. EMI0CF[3:2] = 00 0xFFFF On-Chip XRAM EMI0CF[3:2] = 01 0xFFFF EMI0CF[3:2] = 10 0xFFFF EMI0CF[3:2] = 11 0xFFFF On-Chip XRAM Off-Chip Memory (No Bank Select) Off-Chip Memory (Bank Select) Off-Chip Memory On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM 0x0000 0x0000 0x0000 0x0000 On-Chip XRAM Figure 15.3. EMIF Operating Modes 15.5.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap on 1k boundaries. As an example, the addresses 0x0400 and 0x1000 both evaluate to address 0x0000 in on-chip XRAM space. • • 8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0 or R1 to determine the low-byte of the effective address. 16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address. 15.5.2. Split Mode without Bank Select When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. Effective addresses above the internal XRAM size boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-chip. However, in the “No Bank Select” mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8] of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly via the port latches. This behavior is in contrast with “Split Mode with Bank Select” described below. The lower 8-bits of the Address Bus A[7:0] are driven, determined by R0 or R1. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. • Rev. 1.0 159 C8051F360/1/2/3/4/5/6/7/8/9 15.5.3. Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • • • Effective addresses below the internal XRAM size boundary will access on-chip XRAM space. Effective addresses above the internal XRAM size boundary will access off-chip space. 8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank Select” mode. 16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. • 15.5.4. External Only When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visible to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the internal XRAM size boundary. • 8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identical behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective address A[7:0] are determined by the contents of R0 or R1. 16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction. • 15.6. Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements. The Address Setup time, Address Hold time, / RD and /WR strobe widths, and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through EMI0TC, shown in SFR Definition 15.3, and EMI0CF[1:0]. The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 for /ALE + 1 for /RD or /WR + 4). The programmable setup and hold times default to the maximum delay settings after a reset. Table 15.2 lists the AC parameters for the External Memory Interface, and Figure 15.4 through Figure 15.9 show the timing diagrams for the different External Memory Interface modes and MOVX operations. 160 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 15.3. EMI0TC: External Memory Timing Control SFR Page: F SFR Address: 0xF7 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EAS1 Bit7 EAS0 Bit6 ERW3 Bit5 EWR2 Bit4 EWR1 Bit3 EWR0 Bit2 EAH1 Bit1 EAH0 Bit0 11111111 Bits 7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. 11: Address setup time = 3 SYSCLK cycles. Bits 5–2: EWR3–0: EMIF /WR and /RD Pulse-Width Control Bits. 0000: /WR and /RD pulse width = 1 SYSCLK cycle. 0001: /WR and /RD pulse width = 2 SYSCLK cycles. 0010: /WR and /RD pulse width = 3 SYSCLK cycles. 0011: /WR and /RD pulse width = 4 SYSCLK cycles. 0100: /WR and /RD pulse width = 5 SYSCLK cycles. 0101: /WR and /RD pulse width = 6 SYSCLK cycles. 0110: /WR and /RD pulse width = 7 SYSCLK cycles. 0111: /WR and /RD pulse width = 8 SYSCLK cycles. 1000: /WR and /RD pulse width = 9 SYSCLK cycles. 1001: /WR and /RD pulse width = 10 SYSCLK cycles. 1010: /WR and /RD pulse width = 11 SYSCLK cycles. 1011: /WR and /RD pulse width = 12 SYSCLK cycles. 1100: /WR and /RD pulse width = 13 SYSCLK cycles. 1101: /WR and /RD pulse width = 14 SYSCLK cycles. 1110: /WR and /RD pulse width = 15 SYSCLK cycles. 1111: /WR and /RD pulse width = 16 SYSCLK cycles. Bits 1–0: EAH1–0: EMIF Address Hold Time Bits. 00: Address hold time = 0 SYSCLK cycles. 01: Address hold time = 1 SYSCLK cycle. 10: Address hold time = 2 SYSCLK cycles. 11: Address hold time = 3 SYSCLK cycles. Rev. 1.0 161 C8051F360/1/2/3/4/5/6/7/8/9 15.6.1. Non-multiplexed Mode 15.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Nonmuxed 16-bit WRITE ADDR[15:8] ADDR[7:0] DATA[7:0] P3.4–P4.3 P2 P1 T T /WR /RD P4.5 P4.4 ACS EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL EMIF WRITE DATA WDS P3.4–P4.3 P2 P1 T T ACW WDH ACH T P4.5 P4.4 Nonmuxed 16-bit READ ADDR[15:8] ADDR[7:0] DATA[7:0] P3.4–P4.3 P2 P1 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL EMIF READ DATA T T /RD /WR P4.4 P4.5 ACS RDS P3.4–P4.3 P2 P1 T RDH T ACW T ACH P4.4 P4.5 Figure 15.4. Non-multiplexed 16-bit MOVX Timing 162 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Nonmuxed 8-bit WRITE without Bank Select ADDR[15:8] ADDR[7:0] DATA[7:0] P2 P1 T T /WR /RD P4.5 P4.4 ACS P3.4-P4.3 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF WRITE DATA WDS P2 P1 T T ACW WDH ACH T P4.5 P4.4 Nonmuxed 8-bit READ without Bank Select ADDR[15:8] ADDR[7:0] DATA[7:0] P2 P1 P3.4-P4.3 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF READ DATA T T /RD /WR P4.4 P4.5 ACS RDS P2 P1 T RDH T ACW T ACH P4.4 P4.5 Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing Rev. 1.0 163 C8051F360/1/2/3/4/5/6/7/8/9 15.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Nonmuxed 8-bit WRITE with Bank Select ADDR[15:8] ADDR[7:0] DATA[7:0] P3.4–P4.3 P2 P1 T T /WR /RD P4.5 P4.4 ACS EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF WRITE DATA WDS P3.4–P4.3 P2 P1 T T ACW WDH ACH T P4.5 P4.4 Nonmuxed 8-bit READ with Bank Select ADDR[15:8] ADDR[7:0] DATA[7:0] P3.4–P4.3 P2 P1 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF READ DATA T T /RD /WR P4.4 P4.5 ACS RDS P3.4–P4.3 P2 P1 T RDH T ACW T ACH P4.4 P4.5 Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing 164 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15.6.2. Multiplexed Mode 15.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Muxed 16-bit WRITE ADDR[15:8] AD[7:0] P3.4–P4.3 P1 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH P3.4–P4.3 P1 EMIF WRITE DATA T ALEL ALE P0.0 T T ACS WDS P0.0 T T ACW WDH ACH T /WR /RD P4.5 P4.4 P4.5 P4.4 Muxed 16-bit READ ADDR[15:8] AD[7:0] P3.4–P4.3 P1 EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL T ALEH P3.4–P4.3 P1 EMIF READ DATA T ALEL T RDS T RDH ALE P0.0 P0.0 T /RD /WR P4.4 P4.5 ACS T ACW T ACH P4.4 P4.5 Figure 15.7. Multiplexed 16-bit MOVX Timing Rev. 1.0 165 C8051F360/1/2/3/4/5/6/7/8/9 15.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Muxed 8-bit WRITE Without Bank Select ADDR[15:8] AD[7:0] P1 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH P3.4–P4.3 EMIF WRITE DATA P1 T ALEL ALE P0.0 T T ACS WDS P0.0 T T ACW WDH ACH T /WR /RD P4.5 P4.4 P4.5 P4.4 Muxed 8-bit READ Without Bank Select ADDR[15:8] AD[7:0] P1 EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH P3.4–P4.3 EMIF READ DATA P1 T ALEL T RDS T RDH ALE P0.0 P0.0 T /RD /WR P4.4 P4.5 ACS T ACW T ACH P4.4 P4.5 Figure 15.8. Multiplexed 8-bit MOVX without Bank Select Timing 166 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 15.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Muxed 8-bit WRITE with Bank Select ADDR[15:8] AD[7:0] P3.4–P4.3 P1 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH P3.4–P4.3 P1 EMIF WRITE DATA T ALEL ALE P0.0 T T ACS WDS P0.0 T T ACW WDH ACH T /WR /RD P4.5 P4.4 P4.5 P4.4 Muxed 8-bit READ with Bank Select ADDR[15:8] AD[7:0] P3.4–P4.3 P1 EMIF ADDRESS (8 MSBs) from EMI0CN EMIF ADDRESS (8 LSBs) from R0 or R1 T ALEH P3.4–P4.3 P1 EMIF READ DATA T ALEL T RDS T RDH ALE P0.0 P0.0 T /RD P4.4 P4.5 ACS T ACW T ACH P4.4 P4.5 /WR Figure 15.9. Multiplexed 8-bit MOVX with Bank Select Timing Rev. 1.0 167 C8051F360/1/2/3/4/5/6/7/8/9 Table 15.2. AC Parameters for External Memory Interface Parameter TACS TACW TACH TALEH TALEL TWDS TWDH TRDS TRDH Description Address/Control Setup Time Address/Control Pulse Width Address/Control Hold Time Address Latch Enable High Time Address Latch Enable Low Time Write Data Setup Time Write Data Hold Time Read Data Setup Time Read Data Hold Time Min* 0 1 x TSYSCLK 0 1 x TSYSCLK 1 x TSYSCLK 1 x TSYSCLK 0 20 0 Max* 3 x TSYSCLK 16 x TSYSCLK 3 x TSYSCLK 4 x TSYSCLK 4 x TSYSCLK 19 x TSYSCLK 3 x TSYSCLK Units ns ns ns ns ns ns ns ns ns *Note: TSYSCLK is equal to one period of the device system clock (SYSCLK). 168 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 16. Oscillators The C8051F36x devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscillator can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as shown in Figure 16.1. The internal low-frequency oscillator can be enabled/disabled and calibrated using the OSCLCN register, as shown in SFR Definition 16.3. Both internal oscillators offer a selectable post-scaling feature. The system clock can be sourced by the external oscillator circuit, either internal oscillator, or the on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 16.1 on page 171 and Table 16.2 on page 172. OSCICL OSCICN IOSCEN IFRDY SUSPEND IFCN1 IFCN0 OSCLCN OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLF0 OSCLD1 OSCLD0 OSCLF OSCLD 000 001 SYSCLK 010 PLL 100 CLKDIV1 CLKDIV0 AV+ EN Option 2 VDD Option 1 XTAL1 Calibrated Internal Oscillator n XTAL2 XTAL2 Input Circuit OSC Option 3 XTAL2 Option 4 XTAL2 OSCLF Low Frequency Oscillator EN n OSCLD AGND XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 CLKSL2 CLKSL1 CLKSL0 XFCN2 XFCN1 XFCN0 OSCXCN CLKSEL Figure 16.1. Oscillator Diagram 16.1. Programmable Internal High-Frequency (H-F) Oscillator All devices include a calibrated internal high-frequency oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 16.1. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. Electrical specifications for the precision internal oscillator are given in Table 16.1 on page 171 and Table 16.2 on page 172. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. The divide value defaults to 8 following a reset. Rev. 1.0 169 C8051F360/1/2/3/4/5/6/7/8/9 16.1.1. Internal Oscillator Suspend Mode When software writes a logic ‘1’ to SUSPEND (OSCICN.5), the internal oscillator is suspended. If the system clock is derived from the internal oscillator, the input clock to the peripheral or CIP-51 will be stopped until one of the following events occur: • • • • • Port 0 Match Event. Port 1 Match Event. Port 2 Match Event. Comparator 0 enabled and output is logic ‘0’. Comparator 1 enabled and output is logic ‘0’. When one of the internal oscillator awakening events occur, the internal oscillator, CIP-51, and affected peripherals resume normal operation, regardless of whether the event also causes an interrupt. The CPU resumes execution at the instruction following the write to SUSPEND. Note: Before entering SUSPEND mode, SYSCLK should be switched to run off of the internal oscillator and not the PLL. When the CPU wakes due to the awakening event, the PLL must be reinitialized before switching back to it as the SYSCLK source. SFR Definition 16.1. OSCICL: Internal Oscillator Calibration. SFR Page: F SFR Address: 0xBF R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value Variable Bits 7–0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. The reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. 170 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.2. OSCICN: Internal Oscillator Control SFR Page: F SFR Address: 0xB7 R/W R R/W Bit5 R Bit4 R/W Bit3 R/W Bit2 R/W R/W Reset Value IOSCEN Bit7 IFRDY Bit6 SUSPEND Reserved Reserved Reserved IFCN1 Bit1 IFCN0 Bit0 11000000 IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. Bit 6: IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator not running at programmed frequency. 1: Internal Oscillator running at programmed frequency. Bits 5: SUSPEND: Internal Oscillator Suspend Enable Bit. Setting this bit to logic ‘1’ places the internal oscillator in SUSPEND mode. The internal oscillator resumes operation when one of the SUSPEND mode awakening events occur. Bits 4–2: RESERVED. Read = 000b. Must Write 000b. Bits 1–0: IFCN1-0: Internal Oscillator Frequency Control Bits. 00: Internal Oscillator is divided by 8. (default) 01: Internal Oscillator is divided by 4. 10: Internal Oscillator is divided by 2. 11: Internal Oscillator is divided by 1. Bit 7: Table 16.1. Internal High Frequency Oscillator Electrical Characteristics –40°C to +85°C unless otherwise specified. Parameter Conditions Calibrated Internal Oscillator Frequency Internal Oscillator Supply OSCICN.7 = 1 Current (from VDD) Power Supply Sensitivity Constant Temperature Temperature Sensitivity Constant Supply External Clock Frequency TXCH (External Clock High Time) TXCL (External Clock Low Time) Min 24 — — — 0 15 15 Typ 24.5 450 0.12 60 — — — Max 25 600 — — 30 — — Units MHz µA %/V ppm/°C MHz ns ns 16.2. Programmable Internal Low-Frequency (L-F) Oscillator All C8051F36x devices include a programmable low-frequency internal oscillator, which is calibrated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Definition 16.3). Additionally, the OSCLF bits (OSCLCN5:2) can be used to adjust the oscillator’s output frequency. Rev. 1.0 171 C8051F360/1/2/3/4/5/6/7/8/9 16.2.1. Calibrating the Internal L-F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency, when running from a known time base. When either Timer 2 or Timer 3 is configured for L-F Oscillator Capture Mode, a falling edge (Timer 2) or rising edge (Timer 3) of the low-frequency oscillator’s output will cause a capture event on the corresponding timer. As a capture event occurs, the current timer value (TMRnH:TMRnL) is copied into the timer reload registers (TMRnRLH:TMRnRLL). By recording the difference between two successive timer capture values, the low-frequency oscillator’s period can be calculated. The OSCLF bits can then be adjusted to produce the desired oscillator frequency. SFR Definition 16.3. OSCLCN: Internal L-F Oscillator Control SFR Page: F SFR Address: 0xAD R/W Bit7 R Bit6 R/W Bit5 R/W R/W R/W R/W R/W Reset Value OSCLEN OSCLRDY OSCLF3 OSCLF2 Bit4 OSCLF1 Bit3 OSCLF0 Bit2 OSCLD1 Bit1 OSCLD0 Bit0 00vvvv00 OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit 6: OSCLRDY: Internal L-F Oscillator Ready. 0: Internal L-F Oscillator frequency not stabilized. 1: Internal L-F Oscillator frequency stabilized. Bits 5–2: OSCLF[3:0]: Internal L-F Oscillator Frequency Control bits. Fine-tune control bits for the Internal L-F oscillator frequency. When set to 0000b, the L-F oscillator operates at its fastest setting. When set to 1111b, the L-F oscillator operates at its slowest setting. Bits 1–0: OSCLD[1:0]: Internal L-F Oscillator Divider Select. 00: Divide by 8 selected. 01: Divide by 4 selected. 10: Divide by 2 selected. 11: Divide by 1 selected. Bit 7: Table 16.2. Internal Low Frequency Oscillator Electrical Characteristics –40°C to +85°C unless otherwise specified. Conditions OSCLD = 11b 25 °C, VDD = 3.0 V, Oscillator Supply Current (from VDD) OSCLCN.7 = 1 Power Supply Sensitivity Constant Temperature Temperature Sensitivity Constant Supply Parameter Oscillator Frequency Min 72 — — — Typ 80 5.5 2.4 30 Max 88 10 — — Units kHz µA %/V ppm/°C 172 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 16.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/ resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 16.1. A 10 MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 pin as shown in Option 2, 3, or 4 of Figure 16.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see SFR Definition 16.5). Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.5 and P0.6 (C8051F360/3) or P0.2 and P0.3 (C8051F361/2/4/5/6/7/8/9) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.6 (C8051F360/3) or P0.3 (C8051F361/2/4/5/6/7/8/9) is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit; see Section “17.1. Priority Crossbar Decoder” on page 185 for Crossbar configuration. Additionally, when using the external oscillator circuit in crystal/resonator, capacitor, or RC mode, the associated Port pins should be configured as analog inputs. In CMOS clock mode, the associated pin should be configured as a digital input. See Section “17.2. Port I/O Initialization” on page 187 for details on Port input mode selection. 16.4. System Clock Selection The internal oscillator requires little start-up time, and may be enabled and selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use as the system clock. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. The PLL also requires time to lock onto the desired frequency, and the PLL Lock Flag (PLLLCK in register PLL0CN) is set to ‘1’ by hardware once the PLL is locked on the correct frequency. The CLKSL1-0 bits in register CLKSEL select which oscillator source generates the system clock. CLKSL1-0 must be set to ‘01’ for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals, such as the timers and PCA, when the internal oscillator or the PLL is selected as the system clock. The system clock may be switched on-the-fly between the internal and external oscillators or the PLL, so long as the selected oscillator source is enabled and settled. Rev. 1.0 173 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.4. CLKSEL: System Clock Selection SFR Page: F SFR Address: 0x8F R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W R/W R/W Bit0 Reset Value Reserved Reserved CLKDIV1 CLKDIV0 Reserved CLKSL2 Bit2 CLKSL1 Bit1 CLKSL0 00000000 Bits 7–6: RESERVED. Read = 00b. Must Write 00b. Bits 5–4: CLKDIV1-0: Output SYSCLK Divide Factor. These bits can be used to pre-divide SYSCLK before it is output to a port pin through the crossbar. 00: Output will be SYSCLK. 01: Output will be SYSCLK/2. 10: Output will be SYSCLK/4. 11: Output will be SYSCLK/8. See Section “17. Port Input/Output” on page 183 for more details about routing this output to a port pin. Bit 3: RESERVED. Read = 0b. Must Write 0b. Bits 2–0: CLKSL2–0: System Clock Source Select Bits. 000: SYSCLK derived from the high-frequency Internal Oscillator, and scaled as per the IFCN bits in OSCICN. 001: SYSCLK derived from the External Oscillator circuit. 010: SYSCLK derived from the low-frequency Internal Oscillator, and scaled as per the OSCLD bits in OSCLCN. 011: RESERVED. 100: SYSCLK derived from the PLL. 101-11x: RESERVED. 174 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.5. OSCXCN: External Oscillator Control SFR Page: F SFR Address: 0xB6 R Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R Bit3 R/W R/W R/W Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Reserved Bit 7: XFCN2 Bit2 XFCN1 Bit1 XFCN0 Bit0 00000000 XTLVLD: Crystal Oscillator Valid Flag. (Valid only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits 6–4: XOSCMD2–0: External Oscillator Mode Bits. 00x: External Oscillator circuit off. 010: External CMOS Clock Mode. 011: External CMOS Clock Mode with divide by 2 stage. 100: RC Oscillator Mode. 101: Capacitor Oscillator Mode. 110: Crystal Oscillator Mode. 111: Crystal Oscillator Mode with divide by 2 stage. Bit 3: RESERVED. Read = 0b. Write = don't care. Bits 2–0: XFCN2–0: External Oscillator Frequency Control Bits. 000-111: see table below: XFCN 000 001 010 011 100 101 110 111 Crystal (XOSCMD = 11x) f ≤ 32 kHz 32 kHz < f ≤ 84 kHz 84 kHz < f ≤ 225 kHz 225 kHz < f ≤ 590 kHz 590 kHz < f ≤ 1.5 MHz 1.5 MHz < f ≤ 4 MHz 4 MHz < f ≤ 10 MHz 10 MHz < f ≤ 30 MHz RC (XOSCMD = 100) f ≤ 25 kHz 25 kHz < f ≤ 50 kHz 50 kHz < f ≤ 100 kHz 100 kHz < f ≤ 200 kHz 200 kHz < f ≤ 400 kHz 400 kHz < f ≤ 800 kHz 800 kHz < f ≤ 1.6 MHz 1.6 MHz < f ≤ 3.2 MHz C (XOSCMD = 101) K Factor = 0.87 K Factor = 2.6 K Factor = 7.7 K Factor = 22 K Factor = 65 K Factor = 180 K Factor = 664 K Factor = 1590 CRYSTAL MODE (Circuit from Figure 16.1, Option 1; XOSCMD = 11x) Choose XFCN value to match crystal frequency. RC MODE (Circuit from Figure 16.1, Option 2; XOSCMD = 10x) Choose XFCN value to match frequency range: f = 1.23(103)/(R * C), where f = frequency of oscillation in MHz C = capacitor value in pF R = Pullup resistor value in kΩ C MODE (Circuit from Figure 16.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired: f = KF/(C * VDD), where f = frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins in pF VDD = Power Supply on MCU in Volts Rev. 1.0 175 C8051F360/1/2/3/4/5/6/7/8/9 16.5. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 16.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 16.5 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is enabled, the oscillator amplitude detection circuit requires a settle time to achieve proper bias. Waiting at least 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Step 2. Step 3. Step 4. Step 5. Step 6. Force the XTAL1 and XTAL2 pins low by writing 0's to the port latch. Configure XTAL1 and XTAL2 as analog inputs. Enable the external oscillator. Wait at least 1 ms. Poll for XTLVLD => '1'. Switch the system clock to the external oscillator. Note: Tuning-fork crystals may require additional settling time before XTLVLD returns a valid result. The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the XTAL1 and XTAL2 pins. Note: The load capacitance depends upon the crystal and the manufacturer. Please refer to the crystal data sheet when completing these calculations. For example, a tuning-fork crystal of 32.768 kHz with a recommended load capacitance of 12.5 pF should use the configuration shown in Figure 16.1, Option 1. The total value of the capacitors and the stray capacitance of the XTAL pins should equal 25 pF. With a stray capacitance of 3 pF per pin, the 22 pF capacitors yield an equivalent capacitance of 12.5 pF across the crystal, as shown in Figure 16.2. 22 pF XTAL 1 32.768 kHz 10 M Ω XTAL2 22 pF Figure 16.2. 32.768 kHz External Crystal Example Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 176 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 16.6. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 16.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 kΩ and C = 50 pF: f = 1.23(103)/RC = 1.23 (103)/[246 x 50] = 0.1 MHz = 100 kHz Referring to the table in SFR Definition 16.5, the required XFCN setting is 010b. Programming XFCN to a higher setting in RC mode will improve frequency accuracy at a slightly increased external oscillator supply current. 16.7. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 16.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and f = 75 kHz: f = KF / (C x VDD) 0.075 MHz = KF / (C x 3.0) Since the frequency of roughly 75 kHz is desired, select the K Factor from the table in SFR Definition 16.5 as KF = 7.7: 0.075 MHz = 7.7 / (C x 3.0) C x 3.0 = 7.7 / 0.075 MHz C = 102.6 / 3.0 pF = 34.2 pF Therefore, the XFCN value to use in this example is 010b. Rev. 1.0 177 C8051F360/1/2/3/4/5/6/7/8/9 16.8. Phase-Locked Loop (PLL) A Phase-Locked-Loop (PLL) is included, which is used to multiply the internal oscillator or an external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an output frequency between 25 MHz and 100 MHz, from a divided reference frequency between 5 MHz and 30 MHz. A block diagram of the PLL is shown in Figure 16.3. PLL0CN PLLSRC PLLEN PLLPWR PLLLCK PLL0FLT PLLICO1 PLLICO0 PLLLP3 PLLLP2 PLLLP1 PLLLP0 Internal Oscillator 0 ÷ 1 Divided Reference Clock External Oscillator Phase / Frequency Detection Loop Filter Current Controlled Oscillator PLL Clock Output ÷ PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 PLLN7 PLLN6 PLLN5 PLLN4 PLLN3 PLLN2 PLLN1 PLLN0 PLL0DIV PLL0MUL Figure 16.3. PLL Block Diagram 16.8.1. PLL Input Clock and Pre-divider The PLL circuitry can derive its reference clock from either the internal oscillator or an external clock source. The PLLSRC bit (PLL0CN.2) controls which clock source is used for the reference clock (see SFR Definition 16.6). If PLLSRC is set to ‘0’, the internal oscillator source is used. Note that the internal oscillator divide factor (as specified by bits IFCN1-0 in register OSCICN) will also apply to this clock. When PLLSRC is set to ‘1’, an external oscillator source will be used. The external oscillator should be active and settled before it is selected as a reference clock for the PLL circuit. The reference clock is divided down prior to the PLL circuit, according to the contents of the PLLM4-0 bits in the PLL Pre-divider Register (PLL0DIV), shown in SFR Definition 16.7. 16.8.2. PLL Multiplication and Output Clock The PLL circuitry will multiply the divided reference clock by the multiplication factor stored in the PLL0MUL register shown in SFR Definition 16.8. To accomplish this, it uses a feedback loop consisting of a phase/frequency detector, a loop filter, and a current-controlled oscillator (ICO). It is important to configure the loop filter and the ICO for the correct frequency ranges. The PLLLP3–0 bits (PLL0FLT.3–0) should be set according to the divided reference clock frequency. Likewise, the PLLICO1–0 bits (PLL0FLT.5–4) should be set according to the desired output frequency range. SFR Definition 16.9 describes the proper settings to use for the PLLLP3–0 and PLLICO1–0 bits. When the PLL is locked and stable at the desired frequency, the PLLLCK bit (PLL0CN.5) will be set to a ‘1’. The resulting PLL frequency will be set according to the equation: PLLN PLL Frequency = Reference Frequency × -------------PLLM Where “Reference Frequency” is the selected source clock frequency, PLLN is the PLL Multiplier, and PLLM is the PLL Pre-divider. 178 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 16.8.3. Powering on and Initializing the PLL To set up and use the PLL as the system clock after power-up of the device, the following procedure should be implemented: Step 1. Ensure that the reference clock to be used (internal or external) is running and stable. Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL. Step 3. Program the Flash read timing bits, FLRT (FLSCL.5–4) to the appropriate value for the new clock rate (see Section “13. Flash Memory” on page 135). Step 4. Enable power to the PLL by setting PLLPWR (PLL0CN.0) to ‘1’. Step 5. Program the PLL0DIV register to produce the divided reference frequency to the PLL. Step 6. Program the PLLLP3–0 bits (PLL0FLT.3–0) to the appropriate range for the divided reference frequency. Step 7. Program the PLLICO1–0 bits (PLL0FLT.5–4) to the appropriate range for the PLL output frequency. Step 8. Program the PLL0MUL register to the desired clock multiplication factor. Step 9. Wait at least 5 µs, to provide a fast frequency lock. Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’. Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’. Step 12. Switch the System Clock source to the PLL using the CLKSEL register. If the PLL characteristics need to be changed when the PLL is already running, the following procedure should be implemented: Step 1. The system clock should first be switched to either the internal oscillator or an external clock source that is running and stable, using the CLKSEL register. Step 2. Ensure that the reference clock to be used for the new PLL setting (internal or external) is running and stable. Step 3. Set the PLLSRC bit (PLL0CN.2) to select the new clock source for the PLL. Step 4. If moving to a faster frequency, program the Flash read timing bits, FLRT (FLSCL.5–4) to the appropriate value for the new clock rate (see Section “13. Flash Memory” on page 135). Step 5. Disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’. Step 6. Program the PLL0DIV register to produce the divided reference frequency to the PLL. Step 7. Program the PLLLP3–0 bits (PLL0FLT.3–0) to the appropriate range for the divided reference frequency. Step 8. Program the PLLICO1-0 bits (PLL0FLT.5–4) to the appropriate range for the PLL output frequency. Step 9. Program the PLL0MUL register to the desired clock multiplication factor. Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to ‘1’. Step 11. Poll PLLLCK (PLL0CN.4) until it changes from ‘0’ to ‘1’. Step 12. Switch the System Clock source to the PLL using the CLKSEL register. Step 13. If moving to a slower frequency, program the Flash read timing bits, FLRT (FLSCL.5–4) to the appropriate value for the new clock rate (see Section “13. Flash Memory” on page 135). Important Note: Cache reads, cache writes, and the prefetch engine should be disabled whenever the FLRT bits are changed to a lower setting. Rev. 1.0 179 C8051F360/1/2/3/4/5/6/7/8/9 To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’. Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLLPWR bits can be cleared at the same time. SFR Definition 16.6. PLL0CN: PLL Control SFR Page: F SFR Address: 0xB3 R/W R/W R/W R R/W R/W R/W R/W Bit0 Reset Value – Bit7 – Bit6 – Bit5 PLLLCK Bit4 Reserved Bit3 PLLSRC Bit2 PLLEN Bit1 PLLPWR 00000000 Bits 7–5: UNUSED. Read = 000b. Write = don’t care. Bit 4: PLLLCK: PLL Lock Flag. 0: PLL Frequency is not locked. 1: PLL Frequency is locked. Bit 3: RESERVED. Read = 0b. Must Write 0b. Bit 2: PLLSRC: PLL Reference Clock Source Select Bit. 0: PLL Reference Clock Source is Internal Oscillator. 1: PLL Reference Clock Source is External Oscillator. Bit 1: PLLEN: PLL Enable Bit. 0: PLL is held in reset. 1: PLL is enabled. PLLPWR must be ‘1’. Bit 0: PLLPWR: PLL Power Enable. 0: PLL bias generator is de-activated. No static power is consumed. 1: PLL bias generator is active. Must be set for PLL to operate. SFR Definition 16.7. PLL0DIV: PLL Pre-divider SFR Page: F SFR Address: 0xA9 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 – Bit6 – Bit5 PLLM4 Bit4 PLLM3 Bit3 PLLM2 Bit2 PLLM1 Bit1 PLLM0 Bit0 00000001 Bits 7–5: UNUSED. Read = 000b. Write = don’t care. Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider. These bits select the pre-divide value of the PLL reference clock. When set to any non-zero value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’, the reference clock will be divided by 32. 180 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 16.8. PLL0MUL: PLL Clock Scaler SFR Page: F SFR Address: 0xB1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value PLLN7 Bit7 PLLN6 Bit6 PLLN5 Bit5 PLLN4 Bit4 PLLN3 Bit3 PLLN2 Bit2 PLLN1 Bit1 PLLN0 Bit0 00000001 Bits 7–0: PLLN7–0: PLL Multiplier. These bits select the multiplication factor of the divided PLL reference clock. When set to any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set to ‘00000000b’, the multiplication factor will be equal to 256. SFR Definition 16.9. PLL0FLT: PLL Filter SFR Page: F SFR Address: 0xB2 R/W R/W R/W Bit5 R/W Bit4 R/W R/W R/W R/W Reset Value – Bit7 – Bit6 PLLICO1 PLLICO0 PLLLP3 Bit3 PLLLP2 Bit2 PLLLP1 Bit1 PLLLP0 Bit0 00110001 Bits 7–6: UNUSED. Read = 00b. Write = don’t care. Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits. Selection is based on the desired output frequency, according to the following table: PLL Output Clock 65–100 MHz 45–80 MHz 30–60 MHz 25–50 MHz PLLICO1-0 00 01 10 11 Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits. Selection is based on the divided PLL reference clock, according to the following table: Divided PLL Reference Clock 19–30 MHz 12.2–19.5 MHz 7.8–12.5 MHz 5–8 MHz All other states of PLLLP3–0 are RESERVED. PLLLP3-0 0001 0011 0111 1111 Rev. 1.0 181 C8051F360/1/2/3/4/5/6/7/8/9 Table 16.3. PLL Frequency Characteristics –40 to +85 °C unless otherwise specified. Parameter Input Frequency (Divided Reference Frequency) PLL Output Frequency Conditions Min 5 25 Typ Max 30 100* Units MHz MHz *Note: The maximum operating frequency of the C8051F366/7/8/9 is 50 MHz. Table 16.4. PLL Lock Timing Characteristics –40 to +85 °C unless otherwise specified Input Frequency 5 MHz 25 MHz Multiplier (Pll0mul) 20 13 16 9 12 6 10 5 4 2 3 2 2 1 2 1 Pll0flt Setting 0x0F 0x0F 0x1F 0x1F 0x2F 0x2F 0x3F 0x3F 0x01 0x01 0x11 0x11 0x21 0x21 0x31 0x31 Output Frequency 100 MHz 65 MHz 80 MHz 45 MHz 60 MHz 30 MHz 50 MHz 25 MHz 100 MHz 50 MHz 75 MHz 50 MHz 50 MHz 25 MHz 50 MHz 25 MHz Min Typ 202 115 241 116 258 112 263 113 42 33 48 17 42 33 60 25 Max Units µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs 182 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 17. Port Input/Output Digital and analog resources are available through up to 39 I/O pins. On the largest devices (C8051F360/3), port pins are organized as four byte-wide Ports and one 7-bit-wide Port. On the other devices (C8051F361/2/4/5/6/7/8/9), port pins are three byte-wide Ports and one partial port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; Port pins P0.0–P3.7 can be assigned to one of the internal digital resources as shown in Figure 17.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding Port latch, regardless of the Crossbar settings. The Crossbar assigns the selected internal digital resources to the I/O pins based on the peripheral priority order of the Priority Decoder (Figure 17.3 and Figure 17.4). The registers XBR0 and XBR1, defined in SFR Definition 17.1 and SFR Definition 17.2, are used to select internal digital functions. All Port I/Os are 5 V tolerant (refer to Figure 17.2 for the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3,4). Complete Electrical Specifications for Port I/O are given in Table 17.1 on page 201. XBR0, XBR1, PnSKIP Registers P0MASK, P0MATCH P1MASK, P1MATCH, P2MASK, P2MATCH Registers Priority Decoder Highest Priority UART SPI (Internal Digital Signals) SMBus CP0 CP1 Outputs SYSCLK PCA Lowest Priority T0, T1 7 8 2 8 P0 (P0.0-P0.7) 8 P1 (Port Latches) (P1.0-P1.7) 8 P2 (P2.0-P2.7) 8 P3 (P3.0-P3.7) P3 I/O Cells 2 4 2 8 P0 I/O Cells PnMDOUT, PnMDIN Registers P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.7 3.5–3.7 available on C8051F360/3 3.1–3.4 available on C8051F360/1/3/4/6/8 Digital Crossbar 4 8 P1 I/O Cells 8 P2 I/O Cell Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3) Rev. 1.0 183 C8051F360/1/2/3/4/5/6/7/8/9 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE VIO VIO (WEAK) PORT PAD PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT G ND Figure 17.2. Port I/O Cell Block Diagram 184 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 17.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 17.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which will be assigned to specific port pins (P0.1 and P0.2 in the C8051F360/3 devices, P0.4 and P0.5 in the C8051F361/2/4/5/6/7/8/9 devices). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that are to be used for analog input, dedicated functions, or GPIO. Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the Crossbar, its corresponding PnSKIP bit should be set. This applies to the port pins associated with the external oscillator, VREF, external CNVSTR signal, IDA0, and any selected ADC or comparator inputs. The Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. Figure 17.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP, P3SKIP = 0x00); Figure 17.4 shows the Crossbar Decoder priority with the P1.0 and P1.1 pins skipped (P1SKIP = 0x03). P0 CNVSTR SF Signals (32- and 28pin) XTAL1 XTAL2 VREF IDA0 P1 P2 P3 P3.5-P3.7 P3.1-P3.4 available available on on 48-pin 32/48-pin only only VREF PIN I/O TX0 RX0 TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A /SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI T0 T1 0 1 2 3 IDA0 SF Signals (48-pin) 4 5 6 CNVSTR 7 0 XTAL1 XTAL2 ALE 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 (32-pin and 28-pin packages) (48-pin package) (*4-Wire SPI Only) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0SKIP[0:7] P1SKIP[0:7] P2SKIP[0:7] P3SKIP[0:7] Figure 17.3. Crossbar Priority Decoder with No Pins Skipped Rev. 1.0 185 C8051F360/1/2/3/4/5/6/7/8/9 P0 CNVSTR SF Signals (32- and 28pin) XTAL1 XTAL2 VREF IDA0 P1 P2 P3 P3.5-P3.7 P3.1-P3.4 available available on on 48-pin 32/48-pin only only CNVSTR 7 0 XTAL1 5 VREF PIN I/O TX0 RX0 TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A /SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 CEX5 ECI T0 T1 0 1 2 3 IDA0 4 SF Signals (48-pin) XTAL2 6 ALE 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 (32-pin and 28-pin packages) (48-pin package) (*4-Wire SPI Only) 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P0SKIP[0:7] P1SKIP[0:7] P2SKIP[0:7] P3SKIP[0:7] Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.1 (C8051F360/3) or P0.4 (C8051F361/2/4/5/6/7/8/9); UART RX0 is always assigned to P0.2 (C8051F360/3) or P0.5 (C8051F361/2/4/5/6/7/8/9). Standard Port I/Os appear contiguously starting at P0.0 after prioritized functions and skipped pins are assigned. Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. 186 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 17.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). Step 4. Assign Port pins to desired peripherals using the XBRn registers. Step 5. Enable the Crossbar (XBARE = ‘1’). All Port pins must be configured as either analog or digital inputs. Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins configured as digital inputs may still be used by analog peripherals; however, this practice is not recommended. Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a ‘1’ indicates a digital input, and a ‘0’ indicates an analog input. All pins default to digital inputs on reset. See SFR Definition 17.4 for the PnMDIN register details. The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMDOUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is required even for the digital resources selected in the XBRn registers, and is not automatic. The only exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the PnMDOUT settings. When the WEAKPUD bit in XBR1 is ‘0’, a weak pullup is enabled for all Port I/O configured as open-drain. WEAKPUD does not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an output that is driving a ‘0’ and for pins configured for analog input mode to avoid unnecessary power dissipation. Registers XBR0 and XBR1 must be loaded with the appropriate values to select the digital I/O functions required by the design. Setting the XBARE bit in XBR1 to ‘1’ enables the Crossbar. Until the Crossbar is enabled, the external pins remain as standard Port I/O (in input mode), regardless of the XBRn Register settings. For given XBRn Register settings, one can determine the I/O pin-out using the Priority Decode Table; as an alternative, the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. The Crossbar must be enabled to use Port pins as standard Port I/O in output mode. Port output drivers are disabled while the Crossbar is disabled. Rev. 1.0 187 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0 SFR Page: F SFR Address: 0xE1 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CP1AE Bit7 CP1E Bit6 CP0AE Bit5 CP0E Bit4 SYSCKE Bit3 SMB0E Bit2 SPI0E Bit1 URT0E Bit0 00000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. 1: CP1 routed to Port pin. CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. 1: Asynchronous CP0 routed to Port pin. CP0E: Comparator0 Output Enable 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. SYSCKE: /SYSCLK Output Enable 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. The divide factor is determined by the CLKDIV1–0 bits in register CLKSEL (See Section Section “16. Oscillators” on page 169). SMB0E: SMBus I/O Enable 0: SMBus I/O unavailable at Port pins. 1: SMBus I/O routed to Port pins. SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins. URT0E: UART I/O Output Enable 0: UART I/O unavailable at Port pin. 1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5 (C8051F361/2/4/5/6/7/8/9). 188 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1 SFR Page: SFR Address: F 0xE2 R/W Bit7 R/W Bit6 R/W R/W R/W R/W Bit2 R/W R/W Bit0 Reset Value WEAKPUD XBARE T1E Bit5 T0E Bit4 ECIE Bit3 PCA0ME Bit1 00000000 Bit 7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). 1: Weak Pullups disabled. Bit 6: XBARE: Crossbar Enable. 0: Crossbar disabled. 1: Crossbar enabled. Bit 5: T1E: T1 Enable 0: T1 unavailable at Port pin. 1: T1 routed to Port pin. Bit 4: T0E: T0 Enable 0: T0 unavailable at Port pin. 1: T0 routed to Port pin. Bit 3: ECIE: PCA0 External Counter Input Enable 0: ECI unavailable at Port pin. 1: ECI routed to Port pin. Bits 2–0: PCA0ME: PCA Module I/O Enable Bits. 000: All PCA I/O unavailable at Port pins. 001: CEX0 routed to Port pin. 010: CEX0, CEX1 routed to Port pins. 011: CEX0, CEX1, CEX2 routed to Port pins. 100: CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins. 111: Reserved. Rev. 1.0 189 C8051F360/1/2/3/4/5/6/7/8/9 17.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0-P3 are accessed through corresponding special function registers (SFRs) that are both byte-addressable and bit-addressable. Port 4 (C8051F360/3 only) uses an SFR which is byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the value of the latch register (not the pin) is read, modified, and written back to the SFR. In addition to performing general purpose I/O, P0, P1, and P2 can generate a port match event if the logic levels of the Port’s input pins match a software controlled value. A port match event is generated if (P0 & P0MASK) does not equal (P0MATCH & P0MASK), if (P1 & P1MASK) does not equal (P1MATCH & P1MASK), or if (P2 & P2MASK) does not equal (P2MATCH & P2MASK). This allows Software to be notified if a certain change or pattern occurs on P0, P1, or P2 input pins regardless of the XBRn settings. A port match event can cause an interrupt if EMAT (EIE2.1) is set to '1' or cause the internal oscillator to awaken from SUSPEND mode. See Section “16.1.1. Internal Oscillator Suspend Mode” on page 170 for more information. SFR Definition 17.3. P0: Port0 SFR Page: all pages SFR Address: 0x80 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W P0.7 Bit7 P0.6 Bit6 P0.5 Bit5 P0.4 Bit4 P0.3 Bit3 P0.2 Bit2 P0.1 Bit1 P0.0 Bit0 11111111 Bits 7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P0MDIN. Directly reads Port pin when configured as digital input. 0: P0.n pin is logic low. 1: P0.n pin is logic high. 190 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.4. P0MDIN: Port0 Input Mode SFR Page: F SFR Address: 0xF1 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: Analog Input Configuration Bits for P0.7-P0.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P0.n pin is configured as an analog input. 1: Corresponding P0.n pin is not configured as an analog input. SFR Definition 17.5. P0MDOUT: Port0 Output Mode SFR Page: F SFR Address: 0xA4 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic ‘0’. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT. Rev. 1.0 191 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.6. P0SKIP: Port0 Skip SFR Page: F SFR Address: 0xD4 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. SFR Definition 17.7. P0MAT: Port0 Match SFR Page: 0 SFR Address: 0xF3 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: P0MAT[7:0]: Port0 Match Value. These bits control the value that unmasked P0 Port pins are compared against. A Port Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK). SFR Definition 17.8. P0MASK: Port0 Mask SFR Page: 0 SFR Address: 0xF4 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P0MASK[7:0]: Port0 Mask Value. These bits select which Port pins will be compared to the value stored in P0MAT. 0: Corresponding P0.n pin is ignored and cannot cause a Port Match event. 1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT. 192 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.9. P1: Port1 SFR Page: all pages SFR Address: 0x90 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W P1.7 Bit7 P1.6 Bit6 P1.5 Bit5 P1.4 Bit4 P1.3 Bit3 P1.2 Bit2 P1.1 Bit1 P1.0 Bit0 11111111 Bits 7–0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port pin when configured as digital input. 0: P1.n pin is logic low. 1: P1.n pin is logic high. SFR Definition 17.10. P1MDIN: Port1 Input Mode SFR Page: F SFR Address: 0xF2 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: Analog Input Configuration Bits for P1.7-P1.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P1.n pin is configured as an analog input. 1: Corresponding P1.n pin is not configured as an analog input. Rev. 1.0 193 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.11. P1MDOUT: Port1 Output Mode SFR Page: F SFR Address: 0xA5 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic ‘0’. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. SFR Definition 17.12. P1SKIP: Port1 Skip SFR Page: F SFR Address: 0xD5 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P1.n pin is not skipped by the Crossbar. 1: Corresponding P1.n pin is skipped by the Crossbar. SFR Definition 17.13. P1MAT: Port1 Match SFR Page: 0 SFR Address: 0xE1 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: P1MAT[7:0]: Port1 Match Value. These bits control the value that unmasked P0 Port pins are compared against. A Port Match event is generated if (P1 & P1MASK) does not equal (P1MAT & P1MASK). 194 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.14. P1MASK: Port1 Mask SFR Page: 0 SFR Address: 0xE2 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P1MASK[7:0]: Port1 Mask Value. These bits select which Port pins will be compared to the value stored in P1MAT. 0: Corresponding P1.n pin is ignored and cannot cause a Port Match event. 1: Corresponding P1.n pin is compared to the corresponding bit in P1MAT. SFR Definition 17.15. P2: Port2 SFR Page: all pages SFR Address: 0xA0 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W P2.7 Bit7 P2.6 Bit6 P2.5 Bit5 P2.4 Bit4 P2.3 Bit3 P2.2 Bit2 P2.1 Bit1 P2.0 Bit0 11111111 Bits 7–0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. Rev. 1.0 195 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.16. P2MDIN: Port2 Input Mode SFR Page: F SFR Address: 0xF3 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: Analog Input Configuration Bits for P2.7-P2.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P2.n pin is configured as an analog input. 1: Corresponding P2.n pin is not configured as an analog input. SFR Definition 17.17. P2MDOUT: Port2 Output Mode SFR Page: F SFR Address: 0xA6 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: Output Configuration Bits for P2.7-P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic ‘0’. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. 196 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.18. P2SKIP: Port2 Skip SFR Page: F SFR Address: 0xD6 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. SFR Definition 17.19. P2MAT: Port2 Match SFR Page: 0 SFR Address: 0xB1 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: P2MAT[7:0]: Port2 Match Value. These bits control the value that unmasked P2 Port pins are compared against. A Port Match event is generated if (P2 & P2MASK) does not equal (P2MAT & P2MASK). SFR Definition 17.20. P2MASK: Port2 Mask SFR Page: 0 SFR Address: 0xB2 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P2MASK[7:0]: Port2 Mask Value. These bits select which Port pins will be compared to the value stored in P2MAT. 0: Corresponding P2.n pin is ignored and cannot cause a Port Match event. 1: Corresponding P2.n pin is compared to the corresponding bit in P2MAT. Rev. 1.0 197 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.21. P3: Port3 SFR Page: all pages SFR Address: 0xB0 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R/W P3.7 Bit7 P3.6 Bit6 P3.5 Bit5 P3.4 Bit4 P3.3 Bit3 P3.2 Bit2 P3.1 Bit1 P3.0 Bit0 11111111 Bits 7–0: P3.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. SFR Definition 17.22. P3MDIN: Port3 Input Mode SFR Page: F SFR Address: 0xF4 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 11111111 Bits 7–0: Analog Input Configuration Bits for P3.7-P3.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding P3.n pin is configured as an analog input. 1: Corresponding P3.n pin is not configured as an analog input. 198 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.23. P3MDOUT: Port3 Output Mode SFR Page: F SFR Address: 0xAF R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: Output Configuration Bits for P3.7-P3.0 (respectively): ignored if corresponding bit in register P3MDIN is logic ‘0’. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. SFR Definition 17.24. P3SKIP: Port3 Skip SFR Page: F SFR Address: 0xD7 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: P3SKIP[7:0]: Port3 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as analog inputs (for ADC or Comparator) or used as special functions (VREF input, external oscillator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P3.n pin is not skipped by the Crossbar. 1: Corresponding P3.n pin is skipped by the Crossbar. Rev. 1.0 199 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 17.25. P4: Port4 SFR Page: all pages SFR Address: 0xB5 R R/W R/W R/W R/W R/W R/W R/W Reset Value – Bit7 P4.6 Bit6 P4.5 Bit5 P4.4 Bit4 P4.3 Bit3 P4.2 Bit2 P4.1 Bit1 P4.0 Bit0 01111111 Bit 7: UNUSED. Read = 0b. Write = don’t care. Bits 6–0: P4.[6:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P4MDOUT.n bit = 0). Read - Directly reads Port pin. 0: P4.n pin is logic low. 1: P4.n pin is logic high. SFR Definition 17.26. P4MDOUT: Port4 Output Mode SFR Page: F SFR Address: 0xAE R R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value – Bit7 00000000 Bit 7: UNUSED. Read = 0b. Write = don’t care. Bits 6–0: Output Configuration Bits for P4.6-P4.0 (respectively). 0: Corresponding P4.n Output is open-drain. 1: Corresponding P4.n Output is push-pull. 200 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 17.1. Port I/O DC Electrical Characteristics VDD = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions IOH = –3 mA, Port I/O push-pull IOH = –10 mA, Port I/O push-pull IOL = 8.5 mA Min VDD – 0.7 VDD – 0.1 — — — — 2.0 — — — Typ — — VDD – 0.8 — — 1.0 — — — 25 Max — — — 0.6 0.1 — — 0.8 ±1 50 Units V Output High Voltage IOH = –10 µA, Port I/O push-pull Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current IOL = 10 µA IOL = 25 mA V V V µA Weak Pullup Off Weak Pullup On, VIN = 0 V Rev. 1.0 201 C8051F360/1/2/3/4/5/6/7/8/9 18. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data. Data can be transferred at up to 1/10th of the system clock as a master or slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple masters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation. Three SFRs are associated with the SMBus: SMB0CF configures the SMBus; SMB0CN controls the status of the SMBus; and SMB0DAT is the data register, used for both transmitting and receiving SMBus data and slave addresses. SMB0CN MTSSAAAS AXTTCRC I SMAOKBK TO RL ED QO RE S T SMB0CF E I BESSSS N N U XMMMM SHSTBBBB M YHTFCC B OOT S S LEE10 D 00 01 10 11 SMBUS CONTROL LOGIC Interrupt Request Arbitration SCL Synchronization SCL Generation (Master Mode) SDA Control Data Path IRQ Generation Control T0 Overflow T1 Overflow TMR2H Overflow TMR2L Overflow SCL FILTER SCL Control SDA Control N C R O S S B A R SDA Port I/O SMB0DAT 76543210 FILTER N Figure 18.1. SMBus Block Diagram 202 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 18.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum. 18.2. SMBus Configuration Figure 18.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Master Device Slave Device 1 Slave Device 2 SDA SCL Figure 18.2. Typical SMBus Configuration 18.3. SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one device as the Master in a system; any device who transmits a START and a slave address becomes the master for the duration of that transfer. A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 18.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high SCL. Rev. 1.0 203 C8051F360/1/2/3/4/5/6/7/8/9 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic ‘1’ to indicate a "READ" operation and cleared to logic ‘0’ to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 18.3 illustrates a typical SMBus transaction. SCL SDA SLA6 SLA5-0 R/W D7 D6-0 START Slave Address + R/W ACK Data Byte NACK STOP Figure 18.3. SMBus Transaction 18.3.1. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section “18.3.4. SCL High (SMBus Free) Timeout” on page 205). In the event that two or more devices attempt to begin a transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. 18.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency. 18.3.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detecting the timeout condition. When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to 204 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable and re-enable) the SMBus in the event of an SCL low timeout. 18.3.4. SCL High (SMBus Free) Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a Master START, the START will be generated following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only implementation. 18.4. Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting control for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent features: • • • • • • • Byte-wise serial data transfers Clock signal generation on SCL (Master Mode only) and SDA data synchronization Timeout/bus error recognition, as defined by the SMB0CF configuration register START/STOP timing, detection, and generation Bus arbitration Interrupt generation Status information SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting, this interrupt is generated after the ACK cycle so that software may read the received ACK value; when receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value. See Section “18.5. SMBus Transfer Modes” on page 213 for more details on transmission sequences. Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section “18.4.2. SMB0CN Control Register” on page 209; Table 18.4 provides a quick SMB0CN decoding reference. SMBus configuration options include: • • • • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) SDA setup and hold time extensions Slave event enable/disable Clock source selection These options are selected in the SMB0CF register, as described in Section “18.4.1. SMBus Configuration Register” on page 206. Rev. 1.0 205 C8051F360/1/2/3/4/5/6/7/8/9 18.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however, the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of the current transfer). Table 18.1. SMBus Clock Source Selection SMBCS1 0 0 1 1 SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or when the Free Timeout detection is enabled. When operating as a master, overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 18.1. Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer configuration is covered in Section “21. Timers” on page 247. 1 T HighMin = T LowMin = --------------------------------------------f ClockSourceOverflow Equation 18.1. Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 18.1. When the interface is operating as a master (and SCL is not driven or extended by any other devices on the bus), the typical SMBus bit rate is approximated by Equation 18.2. f ClockSourceOverflow BitRate = --------------------------------------------3 Equation 18.2. Typical SMBus Bit Rate 206 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Figure 18.4 shows the typical SCL generation described by Equation 18.2. Notice that THIGH is typically twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices). The bit rate when operating as a master will never exceed the limits defined by equation Equation 18.1. Timer Source Overflows SCL TLow THigh SCL High Timeout Figure 18.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high. The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 18.2 shows the minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz. Table 18.2. Minimum SDA Setup and Hold Times EXTHOLD 0 1 Minimum SDA Setup Time Tlow – 4 system clocks or 1 system clock + s/w delay* 11 system clocks Minimum SDA Hold Time 3 system clocks 12 system clocks *Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w delay occurs between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in the same write that defines the outgoing ACK value, s/w delay is zero. With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts (see Section “18.3.3. SCL Low Timeout” on page 204). The SMBus interface will force Timer 3 to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the SMBus. SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see Figure 18.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an interrupt will be generated, and STO will be set). Rev. 1.0 207 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 18.1. SMB0CF: SMBus Clock/Configuration SFR Page: all pages SFR Address: 0xC1 R/W R/W R R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Reset Value ENSMB Bit7 INH Bit6 BUSY Bit5 EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 Bit0 00000000 Bit 7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. Bit 6: INH: SMBus Slave Inhibit. When this bit is set to logic ‘1’, the SMBus does not generate an interrupt when slave events occur. This effectively removes the SMBus slave from the bus. Master Mode interrupts are not affected. 0: SMBus Slave Mode enabled. 1: SMBus Slave Mode inhibited. Bit 5: BUSY: SMBus Busy Indicator. This bit is set to logic ‘1’ by hardware when a transfer is in progress. It is cleared to logic ‘0’ when a STOP or free-timeout is sensed. Bit 4: EXTHOLD: SMBus Setup and Hold Time Extension Enable. This bit controls the SDA setup and hold times according to: 0: SDA Extended Setup and Hold Times disabled. 1: SDA Extended Setup and Hold Times enabled. Bit 3: SMBTOE: SMBus SCL Timeout Detection Enable. This bit enables SCL low timeout detection. If set to logic ‘1’, the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is configured to Split Mode, only the High Byte of the timer is held in reload while SCL is high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3 interrupt service routine should reset SMBus communication. Bit 2: SMBFTE: SMBus Free Timeout Detection Enable. When this bit is set to logic ‘1’, the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. Bits 1–0: SMBCS1–SMBCS0: SMBus Clock Source Selection. These two bits select the SMBus clock source, which is used to generate the SMBus bit rate. The selected device should be configured according to Equation 18.1. SMBCS1 0 0 1 1 SMBCS0 0 1 0 1 SMBus Clock Source Timer 0 Overflow Timer 1 Overflow Timer 2 High Byte Overflow Timer 2 Low Byte Overflow 208 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 18.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 18.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines. MASTER and TXMODE indicate the master/slave state and transmit/receive modes, respectively. STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus interrupt. STA and STO are also used to generate START and STOP conditions when operating as a master. Writing a ‘1’ to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a ‘1’ to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will be generated. As a receiver, writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the value received on the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave events will be ignored until the next START is detected. The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error condition. ARBLOST is cleared by hardware each time SI is cleared. The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see Table 18.3 for more details. Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 18.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 18.4 for SMBus status decoding using the SMB0CN register. Rev. 1.0 209 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 18.2. SMB0CN: SMBus Control SFR Page: all pages SFR Address: 0xC0 (bit addressable) R/W R/W R Bit3 R Bit2 R/W R/W Reset Value R Bit7 R Bit6 MASTER TXMODE STA Bit5 STO Bit4 ACKRQ ARBLOST ACK Bit1 SI Bit0 00000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. TXMODE: SMBus Transmit Mode Indicator. This read-only bit indicates when the SMBus is operating as a transmitter. 0: SMBus in Receiver Mode. 1: SMBus in Transmitter Mode. STA: SMBus Start Flag. Write: 0: No Start generated. 1: When operating as a master, a START condition is transmitted if the bus is free (If the bus is not free, the START is transmitted after a STOP is received or a timeout is detected). If STA is set by software as an active Master, a repeated START will be generated after the next ACK cycle. Read: 0: No Start or repeated Start detected. 1: Start or repeated Start detected. STO: SMBus Stop Flag. Write: 0: No STOP condition is transmitted. 1: Setting STO to logic ‘1’ causes a STOP condition to be transmitted after the next ACK cycle. When the STOP condition is generated, hardware clears STO to logic ‘0’. If both STA and STO are set, a STOP condition is transmitted followed by a START condition. Read: 0: No Stop condition detected. 1: Stop condition detected (if in Slave Mode) or pending (if in Master Mode). ACKRQ: SMBus Acknowledge Request This read-only bit is set to logic ‘1’ when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value. ARBLOST: SMBus Arbitration Lost Indicator. This read-only bit is set to logic ‘1’ when the SMBus loses arbitration while operating as a transmitter. A lost arbitration while a slave indicates a bus error condition. ACK: SMBus Acknowledge Flag. This bit defines the out-going ACK level and records incoming ACK levels. It should be written each time a byte is received (when ACKRQ=1), or read after each byte is transmitted. 0: A "not acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). 1: An "acknowledge" has been received (if in Transmitter Mode) OR will be transmitted (if in Receiver Mode). SI: SMBus Interrupt Flag. This bit is set by hardware under the conditions listed in Table 18.3. SI must be cleared by software. While SI is set, SCL is held low and the SMBus is stalled. 210 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 18.3. Sources for Hardware Changes to SMB0CN Bit MASTER Set by Hardware When: • A START is generated. • START is generated. • SMB0DAT is written before the start of an SMBus frame. • A START followed by an address byte is received. • A STOP is detected while addressed as a slave. • Arbitration is lost due to a detected STOP. • A byte has been received and an ACK response value is needed. • A repeated START is detected as a MASTER when STA is low (unwanted repeated START). • SCL is sensed low while attempting to generate a STOP or repeated START condition. • SDA is sensed low while transmitting a ‘1’ (excluding ACK bits). • The incoming ACK value is low (ACKNOWLEDGE). • A START has been generated. • Lost arbitration. • A byte has been transmitted and an ACK/NACK received. • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • Must be cleared by software. • A pending STOP is generated. • After each ACK cycle. TXMODE STA STO ACKRQ ARBLOST • Each time SI is cleared. ACK • The incoming ACK value is high (NOT ACKNOWLEDGE). SI • Must be cleared by software. Rev. 1.0 211 C8051F360/1/2/3/4/5/6/7/8/9 18.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic ‘0’, as the interface may be in the process of shifting a byte of data into or out of the register. Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data or address in SMB0DAT. SFR Definition 18.3. SMB0DAT: SMBus Data SFR Page: all pages SFR Address: 0xC2 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: SMB0DAT: SMBus Data. The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial interface or a byte that has just been received on the SMBus serial interface. The CPU can read from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to logic ‘1’. The serial data in the register remains stable as long as the SI flag is set. When the SI flag is not set, the system may be in the process of shifting data in/out and the CPU should not attempt to access this register. 212 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 18.5. SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end of all SMBus byte frames; however, note that the interrupt is generated before the ACK cycle when operating as a receiver, and after the ACK cycle when operating as a transmitter. 18.5.1. Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic ‘0’ (WRITE). The master then transmits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 18.5 shows a typical Master Transmitter sequence. Two transmit data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. S SLA W A Data Byte A Data Byte A P Interrupt Interrupt Interrupt Interrupt Received by SMBus Interface Transmitted by SMBus Interface S = START P = STOP A = ACK W = WRITE SLA = Slave Address Figure 18.5. Typical Master Transmitter Sequence Rev. 1.0 213 C8051F360/1/2/3/4/5/6/7/8/9 18.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic ‘1’ (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit generates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if SMB0DAT is written while an active Master Receiver. Figure 18.6 shows a typical Master Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. S SLA R A Data Byte A Data Byte N P Interrupt Interrupt Interrupt Interrupt S = START P = STOP A = ACK N = NACK R = READ SLA = Slave Address Received by SMBus Interface Transmitted by SMBus Interface Figure 18.6. Typical Master Receiver Sequence 214 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 18.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected. If the received slave address is acknowledged, zero or more data bytes are received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 18.7 shows a typical Slave Receiver sequence. Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. Interrupt S SLA W A Data Byte A Data Byte A P Interrupt Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Figure 18.7. Typical Slave Receiver Sequence Rev. 1.0 215 C8051F360/1/2/3/4/5/6/7/8/9 18.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until a START is detected. If the received slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared (Note: an error condition may be generated if SMB0DAT is written following a received NACK while in Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter interrupt. Figure 18.8 shows a typical Slave Transmitter sequence. Two transmitted data bytes are shown, though any number of bytes may be transmitted. Notice that the ‘data byte transferred’ interrupts occur after the ACK cycle in this mode. Interrupt S SLA R A Data Byte A Data Byte N P Interrupt Received by SMBus Interface Transmitted by SMBus Interface Interrupt Interrupt S = START P = STOP N = NACK R = READ SLA = Slave Address Figure 18.8. Typical Slave Transmitter Sequence 216 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 18.6. SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown response options are only the typical responses; application-specific procedures are allowed as long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to the SMBus specification. Table 18.4. SMBus Status Decoding Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STA STo 0 0 1 0 1 1 0 0 Values Written ACK X X X X X X X X 217 ACK 1110 0 0 0 0 X A master START was generated. 0 Load slave address + R/W into SMB0DAT. 0 1 0 0 0 1 1 0 Master Transmitter Set STA to restart transfer. A master data or address byte was transmitted; NACK received. Abort transfer. Load next data byte into SMB0DAT. 1100 0 0 1 A master data or address byte was transmitted; ACK received. End transfer with STOP. End transfer with STOP and start another transfer. Send repeated START. Switch to Master Receiver Mode (clear SI without writing new data to SMB0DAT). Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 18.4. SMBus Status Decoding (Continued) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STA STo 0 1 1 0 0 0 0 0 0 0 0 Values Written ACK 1 0 0 1 0 1 0 X X X X ACK Acknowledge received byte; Read SMB0DAT. Send NACK to indicate last byte, and send STOP. Send NACK to indicate last byte, and send STOP followed by START. Master Receiver Send ACK followed by repeated START. 1000 1 0 X A master data byte was received; Send NACK to indicate last ACK requested. byte, and send repeated START. Send ACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). Send NACK and switch to Master Transmitter Mode (write to SMB0DAT before clearing SI). Slave Transmitter 0 0100 0 0 0101 0 0 0 1 X 0 1 X X A slave byte was transmitted; NACK received. A slave byte was transmitted; ACK received. A Slave byte was transmitted; error detected. A STOP was detected while an addressed Slave Transmitter. No action required (expecting STOP condition). Load SMB0DAT with next data byte to transmit. No action required (expecting Master to end transfer). No action required (transfer complete). 0 0 1 1 1 0 0 0 0 0 0 218 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 18.4. SMBus Status Decoding (Continued) Values Read Mode ARBLOST ACKRQ Status Vector Current SMbus State Typical Response Options STA STo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Values Written ACK 1 0 1 0 0 X X 0 X X X 1 0 0 0 219 ACK 1 0 A slave address was received; X ACK requested. Acknowledge received address. Do not acknowledge received address. Acknowledge received address. 0 0 0 0 1 0010 1 1 Lost arbitration as master; slave X address received; ACK requested. Do not acknowledge received address. Reschedule failed transfer; do not acknowledge received address. Slave Receiver 0 1 0001 0 0 1 1 0 1 X X X X Lost arbitration while attempting a Abort failed transfer. repeated START. Reschedule failed transfer. Lost arbitration while attempting a No action required (transfer STOP. complete/aborted). A STOP was detected while an addressed slave receiver. No action required (transfer complete). 0 1 0 0 0 1 0 0 0 1 Lost arbitration due to a detected Abort transfer. STOP. Reschedule failed transfer. Acknowledge received byte; Read SMB0DAT. Do not acknowledge received byte. 1 0000 1 0 A slave byte was received; ACK X requested. 1 X Lost arbitration while transmitting Abort failed transfer. a data byte as master. Reschedule failed transfer. Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 19. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “19.1. Enhanced Baud Rate Generation” on page 221). Received data buffering allows UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0 always access the Transmit register. Reads of SBUF0 always access the buffered Receive register; it is not possible to read data from the Transmit register. With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive complete). SFR Bus Write to SBUF TB8 SET D CLR Q SBUF (TX Shift) TX Crossbar Zero Detector Stop Bit Start Tx Clock Shift Data Tx Control Tx IRQ Send SCON SMODE MCE REN TB8 RB8 TI RI UART Baud Rate Generator TI RI Serial Port Interrupt Port I/O Rx IRQ Rx Clock Rx Control Start Shift 0x1FF RB8 Load SBUF Input Shift Register (9 bits) Load SBUF SBUF (RX Latch) Read SBUF SFR Bus RX Crossbar Figure 19.1. UART0 Block Diagram 220 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 19.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 19.2), which is not useraccessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Timer 1 TL1 Overflow UART 2 TX Clock TH1 Start Detected RX Timer Overflow 2 RX Clock Figure 19.2. UART0 Baud Rate Logic Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “21.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 249). The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an external input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 19.1-A and Equation 19.1-B. A) B) 1 UartBaudRate = -- × T1_Overflow_Rate 2 T1 CLK T1_Overflow_Rate = ------------------------256 – TH1 Equation 19.1. UART0 Baud Rate Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “21. Timers” on page 247. A quick reference for typical baud rates and system clock frequencies is given in Table 19.1 through Table 19.6. Note that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1. Rev. 1.0 221 C8051F360/1/2/3/4/5/6/7/8/9 19.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. RS-232 RS-232 LEVEL XLTR TX RX C8051Fxxx OR TX TX MCU RX RX C8051Fxxx Figure 19.3. UART Interconnect Diagram 19.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2). Data transmission begins when software writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic ‘1’. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic ‘0’, and if MCE0 is logic ‘1’, the stop bit must be logic ‘1’. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF0 receive register and the following overrun data bits are lost. If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. MARK SPACE BIT TIMES START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT SAMPLING Figure 19.4. 8-Bit UART Timing Diagram 222 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 19.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored. Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to ‘1’. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: (1) RI0 must be logic ‘0’, and (2) if MCE0 is logic ‘1’, the 9th bit must be logic ‘1’ (when MCE0 is logic ‘0’, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to ‘1’. If the above conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to ‘1’. A UART0 interrupt will occur if enabled when either TI0 or RI0 is set to ‘1’. MARK SPACE BIT TIMES START BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP BIT BIT SAMPLING Figure 19.5. 9-Bit UART Timing Diagram Rev. 1.0 223 C8051F360/1/2/3/4/5/6/7/8/9 19.3. Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic ‘1’; in a data byte, the ninth bit is always set to logic ‘0’. Setting the MCE0 bit (SCON0.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic ‘1’ (RB80 = 1) signifying an address byte has been received. In the UART interrupt handler, software will compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE0 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave resets its MCE0 bit to ignore all transmissions until it receives the next address byte. Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s). Master Device RX TX Slave Device RX TX Slave Device RX TX Slave Device RX TX V+ Figure 19.6. UART Multi-Processor Mode Interconnect Diagram 224 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 19.1. SCON0: Serial Port 0 Control SFR Page: all pages SFR Address: 0x98 (bit addressable) R/W R/W R/W R/W R/W R/W Reset Value R/W R S0MODE Bit7 – Bit6 MCE0 Bit5 REN0 Bit4 TB80 Bit3 RB80 Bit2 TI0 Bit1 RI0 Bit0 01000000 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. UNUSED. Read = 1b. Write = don’t care. MCE0: Multiprocessor Communication Enable. The function of this bit is dependent on the Serial Port 0 Operation Mode. S0MODE = 0: Checks for valid stop bit. 0: Logic level of stop bit is ignored. 1: RI0 will only be activated if stop bit is logic level ‘1’. S0MODE = 1: Multiprocessor Communications Enable. 0: Logic level of ninth bit is ignored. 1: RI0 is set and an interrupt is generated only when the ninth bit is logic ‘1’. REN0: Receive Enable. This bit enables/disables the UART receiver. 0: UART0 reception disabled. 1: UART0 reception enabled. TB80: Ninth Transmission Bit. The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not used in 8-bit UART Mode. Set or cleared by software as required. RB80: Ninth Receive Bit. RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1. TI0: Transmit Interrupt Flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. RI0: Receive Interrupt Flag. Set to ‘1’ by hardware when a byte of data has been received by UART0 (set at the STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software. Rev. 1.0 225 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 19.2. SBUF0: Serial (UART0) Port Data Buffer SFR Page: all pages SFR Address: 0x99 R/W Bit7 R/W Bit6 R/W Bit5 R/W Bit4 R/W Bit3 R/W Bit2 R/W Bit1 R/W Bit0 Reset Value 00000000 Bits 7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB–LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. 226 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Oscillator Frequency: 24.5 MHz Target Baud Rate (bps) 230400 115200 57600 SYSCLK from Internal Osc. 28800 14400 9600 2400 1200 Baud Rate % Error –0.32% –0.32% 0.15% –0.32% 0.15% –0.32% –0.32% 0.15% Oscillator Divide Factor 106 212 426 848 1704 2544 10176 20448 Timer Clock SCA1–SCA0 T1M1 1 Source (pre-scale select) SYSCLK SYSCLK SYSCLK SYSCLK/4 SYSCLK/12 SYSCLK/12 SYSCLK/48 SYSCLK/48 XX2 XX XX 01 00 00 10 10 1 1 1 0 0 0 0 0 Timer 1 Reload Value (hex) 0xCB 0x96 0x2B 0x96 0xB9 0x96 0x96 0x2B Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 227 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 57600 28800 14400 Baud Rate % Error –0.47% 0.45% –0.01% 0.45% –0.01% 0.15% 0.45% –0.01% –0.47% –0.47% 0.45% Frequency: 25.0 MHz Oscilla- Timer Clock SCA1–SCA0 Timer 1 T1M1 1 tor Divide Source Reload (pre-scale select) Factor Value (hex) 108 SYSCLK 1 0xCA XX2 218 434 872 1736 2608 10464 20832 432 864 1744 SYSCLK SYSCLK SYSCLK/4 SYSCLK/4 EXTCLK/8 SYSCLK/48 SYSCLK/48 EXTCLK/8 EXTCLK/8 EXTCLK/8 XX XX 01 01 11 10 10 11 11 11 1 1 0 0 0 0 0 0 0 0 0x93 0x27 0x93 0x27 0x5D 0x93 0x27 0xE5 0xCA 0x93 SYSCLK from Internal Osc., SYSCLK and Timer Clock Timer Clock from External Osc. from External Osc. 9600 0.15% 2608 EXTCLK/8 11 0 0x5D Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. 228 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 22.1184 MHz Oscilla- Timer Clock SCA1–SCA0 Timer 1 T1M1 1 tor Divide Source Reload (pre-scale select) Factor Value (hex) 96 SYSCLK 1 0xD0 XX2 192 384 768 1536 2304 9216 18432 96 192 384 768 1536 2304 SYSCLK SYSCLK SYSCLK/12 SYSCLK/12 SYSCLK/12 SYSCLK/48 SYSCLK/48 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 XX XX 00 00 00 10 10 11 11 11 11 11 11 1 1 0 0 0 0 0 0 0 0 0 0 0 0xA0 0x40 0xE0 0xC0 0xA0 0xA0 0x40 0xFA 0xF4 0xE8 0xD0 0xA0 0x70 SYSCLK from Internal Osc., SYSCLK and Timer Clock Timer Clock from External Osc. from External Osc. Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 229 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 18.432 MHz Oscilla- Timer Clock SCA1–SCA0 Timer 1 T1M1 1 tor Divide Source Reload (pre-scale select) Factor Value (hex) 80 SYSCLK 1 0xD8 XX2 160 320 640 1280 1920 7680 15360 80 160 320 640 1280 1920 SYSCLK SYSCLK SYSCLK/4 SYSCLK/4 SYSCLK/12 SYSCLK/48 SYSCLK/48 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 XX XX 01 01 00 10 10 11 11 11 11 11 11 1 1 0 0 0 0 0 0 0 0 0 0 0 0xB0 0x60 0xB0 0x60 0xB0 0xB0 0x60 0xFB 0xF6 0xEC 0xD8 0xB0 0x88 230 SYSCLK from Internal Osc., SYSCLK and Timer Clock Timer Clock from External Osc. from External Osc. Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate % Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 11.0592 MHz Oscilla- Timer Clock SCA1–SCA0 Timer 1 T1M1 1 tor Divide Source Reload (pre-scale select) Factor Value (hex) 48 SYSCLK 1 0xE8 XX2 96 192 384 768 1152 4608 9216 48 96 192 384 768 1152 SYSCLK SYSCLK SYSCLK SYSCLK/12 SYSCLK/12 SYSCLK/12 SYSCLK/48 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 XX XX XX 00 00 00 10 11 11 11 11 11 11 1 1 1 0 0 0 0 0 0 0 0 0 0 0xD0 0xA0 0x40 0xE0 0xD0 0x40 0xA0 0xFD 0xFA 0xF4 0xE8 0xD0 0xB8 SYSCLK from Internal Osc., SYSCLK and Timer Clock Timer Clock from External Osc. from External Osc. Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 231 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHz Oscillator Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 Baud Rate% Error 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% Frequency: 3.6864 MHz Oscilla- Timer Clock SCA1–SCA0 Timer 1 T1M1 1 tor Divide Source Reload (pre-scale select) Factor Value (hex) 16 SYSCLK 1 0xF8 XX2 32 64 128 256 384 1536 3072 16 32 64 128 256 384 SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK/12 SYSCLK/12 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 EXTCLK/8 XX XX XX XX XX 00 00 11 11 11 11 11 11 1 1 1 1 1 0 0 0 0 0 0 0 0 0xF0 0xE0 0xC0 0x80 0x40 0xC0 0x80 0xFF 0xFE 0xFC 0xF8 0xF0 0xE8 232 SYSCLK from Internal Osc., SYSCLK and Timer Clock Timer Clock from External Osc. from External Osc. Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 Table 19.7. Timer Settings for Standard Baud Rates Using the PLL Frequency: 50.0 MHz Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 2400 Baud Rate % Error 0.45% –0.01% 0.45% –0.01% 0.22% –0.01% –0.01% Oscillator Divide Factor 218 434 872 1736 3480 5208 20832 Timer Clock SCA1-SCA0 T1M1 1 Source (pre-scale select) SYSCLK SYSCLK SYSCLK/4 SYSCLK/4 SYSCLK/12 SYSCLK/12 SYSCLK/48 XX2 XX 01 01 00 00 10 1 1 0 0 0 0 0 Timer 1 Reload Value (hex) 0x93 0x27 0x93 0x27 0x6F 0x27 0x27 Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Table 19.8. Timer Settings for Standard Baud Rates Using the PLL Frequency: 100.0 MHz Target Baud Rate (bps) 230400 115200 57600 28800 14400 9600 Baud Rate % Error –0.01% 0.45% –0.01% 0.22% –0.47% 0.45% Oscillator Divide Factor 434 872 1736 3480 6912 10464 Timer Clock SCA1-SCA0 T1M1 1 Source (pre-scale select) SYSCLK SYSCLK/4 SYSCLK/4 SYSCLK/12 SYSCLK/48 SYSCLK/48 XX2 01 01 00 10 10 1 0 0 0 0 0 Timer 1 Reload Value (hex) 0x27 0x93 0x27 0x6F 0xB8 0x93 Notes: 1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1. 2. X = Don’t care. Rev. 1.0 233 C8051F360/1/2/3/4/5/6/7/8/9 20. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. SFR Bus SPI0CKR SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 SPI0CFG SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT SPI0CN SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN SYSCLK Clock Divide Logic SPI CONTROL LOGIC Data Path Control Pin Interface Control SPI IRQ Tx Data MOSI SPI0DAT Transmit Data Buffer Pin Control Logic SCK Shift Register 76543210 Rx Data MISO C R O S S B A R Port I/O Receive Data Buffer NSS Write SPI0DAT Read SPI0DAT SFR Bus Figure 20.1. SPI Block Diagram 234 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 20.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 20.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master, MOSI is driven by the MSB of the shift register in both 3- and 4-wire mode. 20.1.2. Master In, Slave Out (MISO) The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a high-impedance state when the SPI module is disabled and when the SPI operates in 4-wire mode as a slave that is not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register. 20.1.3. Serial Clock (SCK) The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines. SPI0 generates this signal when operating as a master. The SCK signal is ignored by a SPI slave when the slave is not selected (NSS = 1) in 4-wire slave mode. 20.1.4. Slave Select (NSS) The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the SPI0CN register. There are three possible modes that can be selected with these bits: 1. NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point communication between a master and one slave. 2. NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a 1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can be used on the same SPI bus. 3. NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an output. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should only be used when operating SPI0 as a master device. See Figure 20.2, Figure 20.3, and Figure 20.4 for typical connection diagrams of the various operational modes. Note that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device. See Section “17. Port Input/Output” on page 183 for general purpose port I/O and crossbar information. Rev. 1.0 235 C8051F360/1/2/3/4/5/6/7/8/9 20.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic ‘1’ at the end of the transfer. If interrupts are enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on the MOSI line, the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading SPI0DAT. When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circumstances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins. Figure 20.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 20.3 shows a connection diagram between a master device in 3-wire master mode and a slave device. 4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-purpose I/O pins. Figure 20.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. 236 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 NSS GPIO MISO MOSI SCK NSS Master Device 1 MISO MOSI SCK GPIO Master Device 2 Figure 20.2. Multiple-Master Mode Connection Diagram Master Device MISO MOSI SCK MISO MOSI SCK Slave Device Figure 20.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master Device GPIO MISO MOSI SCK NSS MISO MOSI SCK NSS Slave Device MISO MOSI SCK NSS Slave Device Figure 20.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram Rev. 1.0 237 C8051F360/1/2/3/4/5/6/7/8/9 20.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic ‘1’, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer. When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic ‘0’, and disabled when NSS is logic ‘1’. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer. Figure 20.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and reenabling SPI0 with the SPIEN bit. Figure 20.3 shows a connection diagram between a slave device in 3wire slave mode and a master device. 20.4. SPI0 Interrupt Sources When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic ‘1’: All of the following bits must be cleared by software. 1. The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic ‘1’ at the end of each byte transfer. This flag can occur in all SPI0 modes. 2. The Write Collision Flag, WCOL (SPI0CN.6) is set to logic ‘1’ if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes. 3. The Mode Fault Flag MODF (SPI0CN.5) is set to logic ‘1’ when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits in SPI0CN are set to logic ‘0’ to disable SPI0 and allow another master device to access the bus. 4. The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic ‘1’ when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost. 238 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 20.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are shown in Figure 20.5. For slave mode, the clock and data relationships are shown in Figure 20.6 and Figure 20.7. Note that CKPHA must be set to ‘0’ on both the master and slave SPI when communicating between two of the following devices: C8051F04x, C8051F06x, C8051F12x, C8051F31x, C8051F32x, C8051F33x, and C8051F36x. The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 20.3 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock. SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=0) SCK (CKPOL=1, CKPHA=1) MISO/MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (Must Remain High in Multi-Master Mode) Figure 20.5. Master Mode Data/Clock Timing Rev. 1.0 239 C8051F360/1/2/3/4/5/6/7/8/9 SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) 240 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 20.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. SFR Definition 20.1. SPI0CFG: SPI0 Configuration SFR Page: all pages SFR Address: 0xA1 R R/W R/W R/W R R R R Reset Value SPIBSY Bit7 MSTEN Bit6 CKPHA Bit5 CKPOL Bit4 SLVSEL Bit3 NSSIN Bit2 SRMT Bit1 RXBMT Bit0 00000111 Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: SPIBSY: SPI Busy (read only). This bit is set to logic ‘1’ when a SPI transfer is in progress (Master or slave Mode). MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data centered on first edge of SCK period.* 1: Data centered on second edge of SCK period.* CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. SLVSEL: Slave Selected Flag (read only). This bit is set to logic ‘1’ whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic ‘0’ when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSSIN: NSS Instantaneous Pin Input (read only). This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. SRMT: Shift Register Empty (Valid in Slave Mode, read only). This bit will be set to logic ‘1’ when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic ‘0’ when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. NOTE: SRMT = 1 when in Master Mode. RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only). This bit will be set to logic ‘1’ when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic ‘0’. NOTE: RXBMT = 1 when in Master Mode. *Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 20.1 for timing parameters. Rev. 1.0 241 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 20.2. SPI0CN: SPI0 Control SFR Page: all pages SFR Address: 0xF8 (bit addressable) R/W R/W Bit4 R/W Bit3 R/W Bit2 R R/W Reset Value R/W R/W SPIF Bit7 WCOL Bit6 MODF Bit5 RXOVRN NSSMD1 NSSMD0 TXBMT Bit1 SPIEN Bit0 00000110 SPIF: SPI0 Interrupt Flag. This bit is set to logic ‘1’ by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. Bit 6: WCOL: Write Collision Flag. This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software. Bit 5: MODF: Mode Fault Flag. This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software. Bit 4: RXOVRN: Receive Overrun Flag (Slave Mode only). This bit is set to logic ‘1’ by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. Bits 3–2: NSSMD1–NSSMD0: Slave Select Mode. Selects between the following NSS operation modes: (See Section 20.2 and Section 20.3). 00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. Bit 1: TXBMT: Transmit Buffer Empty. This bit will be set to logic ‘0’ when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic ‘1’, indicating that it is safe to write a new byte to the transmit buffer. Bit 0: SPIEN: SPI0 Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. Bit 7: 242 Rev. 1.0 C8051F360/1/2/3/4/5/6/7/8/9 SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate SFR Page: all pages SFR Address: 0xA2 R/W R/W R/W R/W R/W R/W R/W R/W Reset Value SCR7 Bit7 SCR6 Bit6 SCR5 Bit5 SCR4 Bit4 SCR3 Bit3 SCR2 Bit2 SCR1 Bit1 SCR0 Bit0 00000000 Bits 7–0: SCR7–SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register. SYSCLK f SCK = -----------------------------------------------2 × ( SPI 0 CKR + 1 ) for 0